mirror of
https://github.com/irmen/prog8.git
synced 2024-06-26 07:29:32 +00:00
renamed cx16.VERA_IRQ_LINE_L to VERA_IRQLINE_L and added VERA_SCANLINE_L, to align with official register naming.
Also added a multi-irq example for the X16 to show the updated irq handler semantics.
This commit is contained in:
Irmen de Jong
parent
08ac459a41
commit
ba67fd318b
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@ -238,7 +238,8 @@ cx16 {
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&ubyte VERA_CTRL = VERA_BASE + $0005
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&ubyte VERA_IEN = VERA_BASE + $0006
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&ubyte VERA_ISR = VERA_BASE + $0007
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&ubyte VERA_IRQ_LINE_L = VERA_BASE + $0008
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&ubyte VERA_IRQLINE_L = VERA_BASE + $0008 ; write only
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&ubyte VERA_SCANLINE_L = VERA_BASE + $0008 ; read only
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&ubyte VERA_DC_VIDEO = VERA_BASE + $0009 ; DCSEL= 0
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&ubyte VERA_DC_HSCALE = VERA_BASE + $000A ; DCSEL= 0
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&ubyte VERA_DC_VSCALE = VERA_BASE + $000B ; DCSEL= 0
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@ -931,6 +932,7 @@ asmsub cleanup_at_exit() {
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}
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asmsub set_irq(uword handler @AY) clobbers(A) {
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; Sets the handler for the VSYNC interrupt, and enable that interrupt.
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%asm {{
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sta _modified+1
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sty _modified+2
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@ -939,9 +941,8 @@ asmsub set_irq(uword handler @AY) clobbers(A) {
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sta cx16.CINV
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lda #>_irq_handler
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sta cx16.CINV+1
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lda cx16.VERA_IEN
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ora #%00000001 ; enable the vsync irq
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sta cx16.VERA_IEN
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lda #1
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tsb cx16.VERA_IEN ; enable the vsync irq
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cli
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rts
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@ -974,8 +975,8 @@ asmsub restore_irq() clobbers(A) {
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lda _orig_irqvec+1
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sta cx16.CINV+1
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lda cx16.VERA_IEN
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and #%11110000 ; disable all Vera IRQs
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ora #%00000001 ; enable only the vsync Irq
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and #%11110000 ; disable all Vera IRQs but the vsync
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ora #%00000001
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sta cx16.VERA_IEN
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cli
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rts
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@ -984,6 +985,7 @@ _orig_irqvec .word 0
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}
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asmsub set_rasterirq(uword handler @AY, uword rasterpos @R0) clobbers(A) {
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; Sets the handler for the LINE interrupt, and enable (only) that interrupt.
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%asm {{
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sta _modified+1
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sty _modified+2
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@ -991,8 +993,8 @@ asmsub set_rasterirq(uword handler @AY, uword rasterpos @R0) clobbers(A) {
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ldy cx16.r0+1
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sei
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lda cx16.VERA_IEN
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and #%11110000 ; clear other IRQs
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ora #%00000010 ; enable the line (raster) irq
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and #%11110000 ; disable all irqs but the line(raster) one
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ora #%00000010
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sta cx16.VERA_IEN
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lda cx16.r0
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ldy cx16.r0+1
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@ -1010,9 +1012,8 @@ _raster_irq_handler
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_modified jsr $ffff ; modified
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jsr sys.restore_prog8_internals
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; end irq processing - don't use kernal's irq handling
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lda cx16.VERA_ISR
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ora #%00000010
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sta cx16.VERA_ISR ; clear Vera line irq status
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lda #2
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tsb cx16.VERA_ISR ; clear Vera line irq status
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ply
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plx
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pla
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@ -1022,7 +1023,7 @@ _modified jsr $ffff ; modified
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asmsub set_rasterline(uword line @AY) {
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%asm {{
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sta cx16.VERA_IRQ_LINE_L
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sta cx16.VERA_IRQLINE_L
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lda cx16.VERA_IEN
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and #%01111111
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sta cx16.VERA_IEN
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@ -117,6 +117,7 @@ class TestCompilerOnExamplesCx16: FunSpec({
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"kefrenbars",
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"keyboardhandler",
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"mandelbrot",
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"multi-irq",
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"plasma",
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"rasterbars",
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"snow",
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@ -2,7 +2,8 @@
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TODO
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====
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- use TRB/TSB instructions more on the x16 such as when ack vera irq bits
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- use TRB/TSB instructions more on the x16 such as when ack vera irq bits cx16.VERA_ISR |= 4
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xx |= %0001000, xx &= %1110111
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- [on branch: shortcircuit] investigate McCarthy evaluation again? this may also reduce code size perhaps for things like if a>4 or a<2 ....
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@ -23,6 +24,8 @@ Compiler:
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- Currently "320*240/8/8" gives integer overflow, so: allow constant integer subexpressions to contain out of range integers (>65535 etc) as long as the final constant value is within byte/word range.
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- Multidimensional arrays and chained indexing, purely as syntactic sugar over regular arrays.
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- fix the other cases of "TODO index could also be a binexpr" (in AssignmentAsmGen), but these are for float arrays so rarely used.
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- make a form of "manual generics" possible like: varsub routine(T arg)->T where T is expanded to a specific type
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(this is already done hardcoded for several of the builtin functions)
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- [much work:] more support for (64tass) SEGMENTS ?
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- (What, how, isn't current BSS support enough?)
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86
examples/cx16/multi-irq.p8
Normal file
86
examples/cx16/multi-irq.p8
Normal file
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@ -0,0 +1,86 @@
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%import palette
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%import textio
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%import syslib
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%zeropage basicsafe
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; Example that shows a way to handle multiple IRQ sources on the X16.
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; Currently only Vera interrupts are supported.
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main {
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sub start() {
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sys.set_rasterline(150)
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sys.set_irq(&irq.master_handler) ; ..will just enable vsync..
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cx16.VERA_IEN |= 2 ; .. so also enable line irq here.
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txt.print("\n\n\nisr installed\n")
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txt.print("red = vsync\n")
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txt.print("green = first line irq\n")
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txt.print("blue = second line irq\n")
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}
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}
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irq {
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sub master_handler() -> bool {
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ubyte irqsrc = cx16.VERA_ISR
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ror(irqsrc)
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if_cs {
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vsync_irq()
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return true ; run system IRQ handler. It will ack the vsync IRQ as well.
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}
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ror(irqsrc)
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if_cs {
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line_irq()
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cx16.VERA_ISR |= 2 ; ack the irq
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return false
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}
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ror(irqsrc)
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if_cs {
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sprcol_irq()
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cx16.VERA_ISR |= 4 ; ack the irq
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return false
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}
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ror(irqsrc)
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if_cs {
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aflow_irq()
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; note: AFLOW can only be cleared by filling the audio FIFO for at least 1/4. Not via the ISR bit.
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return false
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}
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; weird irq
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return false
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}
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sub vsync_irq() {
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cx16.save_vera_context()
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palette.set_color(0, $f00)
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repeat 1000 {
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cx16.r0++
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}
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palette.set_color(0, $000)
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cx16.restore_vera_context()
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}
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sub line_irq() {
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cx16.save_vera_context()
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if cx16.VERA_SCANLINE_L==150 {
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palette.set_color(0, $0f0)
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sys.set_rasterline(200) ; prepare next line irq
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} else {
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palette.set_color(0, $00f)
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sys.set_rasterline(150) ; back to first line irq
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}
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repeat 500 {
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cx16.r0++
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}
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palette.set_color(0, $000)
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cx16.restore_vera_context()
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}
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sub sprcol_irq() {
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; nothing here yet
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}
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sub aflow_irq() {
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; nothing here yet
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}
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}
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@ -5,17 +5,79 @@
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main {
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sub start() {
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sys.set_rasterirq(&handler, 200)
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txt.print("installed\n")
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sys.set_rasterline(150)
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sys.set_irq(&irq.master_handler)
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cx16.VERA_IEN |= 2 ; also enable line irq
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txt.print("\n\n\nisr installed\n")
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txt.print("red = vsync\n")
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txt.print("green = first line irq\n")
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txt.print("blue = second line irq\n")
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}
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}
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irq {
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sub master_handler() -> bool {
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ubyte irqsrc = cx16.VERA_ISR
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ror(irqsrc)
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if_cs {
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vsync_irq()
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return true ; run system IRQ handler. It will ack the vsync IRQ as well.
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}
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ror(irqsrc)
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if_cs {
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line_irq()
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cx16.VERA_ISR |= 2 ; ack the irq
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return false
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}
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ror(irqsrc)
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if_cs {
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sprcol_irq()
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cx16.VERA_ISR |= 4 ; ack the irq
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return false
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}
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ror(irqsrc)
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if_cs {
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aflow_irq()
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; note: AFLOW can only be cleared by filling the audio FIFO for at least 1/4. Not via the ISR bit.
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return false
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}
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; weird irq
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return false
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}
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sub handler() -> bool {
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sub vsync_irq() {
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cx16.save_vera_context()
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palette.set_color(0, $f00)
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repeat 1000 {
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cx16.r0++
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}
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palette.set_color(0, $000)
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cx16.restore_vera_context()
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}
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return true
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sub line_irq() {
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cx16.save_vera_context()
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if cx16.VERA_SCANLINE_L==150 {
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palette.set_color(0, $0f0)
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sys.set_rasterline(200) ; prepare next line irq
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} else {
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palette.set_color(0, $00f)
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sys.set_rasterline(150) ; back to first line irq
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}
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repeat 500 {
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cx16.r0++
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}
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palette.set_color(0, $000)
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cx16.restore_vera_context()
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}
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sub sprcol_irq() {
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; nothing here yet
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}
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sub aflow_irq() {
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; nothing here yet
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}
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}
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