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https://github.com/irmen/prog8.git
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vm: use shift-one instructions in codegen
This commit is contained in:
Irmen de Jong
parent
14e36f1362
commit
bacba629a5
@ -762,4 +762,6 @@ class CodeGen(internal val program: PtProgram,
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builtinFuncGen.translate(call, resultRegister)
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internal fun isZero(expression: PtExpression): Boolean = expression is PtNumber && expression.number==0.0
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internal fun isOne(expression: PtExpression): Boolean = expression is PtNumber && expression.number==1.0
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}
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@ -363,24 +363,33 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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private fun operatorShiftRight(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int, signed: Boolean): VmCodeChunk {
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val code = VmCodeChunk()
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// TODO if shift is 1, use ASR/LSR instruction instead of multishift
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val leftResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, leftResultReg, -1)
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code += translateExpression(binExpr.right, rightResultReg, -1)
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val opc = if(signed) Opcode.ASRN else Opcode.LSRN
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code += VmCodeInstruction(opc, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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if(codeGen.isOne(binExpr.right)) {
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code += translateExpression(binExpr.left, resultRegister, -1)
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val opc = if (signed) Opcode.ASR else Opcode.LSR
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code += VmCodeInstruction(opc, vmDt, reg1 = resultRegister)
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} else {
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val leftResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, leftResultReg, -1)
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code += translateExpression(binExpr.right, rightResultReg, -1)
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val opc = if (signed) Opcode.ASRN else Opcode.LSRN
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code += VmCodeInstruction(opc, vmDt, reg1 = resultRegister, reg2 = leftResultReg, reg3 = rightResultReg)
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}
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return code
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}
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private fun operatorShiftLeft(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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// TODO if shift is 1, use LSL instruction instead of multishift
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val leftResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, leftResultReg, -1)
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code += translateExpression(binExpr.right, rightResultReg, -1)
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code += VmCodeInstruction(Opcode.LSLN, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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if(codeGen.isOne(binExpr.right)){
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code += translateExpression(binExpr.left, resultRegister, -1)
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code += VmCodeInstruction(Opcode.LSL, vmDt, reg1=resultRegister)
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} else {
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val leftResultReg = codeGen.vmRegisters.nextFree()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, leftResultReg, -1)
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code += translateExpression(binExpr.right, rightResultReg, -1)
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code += VmCodeInstruction(Opcode.LSLN, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg)
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}
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return code
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}
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@ -3,7 +3,7 @@ TODO
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For next release
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^^^^^^^^^^^^^^^^
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- vm: use more instructions in codegen: shift one
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- vm: expressiongen: use resultRegister arg instead of allocating new leftResultReg
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- vm: use more instructions in codegen: branching
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- vm: add more instructions operating directly on memory instead of only registers?
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- in-place modifiying functions (rol, ror, ..) don't accept a memory address but require a memory-read expression. that is weird.
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100
examples/test.p8
100
examples/test.p8
@ -7,63 +7,61 @@
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; NOTE: meant to test to virtual machine output target (use -target vitual)
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main {
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; ubyte value = 42
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;
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; sub inline_candidate() -> ubyte {
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; return math.sin8u(value)
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; }
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;
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; sub add(ubyte first, ubyte second) -> ubyte {
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; return first + second
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; }
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;
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; sub mul(ubyte first, ubyte second) -> ubyte {
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; return first * second
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; }
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ubyte value = 42
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sub inline_candidate() -> ubyte {
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return math.sin8u(value)
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}
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sub add(ubyte first, ubyte second) -> ubyte {
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return first + second
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}
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sub mul(ubyte first, ubyte second) -> ubyte {
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return first * second
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}
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sub start() {
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uword[] arrayuw = [1111,2222,3333,4444]
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txt.print_uw(arrayuw[1])
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txt.nl()
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arrayuw[1] = 9999
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txt.print_uw(arrayuw[1])
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txt.nl()
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arrayuw[1] = 0
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txt.print_uw(arrayuw[1])
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txt.nl()
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float[] array = [1.1, 2.2, 3.3, 4.4]
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floats.print_f(array[1])
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ubyte @shared value = inline_candidate()
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value = %01011100
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byte @shared svalue = 99
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svalue = -svalue
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@($5000) = not @($5000)
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sys.set_carry()
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rol(value)
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rol(@($5000))
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txt.print_ub(value)
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txt.nl()
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array[1] = 99.99
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floats.print_f(array[1])
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sys.set_carry()
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ror(value)
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ror(@($5000))
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txt.print_ub(value)
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txt.nl()
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array[1] = 0
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floats.print_f(array[1])
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txt.nl()
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; ubyte value = inline_candidate()
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; byte svalue = 99
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; svalue = -svalue
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; @($5000) = not @($5000)
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; rol(value)
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; rol(@($5000))
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; ror(value)
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; ror(@($5000))
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; rol2(value)
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; rol2(@($5000))
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; ror2(value)
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; ror2(@($5000))
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; @($5000) <<= 1
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; @($5000) >>= 1
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; value <<= 1
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; value >>= 1
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; @($5000) <<= 3
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; @($5000) >>= 3
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; value <<= 3
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; value >>= 3
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; txt.print_ub(value)
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; txt.nl()
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value = %01011100
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sys.set_carry()
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rol2(value)
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rol2(@($5000))
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txt.print_ub(value)
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txt.nl()
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sys.clear_carry()
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ror2(value)
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ror2(@($5000))
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txt.print_ub(value)
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txt.nl()
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@($5000) <<= 1
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@($5000) >>= 1
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value <<= 1
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value >>= 1
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txt.print_ub(value)
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txt.nl()
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@($5000) <<= 3
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@($5000) >>= 3
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value <<= 3
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value >>= 3
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txt.print_ub(value)
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txt.nl()
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; txt.print_ub(inline_candidate())
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; txt.nl()
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@ -124,8 +124,8 @@ asr reg1 - shift reg1 right by 1 bits (signe
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lsl reg1 - shift reg1 left by 1 bits + set Carry to shifted bit
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ror reg1 - rotate reg1 right by 1 bits, not using carry + set Carry to shifted bit
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roxr reg1 - rotate reg1 right by 1 bits, using carry + set Carry to shifted bit
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rol reg1 - rotate reg1 left by 1bits, not using carry + set Carry to shifted bit
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roxl reg1 - rotate reg1 left by 1bits, using carry, + set Carry to shifted bit
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rol reg1 - rotate reg1 left by 1 bits, not using carry + set Carry to shifted bit
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roxl reg1 - rotate reg1 left by 1 bits, using carry, + set Carry to shifted bit
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FLOATING POINT CONVERSIONS AND FUNCTIONS
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@ -227,9 +227,9 @@ enum class Opcode {
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ASRN,
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LSRN,
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LSLN,
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ASR, // TODO not used in codegen of shift 1
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LSR, // TODO not used in codegen of shift 1
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LSL, // TODO not used in codegen of shift 1
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ASR,
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LSR,
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LSL,
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ROR,
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ROXR,
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ROL,
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