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unit test
This commit is contained in:
Irmen de Jong
parent
8d6542905d
commit
bed0e33b4f
@ -15,10 +15,12 @@
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<content url="file://$MODULE_DIR$">
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<sourceFolder url="file://$MODULE_DIR$/src" isTestSource="false" />
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<sourceFolder url="file://$MODULE_DIR$/res" type="java-resource" />
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<sourceFolder url="file://$MODULE_DIR$/test" isTestSource="true" />
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</content>
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<orderEntry type="jdk" jdkName="openjdk-11" jdkType="JavaSDK" />
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<orderEntry type="sourceFolder" forTests="false" />
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<orderEntry type="library" name="KotlinJavaRuntime" level="project" />
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<orderEntry type="library" name="kotlinx-cli-jvm-0.1.0-dev-5" level="project" />
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<orderEntry type="library" name="unittest-libs" level="project" />
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</component>
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</module>
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@ -65,8 +65,8 @@ private fun startSimulator(args: Array<String>) {
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bus.reset()
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ram.load("sim65/ram.bin", 0x8000)
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ram.load("sim65/bcdtest.bin", 0x1000)
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ram.load("sim65/test/testfiles/ram.bin", 0x8000)
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ram.load("sim65/test/testfiles/bcdtest.bin", 0x1000)
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//ram.dump(0x8000, 0x802f)
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//cpu.disassemble(ram, 0x8000, 0x802f)
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@ -4,7 +4,7 @@ package sim65.components
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class InstructionError(msg: String) : RuntimeException(msg)
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interface ICpu {
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fun disassemble(memory: Array<UByte>, baseAddress: Address, from: Address, to: Address)
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fun disassemble(memory: Array<UByte>, baseAddress: Address, from: Address, to: Address): List<String>
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fun disassemble(component: MemMappedComponent, from: Address, to: Address) =
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disassemble(component.cloneMem(), component.startAddress, from, to)
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@ -30,10 +30,13 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
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const val RESET_vector = 0xfffc
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const val IRQ_vector = 0xfffe
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fun hexW(number: Address): String {
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fun hexW(number: Address, allowSingleByte: Boolean = false): String {
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val msb = number ushr 8
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val lsb = number and 255
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return hexB(msb) + hexB(lsb)
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return if(msb==0 && allowSingleByte)
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hexB(lsb)
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else
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hexB(msb) + hexB(lsb)
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}
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private const val hexdigits = "0123456789abcdef"
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@ -130,38 +133,43 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
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AddrMode.IzY to ::amIzy
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)
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override fun disassemble(memory: Array<UByte>, baseAddress: Address, from: Address, to: Address) {
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override fun disassemble(memory: Array<UByte>, baseAddress: Address, from: Address, to: Address): List<String> {
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var address = from - baseAddress
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val spacing1 = " "
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val spacing2 = " "
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val spacing3 = " "
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val result = mutableListOf<String>()
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while (address <= (to - baseAddress)) {
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val byte = memory[address]
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print("\$${hexW(address)} ${hexB(byte)} ")
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var line = "\$${hexW(address)} ${hexB(byte)} "
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address++
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val opcode = opcodes[byte.toInt()]
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if (!opcode.official && !illegalInstrsAllowed) {
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println("$spacing1 ???")
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line += "$spacing1 ???"
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} else {
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when (opcode.mode) {
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AddrMode.Imp, AddrMode.Acc -> {
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println("$spacing1 ${opcode.mnemonic}")
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AddrMode.Acc -> {
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line += "$spacing1 ${opcode.mnemonic} a"
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}
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AddrMode.Imp -> {
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line += "$spacing1 ${opcode.mnemonic}"
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}
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AddrMode.Imm -> {
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val value = memory[address++]
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println("${hexB(value)} $spacing2 ${opcode.mnemonic} #\$${hexB(value)}")
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line += "${hexB(value)} $spacing2 ${opcode.mnemonic} #\$${hexB(value)}"
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}
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AddrMode.Zp -> {
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val zpAddr = memory[address++]
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println("${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)}")
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line += "${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)}"
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}
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AddrMode.ZpX -> {
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val zpAddr = memory[address++]
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println("${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)},x")
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line += "${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)},x"
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}
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AddrMode.ZpY -> {
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val zpAddr = memory[address++]
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println("${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)},y")
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line += "${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} \$${hexB(zpAddr)},y"
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}
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AddrMode.Rel -> {
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val rel = memory[address++]
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@ -170,43 +178,46 @@ class Cpu6502(private val illegalInstrsAllowed: Boolean) : BusComponent(), ICpu
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address + rel
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else
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address - (256 - rel)
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println("${hexB(rel)} $spacing2 ${opcode.mnemonic} \$${hexW(target)}")
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line += "${hexB(rel)} $spacing2 ${opcode.mnemonic} \$${hexW(target, true)}"
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}
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AddrMode.Abs -> {
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val lo = memory[address++]
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val hi = memory[address++]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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println("${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)}")
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line += "${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)}"
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}
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AddrMode.AbsX -> {
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val lo = memory[address++]
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val hi = memory[address++]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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println("${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)},x")
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line += "${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)},x"
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}
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AddrMode.AbsY -> {
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val lo = memory[address++]
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val hi = memory[address++]
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val absAddr = lo.toInt() or (hi.toInt() shl 8)
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println("${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)},y")
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line += "${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} \$${hexW(absAddr)},y"
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}
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AddrMode.Ind -> {
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val lo = memory[address++]
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val hi = memory[address++]
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val indirectAddr = lo.toInt() or (hi.toInt() shl 8)
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println("${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} (\$${hexW(indirectAddr)})")
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line += "${hexB(lo)} ${hexB(hi)} $spacing3 ${opcode.mnemonic} (\$${hexW(indirectAddr)})"
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}
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AddrMode.IzX -> {
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val zpAddr = memory[address++]
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println("${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} (\$${hexB(zpAddr)},x)")
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line += "${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} (\$${hexB(zpAddr)},x)"
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}
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AddrMode.IzY -> {
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val zpAddr = memory[address++]
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println("${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} (\$${hexB(zpAddr)}),y")
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line += "${hexB(zpAddr)} $spacing2 ${opcode.mnemonic} (\$${hexB(zpAddr)}),y"
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}
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}
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}
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result.add(line)
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}
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return result
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}
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override fun reset() {
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29
sim65/test/DisassemTest.kt
Normal file
29
sim65/test/DisassemTest.kt
Normal file
@ -0,0 +1,29 @@
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import org.junit.jupiter.api.Test
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import sim65.components.*
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import java.io.File
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import kotlin.test.*
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class TestDisassembler {
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@Test
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fun testDisassembleAllOpcodes() {
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val cpu = Cpu6502(true)
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val memory = Ram(0, 0xffff)
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memory.load("test/testfiles/disassem_instr_test.prg", 0x1000-2)
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val result = cpu.disassemble(memory, 0x1000, 0x1221)
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assertEquals(256, result.size)
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assertEquals("\$1000 69 01 adc #\$01", result[0])
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val reference = File("test/testfiles/disassem_ref_output.txt").readLines()
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assertEquals(256, reference.size)
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for(line in result.zip(reference)) {
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if(line.first!=line.second) {
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fail("disassembled instruction mismatch: '${line.first}', expected '${line.second}'")
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}
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}
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}
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}
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256
sim65/test/testfiles/disassem_ref_output.txt
Normal file
256
sim65/test/testfiles/disassem_ref_output.txt
Normal file
@ -0,0 +1,256 @@
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$1000 69 01 adc #$01
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$1002 65 02 adc $02
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$1004 75 03 adc $03,x
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$1006 6d 05 04 adc $0405
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$1009 7d 07 06 adc $0607,x
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$100c 79 09 08 adc $0809,y
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$100f 61 0a adc ($0a,x)
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$1011 71 0b adc ($0b),y
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$1013 29 0c and #$0c
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$1015 25 0d and $0d
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$1017 35 0e and $0e,x
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$1019 2d 10 0f and $0f10
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$101c 3d 12 11 and $1112,x
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$101f 39 14 13 and $1314,y
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$1022 21 15 and ($15,x)
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$1024 31 16 and ($16),y
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$1026 0a asl a
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$1027 06 17 asl $17
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$1029 16 18 asl $18,x
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$102b 0e 1a 19 asl $191a
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$102e 1e 1c 1b asl $1b1c,x
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$1031 90 1d bcc $1050
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$1033 b0 1e bcs $1053
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$1035 f0 1f beq $1056
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$1037 24 20 bit $20
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$1039 2c 22 21 bit $2122
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$103c 30 23 bmi $1061
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$103e d0 24 bne $1064
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$1040 10 25 bpl $1067
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$1042 00 brk
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$1043 50 26 bvc $106b
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$1045 70 27 bvs $106e
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$1047 18 clc
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$1048 d8 cld
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$1049 58 cli
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$104a b8 clv
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$104b c9 28 cmp #$28
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$104d c5 29 cmp $29
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$104f d5 2a cmp $2a,x
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$1051 cd 2c 2b cmp $2b2c
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$1054 dd 2e 2d cmp $2d2e,x
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$1057 d9 30 2f cmp $2f30,y
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$105a c1 31 cmp ($31,x)
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$105c d1 32 cmp ($32),y
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$105e e0 33 cpx #$33
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$1060 e4 34 cpx $34
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$1062 ec 36 35 cpx $3536
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$1065 c0 37 cpy #$37
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$1067 c4 38 cpy $38
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$1069 cc 3a 39 cpy $393a
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$106c c6 3b dec $3b
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$106e d6 3c dec $3c,x
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$1070 ce 3e 3d dec $3d3e
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$1073 de 40 3f dec $3f40,x
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$1076 ca dex
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$1077 88 dey
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$1078 49 41 eor #$41
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$107a 45 42 eor $42
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$107c 55 43 eor $43,x
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$107e 4d 45 44 eor $4445
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$1081 5d 47 46 eor $4647,x
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$1084 59 49 48 eor $4849,y
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$1087 41 4a eor ($4a,x)
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$1089 51 4b eor ($4b),y
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$108b e6 4c inc $4c
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$108d f6 4d inc $4d,x
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$108f ee 4f 4e inc $4e4f
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$1092 fe 51 50 inc $5051,x
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$1095 e8 inx
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$1096 c8 iny
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$1097 4c 53 52 jmp $5253
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$109a 6c 55 54 jmp ($5455)
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$109d 20 57 56 jsr $5657
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$10a0 a9 58 lda #$58
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$10a2 a5 59 lda $59
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$10a4 b5 5a lda $5a,x
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$10a6 ad 5c 5b lda $5b5c
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$10a9 bd 5e 5d lda $5d5e,x
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$10ac b9 60 5f lda $5f60,y
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$10af a1 61 lda ($61,x)
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$10b1 b1 62 lda ($62),y
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$10b3 a2 63 ldx #$63
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$10b5 a6 64 ldx $64
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$10b7 b6 65 ldx $65,y
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$10b9 ae 67 66 ldx $6667
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$10bc be 69 68 ldx $6869,y
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$10bf a0 6a ldy #$6a
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$10c1 a4 6b ldy $6b
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$10c3 b4 6c ldy $6c,x
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$10c5 ac 6e 6d ldy $6d6e
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$10c8 bc 70 6f ldy $6f70,x
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$10cb 4a lsr a
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$10cc 46 71 lsr $71
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$10ce 56 72 lsr $72,x
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$10d0 4e 74 73 lsr $7374
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$10d3 5e 76 75 lsr $7576,x
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$10d6 ea nop
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$10d7 09 77 ora #$77
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$10d9 05 78 ora $78
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$10db 15 79 ora $79,x
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$10dd 0d 7b 7a ora $7a7b
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$10e0 1d 7d 7c ora $7c7d,x
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$10e3 19 7f 7e ora $7e7f,y
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$10e6 01 80 ora ($80,x)
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$10e8 11 81 ora ($81),y
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$10ea 48 pha
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$10eb 08 php
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$10ec 68 pla
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$10ed 28 plp
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$10ee 2a rol a
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$10ef 26 82 rol $82
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$10f1 36 83 rol $83,x
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$10f3 2e 85 84 rol $8485
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$10f6 3e 87 86 rol $8687,x
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$10f9 6a ror a
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$10fa 66 88 ror $88
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$10fc 76 89 ror $89,x
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$10fe 6e 8b 8a ror $8a8b
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$1101 7e 8d 8c ror $8c8d,x
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$1104 40 rti
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$1105 60 rts
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$1106 e9 8e sbc #$8e
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$1108 e5 8f sbc $8f
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$110a f5 90 sbc $90,x
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$110c ed 92 91 sbc $9192
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$110f fd 94 93 sbc $9394,x
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$1112 f9 96 95 sbc $9596,y
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$1115 e1 97 sbc ($97,x)
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$1117 f1 98 sbc ($98),y
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$1119 38 sec
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$111a f8 sed
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$111b 78 sei
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$111c 85 99 sta $99
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$111e 95 9a sta $9a,x
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$1120 8d 9c 9b sta $9b9c
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$1123 9d 9e 9d sta $9d9e,x
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$1126 99 a0 9f sta $9fa0,y
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$1129 81 a1 sta ($a1,x)
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$112b 91 a2 sta ($a2),y
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$112d 86 a3 stx $a3
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$112f 96 a4 stx $a4,y
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$1131 8e a6 a5 stx $a5a6
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$1134 84 a7 sty $a7
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$1136 94 a8 sty $a8,x
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$1138 8c aa a9 sty $a9aa
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$113b aa tax
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$113c a8 tay
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$113d ba tsx
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$113e 8a txa
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$113f 9a txs
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$1140 98 tya
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$1141 02 ???
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$1142 12 ???
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$1143 22 ???
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$1144 32 ???
|
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$1145 42 ???
|
||||
$1146 52 ???
|
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$1147 62 ???
|
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$1148 72 ???
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$1149 92 ???
|
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$114a b2 ???
|
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$114b d2 ???
|
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$114c f2 ???
|
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$114d 7a nop
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$114e 5a nop
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$114f 1a nop
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$1150 3a nop
|
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$1151 da nop
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$1152 fa nop
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$1153 80 00 nop #$00
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$1155 82 00 nop #$00
|
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$1157 89 00 nop #$00
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$1159 c2 00 nop #$00
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$115b e2 00 nop #$00
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$115d 04 00 nop $00
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$115f 64 00 nop $00
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$1161 44 00 nop $00
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$1163 0c 00 00 nop $0000
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$1166 14 00 nop $00,x
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$1168 34 00 nop $00,x
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$116a 54 00 nop $00,x
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$116c 74 00 nop $00,x
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$116e d4 00 nop $00,x
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$1170 f4 00 nop $00,x
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$1172 1c 00 00 nop $0000,x
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$1175 3c 00 00 nop $0000,x
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$1178 5c 00 00 nop $0000,x
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$117b 7c 00 00 nop $0000,x
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$117e dc 00 00 nop $0000,x
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$1181 fc 00 00 nop $0000,x
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$1184 ab 00 lax #$00
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$1186 a7 00 lax $00
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$1188 b7 00 lax $00,y
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$118a af 00 00 lax $0000
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$118d bf 00 00 lax $0000,y
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$1190 a3 00 lax ($00,x)
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$1192 b3 00 lax ($00),y
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$1194 87 00 sax $00
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$1196 97 00 sax $00,y
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$1198 8f 00 00 sax $0000
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$119b 83 00 sax ($00,x)
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$119d eb 00 sbc #$00
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$119f c7 00 dcp $00
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$11a1 d7 00 dcp $00,x
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$11a3 cf 00 00 dcp $0000
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$11a6 df 00 00 dcp $0000,x
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$11a9 db 00 00 dcp $0000,y
|
||||
$11ac c3 00 dcp ($00,x)
|
||||
$11ae d3 00 dcp ($00),y
|
||||
$11b0 e7 00 isc $00
|
||||
$11b2 f7 00 isc $00,x
|
||||
$11b4 ef 00 00 isc $0000
|
||||
$11b7 ff 00 00 isc $0000,x
|
||||
$11ba fb 00 00 isc $0000,y
|
||||
$11bd e3 00 isc ($00,x)
|
||||
$11bf f3 00 isc ($00),y
|
||||
$11c1 27 00 rla $00
|
||||
$11c3 37 00 rla $00,x
|
||||
$11c5 2f 00 00 rla $0000
|
||||
$11c8 3f 00 00 rla $0000,x
|
||||
$11cb 3b 00 00 rla $0000,y
|
||||
$11ce 23 00 rla ($00,x)
|
||||
$11d0 33 00 rla ($00),y
|
||||
$11d2 67 00 rra $00
|
||||
$11d4 77 00 rra $00,x
|
||||
$11d6 6f 00 00 rra $0000
|
||||
$11d9 7f 00 00 rra $0000,x
|
||||
$11dc 7b 00 00 rra $0000,y
|
||||
$11df 63 00 rra ($00,x)
|
||||
$11e1 73 00 rra ($00),y
|
||||
$11e3 07 00 slo $00
|
||||
$11e5 17 00 slo $00,x
|
||||
$11e7 0f 00 00 slo $0000
|
||||
$11ea 1f 00 00 slo $0000,x
|
||||
$11ed 1b 00 00 slo $0000,y
|
||||
$11f0 03 00 slo ($00,x)
|
||||
$11f2 13 00 slo ($00),y
|
||||
$11f4 47 00 sre $00
|
||||
$11f6 57 00 sre $00,x
|
||||
$11f8 4f 00 00 sre $0000
|
||||
$11fb 5f 00 00 sre $0000,x
|
||||
$11fe 5b 00 00 sre $0000,y
|
||||
$1201 43 00 sre ($00,x)
|
||||
$1203 53 00 sre ($00),y
|
||||
$1205 0b 00 anc #$00
|
||||
$1207 2b 00 anc #$00
|
||||
$1209 4b 00 alr #$00
|
||||
$120b 6b 00 arr #$00
|
||||
$120d 8b 00 xaa #$00
|
||||
$120f 93 00 ahx ($00),y
|
||||
$1211 9f 00 00 ahx $0000,y
|
||||
$1214 9b 00 00 tas $0000,y
|
||||
$1217 9e 00 00 shx $0000,y
|
||||
$121a 9c 00 00 shy $0000,x
|
||||
$121d bb 00 00 las $0000,y
|
||||
$1220 cb 00 axs #$00
|
||||
Loading…
Reference in New Issue
Block a user