diff --git a/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt b/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt
index 2bd55cf7c..4cde54ce1 100644
--- a/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt
+++ b/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt
@@ -1216,16 +1216,16 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             val valueReg = codeGen.registers.nextFree()
             result += IRCodeChunk(null, null).also {
                 it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
-                it += IRInstruction(Opcode.SEQ, vmDt, reg1=tr.resultReg, reg2=valueReg)
-                it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress)
+                it += IRInstruction(Opcode.SEQ, vmDt, reg1=valueReg, reg2=tr.resultReg)
+                it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
             }
         } else {
             // symbol = symbol == operand
             val valueReg = codeGen.registers.nextFree()
             result += IRCodeChunk(null, null).also {
                 it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
-                it += IRInstruction(Opcode.SEQ, vmDt, reg1=tr.resultReg, reg2=valueReg)
-                it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
+                it += IRInstruction(Opcode.SEQ, vmDt, reg1=valueReg, reg2=tr.resultReg)
+                it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
             }
         }
         return result
@@ -1240,16 +1240,16 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             val valueReg = codeGen.registers.nextFree()
             result += IRCodeChunk(null, null).also {
                 it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
-                it += IRInstruction(Opcode.SNE, vmDt, reg1=tr.resultReg, reg2=valueReg)
-                it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress)
+                it += IRInstruction(Opcode.SNE, vmDt, reg1=valueReg, reg2=tr.resultReg)
+                it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
             }
         } else {
             // symbol = symbol != operand
             val valueReg = codeGen.registers.nextFree()
             result += IRCodeChunk(null, null).also {
                 it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
-                it += IRInstruction(Opcode.SNE, vmDt, reg1=tr.resultReg, reg2=valueReg)
-                it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
+                it += IRInstruction(Opcode.SNE, vmDt, reg1=valueReg, reg2=tr.resultReg)
+                it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
             }
         }
         return result
@@ -1265,16 +1265,16 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             val valueReg = codeGen.registers.nextFree()
             result += IRCodeChunk(null, null).also {
                 it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
-                it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg)
-                it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress)
+                it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
+                it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
             }
         } else {
             // symbol = symbol > operand
             val valueReg = codeGen.registers.nextFree()
             result += IRCodeChunk(null, null).also {
                 it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
-                it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg)
-                it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
+                it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
+                it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
             }
         }
         return result
@@ -1290,16 +1290,16 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             val valueReg = codeGen.registers.nextFree()
             result += IRCodeChunk(null, null).also {
                 it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
-                it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg)
-                it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress)
+                it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
+                it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
             }
         } else {
             // symbol = symbol < operand
             val valueReg = codeGen.registers.nextFree()
             result += IRCodeChunk(null, null).also {
                 it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
-                it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg)
-                it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
+                it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
+                it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
             }
         }
         return result
@@ -1315,16 +1315,16 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             val valueReg = codeGen.registers.nextFree()
             result += IRCodeChunk(null, null).also {
                 it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
-                it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg)
-                it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress)
+                it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
+                it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
             }
         } else {
             // symbol = symbol > operand
             val valueReg = codeGen.registers.nextFree()
             result += IRCodeChunk(null, null).also {
                 it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
-                it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg)
-                it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
+                it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
+                it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
             }
         }
         return result
@@ -1340,16 +1340,16 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
             val valueReg = codeGen.registers.nextFree()
             result += IRCodeChunk(null, null).also {
                 it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
-                it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg)
-                it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, value=knownAddress)
+                it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
+                it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
             }
         } else {
             // symbol = symbol > operand
             val valueReg = codeGen.registers.nextFree()
             result += IRCodeChunk(null, null).also {
                 it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
-                it += IRInstruction(opcode, vmDt, reg1=tr.resultReg, reg2=valueReg)
-                it += IRInstruction(Opcode.STOREM, vmDt, reg1=tr.resultReg, labelSymbol = symbol)
+                it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
+                it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
             }
         }
         return result
diff --git a/docs/source/todo.rst b/docs/source/todo.rst
index 08de00b56..34dd742b8 100644
--- a/docs/source/todo.rst
+++ b/docs/source/todo.rst
@@ -4,11 +4,16 @@ TODO
 
 For next minor release
 ^^^^^^^^^^^^^^^^^^^^^^
-newxpr vm: fix bouncegfx (crash), bsieve (loops), primes (way too many), textelite (map is wrong, incomplete planet info)
+newxpr vm:  vm/bsieve.p8 has wrong result
+once everything works, disable -newexpr option for IR/virtual target because that already works without eval stack
+and creates far superior code without the newexpr flattening.
+
+IR (normal): fix reg1 out of bounds crash in compiler/test/comparisons/test_compares.p8
 
 ...
 
 
+
 For 9.0 major changes
 ^^^^^^^^^^^^^^^^^^^^^
 - get rid of the disknumber parameter everywhere in diskio, make it a configurable variable that defaults to 8.