Apple-2-SW/prog8
1
0
Fork 0
mirror of https://github.com/irmen/prog8.git synced 2025-02-18 05:30:34 +00:00
Code Issues Projects Releases Wiki Activity

refactor expressionsAsmGen so that it now has just 1 single public function

Browse Source 
this makes replacing it by a non-stack based solution easier in the future.
This commit is contained in:
Irmen de Jong 2021-11-08 19:21:55 +01:00
parent 857724c7e6
commit c8a4b6f23c
4 changed files with 1630 additions and 1631 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1619
codeGeneration/src/prog8/compiler/target/cpu6502/codegen/AsmGen.kt
View File

File diff suppressed because it is too large Load Diff

1613
codeGeneration/src/prog8/compiler/target/cpu6502/codegen/ExpressionsAsmGen.kt
View File

File diff suppressed because it is too large Load Diff

7
codeGeneration/src/prog8/compiler/target/cpu6502/codegen/assignment/AssignmentAsmGen.kt
View File

@ -7,17 +7,14 @@ import prog8.ast.statements.*
import prog8.ast.toHex import prog8.ast.toHex
import prog8.compiler.target.AssemblyError import prog8.compiler.target.AssemblyError
import prog8.compiler.target.cpu6502.codegen.AsmGen import prog8.compiler.target.cpu6502.codegen.AsmGen
import prog8.compiler.target.cpu6502.codegen.ExpressionsAsmGen
import prog8.compilerinterface.BuiltinFunctions import prog8.compilerinterface.BuiltinFunctions
import prog8.compilerinterface.CpuType import prog8.compilerinterface.CpuType
import prog8.compilerinterface.builtinFunctionReturnType import prog8.compilerinterface.builtinFunctionReturnType
internal class AssignmentAsmGen(private val program: Program, private val asmgen: AsmGen, internal class AssignmentAsmGen(private val program: Program, private val asmgen: AsmGen) {
private val exprAsmgen: ExpressionsAsmGen
) {
private val augmentableAsmGen = AugmentableAssignmentAsmGen(program, this, exprAsmgen, asmgen) private val augmentableAsmGen = AugmentableAssignmentAsmGen(program, this, asmgen)
fun translate(assignment: Assignment) { fun translate(assignment: Assignment) {
val target = AsmAssignTarget.fromAstAssignment(assignment, program, asmgen) val target = AsmAssignTarget.fromAstAssignment(assignment, program, asmgen)

22
codeGeneration/src/prog8/compiler/target/cpu6502/codegen/assignment/AugmentableAssignmentAsmGen.kt
View File

@ -7,12 +7,10 @@ import prog8.ast.statements.Subroutine
import prog8.ast.toHex import prog8.ast.toHex
import prog8.compiler.target.AssemblyError import prog8.compiler.target.AssemblyError
import prog8.compiler.target.cpu6502.codegen.AsmGen import prog8.compiler.target.cpu6502.codegen.AsmGen
import prog8.compiler.target.cpu6502.codegen.ExpressionsAsmGen
import prog8.compilerinterface.CpuType import prog8.compilerinterface.CpuType
internal class AugmentableAssignmentAsmGen(private val program: Program, internal class AugmentableAssignmentAsmGen(private val program: Program,
private val assignmentAsmGen: AssignmentAsmGen, private val assignmentAsmGen: AssignmentAsmGen,
private val exprAsmGen: ExpressionsAsmGen,
private val asmgen: AsmGen private val asmgen: AsmGen
) { ) {
fun translate(assign: AsmAssignment) { fun translate(assign: AsmAssignment) {
@ -657,14 +655,14 @@ internal class AugmentableAssignmentAsmGen(private val program: Program,
private fun inplaceModification_byte_memread_to_variable(name: String, dt: DataType, operator: String, memread: DirectMemoryRead) { private fun inplaceModification_byte_memread_to_variable(name: String, dt: DataType, operator: String, memread: DirectMemoryRead) {
when (operator) { when (operator) {
"+" -> { "+" -> {
exprAsmGen.translateDirectMemReadExpressionToRegAorStack(memread, false) asmgen.translateDirectMemReadExpressionToRegAorStack(memread, false)
asmgen.out(""" asmgen.out("""
clc clc
adc $name adc $name
sta $name""") sta $name""")
} }
"-" -> { "-" -> {
exprAsmGen.translateDirectMemReadExpressionToRegAorStack(memread, false) asmgen.translateDirectMemReadExpressionToRegAorStack(memread, false)
asmgen.out(""" asmgen.out("""
sta P8ZP_SCRATCH_B1 sta P8ZP_SCRATCH_B1
lda $name lda $name
@ -673,15 +671,15 @@ internal class AugmentableAssignmentAsmGen(private val program: Program,
sta $name""") sta $name""")
} }
"|", "or" -> { "|", "or" -> {
exprAsmGen.translateDirectMemReadExpressionToRegAorStack(memread, false) asmgen.translateDirectMemReadExpressionToRegAorStack(memread, false)
asmgen.out(" ora $name | sta $name") asmgen.out(" ora $name | sta $name")
} }
"&", "and" -> { "&", "and" -> {
exprAsmGen.translateDirectMemReadExpressionToRegAorStack(memread, false) asmgen.translateDirectMemReadExpressionToRegAorStack(memread, false)
asmgen.out(" and $name | sta $name") asmgen.out(" and $name | sta $name")
} }
"^", "xor" -> { "^", "xor" -> {
exprAsmGen.translateDirectMemReadExpressionToRegAorStack(memread, false) asmgen.translateDirectMemReadExpressionToRegAorStack(memread, false)
asmgen.out(" eor $name | sta $name") asmgen.out(" eor $name | sta $name")
} }
// TODO: tuned code for more operators // TODO: tuned code for more operators
@ -694,7 +692,7 @@ internal class AugmentableAssignmentAsmGen(private val program: Program,
private fun inplaceModification_word_memread_to_variable(name: String, dt: DataType, operator: String, memread: DirectMemoryRead) { private fun inplaceModification_word_memread_to_variable(name: String, dt: DataType, operator: String, memread: DirectMemoryRead) {
when (operator) { when (operator) {
"+" -> { "+" -> {
exprAsmGen.translateDirectMemReadExpressionToRegAorStack(memread, false) asmgen.translateDirectMemReadExpressionToRegAorStack(memread, false)
asmgen.out(""" asmgen.out("""
clc clc
adc $name adc $name
@ -704,7 +702,7 @@ internal class AugmentableAssignmentAsmGen(private val program: Program,
+""") +""")
} }
"-" -> { "-" -> {
exprAsmGen.translateDirectMemReadExpressionToRegAorStack(memread, false) asmgen.translateDirectMemReadExpressionToRegAorStack(memread, false)
asmgen.out(""" asmgen.out("""
sta P8ZP_SCRATCH_B1 sta P8ZP_SCRATCH_B1
lda $name lda $name
@ -716,11 +714,11 @@ internal class AugmentableAssignmentAsmGen(private val program: Program,
+""") +""")
} }
"|", "or" -> { "|", "or" -> {
exprAsmGen.translateDirectMemReadExpressionToRegAorStack(memread, false) asmgen.translateDirectMemReadExpressionToRegAorStack(memread, false)
asmgen.out(" ora $name | sta $name") asmgen.out(" ora $name | sta $name")
} }
"&", "and" -> { "&", "and" -> {
exprAsmGen.translateDirectMemReadExpressionToRegAorStack(memread, false) asmgen.translateDirectMemReadExpressionToRegAorStack(memread, false)
asmgen.out(" and $name | sta $name") asmgen.out(" and $name | sta $name")
if(dt in WordDatatypes) { if(dt in WordDatatypes) {
if(asmgen.isTargetCpu(CpuType.CPU65c02)) if(asmgen.isTargetCpu(CpuType.CPU65c02))
@ -730,7 +728,7 @@ internal class AugmentableAssignmentAsmGen(private val program: Program,
} }
} }
"^", "xor" -> { "^", "xor" -> {
exprAsmGen.translateDirectMemReadExpressionToRegAorStack(memread, false) asmgen.translateDirectMemReadExpressionToRegAorStack(memread, false)
asmgen.out(" eor $name | sta $name") asmgen.out(" eor $name | sta $name")
} }
// TODO: tuned code for more operators // TODO: tuned code for more operators