mirror of
https://github.com/irmen/prog8.git
synced 2024-07-08 10:29:09 +00:00
better names, reorder
This commit is contained in:
Irmen de Jong
parent
ffb47458ff
commit
d0674ad688
@ -514,31 +514,6 @@ internal class AsmGen(private val program: Program,
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internal fun fixNameSymbols(name: String) = name.replace("<", "prog8_").replace(">", "") // take care of the autogenerated invalid (anon) label names
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private fun branchInstruction(condition: BranchCondition, complement: Boolean) =
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if(complement) {
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when (condition) {
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BranchCondition.CS -> "bcc"
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BranchCondition.CC -> "bcs"
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BranchCondition.EQ, BranchCondition.Z -> "beq"
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BranchCondition.NE, BranchCondition.NZ -> "bne"
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BranchCondition.VS -> "bvc"
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BranchCondition.VC -> "bvs"
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BranchCondition.MI, BranchCondition.NEG -> "bmi"
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BranchCondition.PL, BranchCondition.POS -> "bpl"
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}
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} else {
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when (condition) {
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BranchCondition.CS -> "bcs"
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BranchCondition.CC -> "bcc"
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BranchCondition.EQ, BranchCondition.Z -> "beq"
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BranchCondition.NE, BranchCondition.NZ -> "bne"
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BranchCondition.VS -> "bvs"
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BranchCondition.VC -> "bvc"
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BranchCondition.MI, BranchCondition.NEG -> "bmi"
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BranchCondition.PL, BranchCondition.POS -> "bpl"
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}
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}
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internal fun readAndPushArrayvalueWithIndexA(elementDt: DataType, variable: IdentifierReference) {
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val variablename = asmIdentifierName(variable)
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when (elementDt) {
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@ -576,31 +551,6 @@ internal class AsmGen(private val program: Program,
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}
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}
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private fun translateSubroutine(sub: Subroutine) {
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out("")
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outputSourceLine(sub)
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if(sub.isAsmSubroutine) {
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if(sub.asmAddress!=null)
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return // already done at the memvars section
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// asmsub with most likely just an inline asm in it
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out("${sub.name}\t.proc")
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sub.statements.forEach{ translate(it) }
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out(" .pend\n")
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} else {
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// regular subroutine
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out("${sub.name}\t.proc")
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zeropagevars2asm(sub.statements)
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memdefs2asm(sub.statements)
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out("; statements")
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sub.statements.forEach{ translate(it) }
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out("; variables")
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vardecls2asm(sub.statements)
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out(" .pend\n")
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}
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}
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internal fun translate(stmt: Statement) {
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outputSourceLine(stmt)
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when(stmt) {
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@ -652,6 +602,82 @@ internal class AsmGen(private val program: Program,
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}
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}
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internal fun translateArrayIndexIntoA(expr: ArrayIndexedExpression) {
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when (val index = expr.arrayspec.index) {
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is NumericLiteralValue -> throw AssemblyError("this should be optimized directly")
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is IdentifierReference -> {
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val indexName = asmIdentifierName(index)
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out(" lda $indexName")
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}
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else -> {
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expressionsAsmGen.translateExpression(index)
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out(" inx | lda $ESTACK_LO_HEX,x")
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}
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}
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}
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internal fun translateExpression(expression: Expression) =
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expressionsAsmGen.translateExpression(expression)
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internal fun translateFunctioncallExpression(functionCall: FunctionCall, signature: FSignature) =
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builtinFunctionsAsmGen.translateFunctioncallExpression(functionCall, signature)
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internal fun translateFunctionCall(functionCall: FunctionCall) =
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functioncallAsmGen.translateFunctionCall(functionCall)
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internal fun assignToRegister(reg: CpuRegister, value: Int?, identifier: IdentifierReference?) =
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assignmentAsmGen.assignToRegister(reg, value, identifier)
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private fun translateSubroutine(sub: Subroutine) {
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out("")
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outputSourceLine(sub)
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if(sub.isAsmSubroutine) {
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if(sub.asmAddress!=null)
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return // already done at the memvars section
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// asmsub with most likely just an inline asm in it
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out("${sub.name}\t.proc")
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sub.statements.forEach{ translate(it) }
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out(" .pend\n")
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} else {
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// regular subroutine
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out("${sub.name}\t.proc")
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zeropagevars2asm(sub.statements)
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memdefs2asm(sub.statements)
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out("; statements")
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sub.statements.forEach{ translate(it) }
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out("; variables")
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vardecls2asm(sub.statements)
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out(" .pend\n")
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}
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}
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private fun branchInstruction(condition: BranchCondition, complement: Boolean) =
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if(complement) {
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when (condition) {
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BranchCondition.CS -> "bcc"
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BranchCondition.CC -> "bcs"
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BranchCondition.EQ, BranchCondition.Z -> "beq"
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BranchCondition.NE, BranchCondition.NZ -> "bne"
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BranchCondition.VS -> "bvc"
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BranchCondition.VC -> "bvs"
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BranchCondition.MI, BranchCondition.NEG -> "bmi"
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BranchCondition.PL, BranchCondition.POS -> "bpl"
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}
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} else {
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when (condition) {
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BranchCondition.CS -> "bcs"
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BranchCondition.CC -> "bcc"
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BranchCondition.EQ, BranchCondition.Z -> "beq"
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BranchCondition.NE, BranchCondition.NZ -> "bne"
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BranchCondition.VS -> "bvs"
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BranchCondition.VC -> "bvc"
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BranchCondition.MI, BranchCondition.NEG -> "bmi"
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BranchCondition.PL, BranchCondition.POS -> "bpl"
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}
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}
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private fun translate(stmt: IfStatement) {
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expressionsAsmGen.translateExpression(stmt.condition)
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translateTestStack(stmt.condition.inferType(program).typeOrElse(DataType.STRUCT))
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@ -1000,30 +1026,4 @@ $counterVar .byte 0""")
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val assembly = asm.assembly.trimEnd().trimStart('\n')
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assemblyLines.add(assembly)
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}
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internal fun translateArrayIndexIntoA(expr: ArrayIndexedExpression) {
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when (val index = expr.arrayspec.index) {
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is NumericLiteralValue -> throw AssemblyError("this should be optimized directly")
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is IdentifierReference -> {
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val indexName = asmIdentifierName(index)
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out(" lda $indexName")
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}
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else -> {
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expressionsAsmGen.translateExpression(index)
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out(" inx | lda $ESTACK_LO_HEX,x")
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}
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}
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}
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internal fun translateExpression(expression: Expression) =
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expressionsAsmGen.translateExpression(expression)
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internal fun translateFunctioncallExpression(functionCall: FunctionCall, signature: FSignature) =
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builtinFunctionsAsmGen.translateFunctioncallExpression(functionCall, signature)
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internal fun translateFunctionCall(functionCall: FunctionCall) =
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functioncallAsmGen.translateFunctionCall(functionCall)
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internal fun assignToRegister(reg: CpuRegister, value: Short?, identifier: IdentifierReference?) =
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assignmentAsmGen.assignToRegister(reg, value, identifier)
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}
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@ -34,45 +34,37 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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val assign = AsmAssignment(source, target, assignment.isAugmentable, assignment.position)
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when {
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source.kind==SourceStorageKind.LITERALNUMBER -> translateConstantValueAssignment(assign)
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source.kind==SourceStorageKind.VARIABLE -> translateVariableAssignment(assign)
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assign.isAugmentable -> augmentableAsmGen.translate(assign)
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source.kind==SourceStorageKind.LITERALNUMBER -> {
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// simple case: assign a constant number
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val num = assign.source.number!!.number
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when (assign.source.datatype) {
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DataType.UBYTE, DataType.BYTE -> assignConstantByte(assign.target, num.toShort())
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DataType.UWORD, DataType.WORD -> assignConstantWord(assign.target, num.toInt())
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DataType.FLOAT -> assignConstantFloat(assign.target, num.toDouble())
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else -> throw AssemblyError("weird numval type")
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}
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}
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source.kind==SourceStorageKind.VARIABLE -> {
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// simple case: assign from another variable
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val variable = assign.source.variable!!
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when (assign.source.datatype) {
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DataType.UBYTE, DataType.BYTE -> assignVariableByte(assign.target, variable)
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DataType.UWORD, DataType.WORD -> assignVariableWord(assign.target, variable)
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DataType.FLOAT -> assignVariableFloat(assign.target, variable)
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in PassByReferenceDatatypes -> assignAddressOf(assign.target, variable)
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else -> throw AssemblyError("unsupported assignment target type ${assign.target.datatype}")
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}
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}
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assign.isAugmentable -> {
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// special case: the in-place assignment / modification
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augmentableAsmGen.translate(assign)
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}
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else -> translateOtherAssignment(assign)
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}
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}
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internal fun assignToRegister(reg: CpuRegister, value: Short?, identifier: IdentifierReference?) {
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if(value!=null) {
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asmgen.out(" ld${reg.toString().toLowerCase()} #${value.toHex()}")
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} else if(identifier!=null) {
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val name = asmgen.asmIdentifierName(identifier)
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asmgen.out(" ld${reg.toString().toLowerCase()} $name")
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}
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}
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private fun translateVariableAssignment(assign: AsmAssignment) {
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val identifier = assign.source.variable!!
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when (assign.target.datatype) {
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DataType.UBYTE, DataType.BYTE -> assignFromByteVariable(assign.target, identifier)
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DataType.UWORD, DataType.WORD -> assignFromWordVariable(assign.target, identifier)
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DataType.FLOAT -> assignFromFloatVariable(assign.target, identifier)
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in PassByReferenceDatatypes -> assignFromAddressOf(assign.target, identifier)
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else -> throw AssemblyError("unsupported assignment target type ${assign.target.datatype}")
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}
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}
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private fun translateConstantValueAssignment(assign: AsmAssignment) {
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val numVal = assign.source.number!!
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when (numVal.type) {
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DataType.UBYTE, DataType.BYTE -> assignFromByteConstant(assign.target, numVal.number.toShort())
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DataType.UWORD, DataType.WORD -> assignFromWordConstant(assign.target, numVal.number.toInt())
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DataType.FLOAT -> assignFromFloatConstant(assign.target, numVal.number.toDouble())
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else -> throw AssemblyError("weird numval type")
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}
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}
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internal fun translateOtherAssignment(assign: AsmAssignment) {
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// source: expression, register, stack (only expression implemented for now)
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// source kind: expression, register, stack (only expression implemented for now)
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when(assign.source.kind) {
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SourceStorageKind.LITERALNUMBER,
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@ -81,7 +73,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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SourceStorageKind.ARRAY -> {
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val value = assign.source.array!!
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val elementDt = value.inferType(program).typeOrElse(DataType.STRUCT)
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val elementDt = assign.source.datatype
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val index = value.arrayspec.index
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if (index is NumericLiteralValue) {
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// constant array index value
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@ -101,53 +93,54 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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asmgen.translateArrayIndexIntoA(value)
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asmgen.readAndPushArrayvalueWithIndexA(elementDt, value.identifier)
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}
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assignFromEvalResult(assign.target)
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assignStackValue(assign.target)
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}
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SourceStorageKind.MEMORY -> {
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val value = assign.source.memory!!
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when (value.addressExpression) {
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is NumericLiteralValue -> {
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val address = (value.addressExpression as NumericLiteralValue).number.toInt()
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assignFromMemoryByte(assign.target, address, null)
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assignMemoryByte(assign.target, address, null)
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}
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is IdentifierReference -> {
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assignFromMemoryByte(assign.target, null, value.addressExpression as IdentifierReference)
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assignMemoryByte(assign.target, null, value.addressExpression as IdentifierReference)
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}
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else -> {
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asmgen.translateExpression(value.addressExpression)
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asmgen.out(" jsr prog8_lib.read_byte_from_address_on_stack | inx")
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assignByteFromRegister(assign.target, CpuRegister.A)
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assignRegisterByte(assign.target, CpuRegister.A)
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}
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}
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}
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SourceStorageKind.EXPRESSION -> {
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val value = assign.source.expression!!
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if (value is AddressOf) {
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assignFromAddressOf(assign.target, value.identifier)
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assignAddressOf(assign.target, value.identifier)
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}
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else {
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asmgen.translateExpression(value)
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assignFromEvalResult(assign.target)
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assignStackValue(assign.target)
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}
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}
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SourceStorageKind.REGISTER -> {
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assignByteFromRegister(assign.target, assign.source.register!!)
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assignRegisterByte(assign.target, assign.source.register!!)
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}
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SourceStorageKind.STACK -> {
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when(assign.source.datatype) {
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in ByteDatatypes -> {
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asmgen.out(" jsr prog8_lib.read_byte_from_address_on_stack | inx")
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assignByteFromRegister(assign.target, CpuRegister.A)
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}
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in WordDatatypes -> TODO("assign word from stack")
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DataType.FLOAT -> TODO("assign float from stack")
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else -> throw AssemblyError("weird stack value type")
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}
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assignStackValue(assign.target)
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}
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}
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}
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private fun assignFromEvalResult(target: AsmAssignTarget) {
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internal fun assignToRegister(reg: CpuRegister, value: Int?, identifier: IdentifierReference?) {
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if(value!=null) {
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asmgen.out(" ld${reg.toString().toLowerCase()} #${value.toHex()}")
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} else if(identifier!=null) {
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val name = asmgen.asmIdentifierName(identifier)
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asmgen.out(" ld${reg.toString().toLowerCase()} $name")
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}
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}
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private fun assignStackValue(target: AsmAssignTarget) {
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when(target.kind) {
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TargetStorageKind.VARIABLE -> {
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when (target.datatype) {
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@ -189,7 +182,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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private fun assignFromAddressOf(target: AsmAssignTarget, name: IdentifierReference) {
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private fun assignAddressOf(target: AsmAssignTarget, name: IdentifierReference) {
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val struct = name.memberOfStruct(program.namespace)
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val sourceName = if (struct != null) {
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// take the address of the first struct member instead
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@ -225,7 +218,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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private fun assignFromWordVariable(target: AsmAssignTarget, variable: IdentifierReference) {
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private fun assignVariableWord(target: AsmAssignTarget, variable: IdentifierReference) {
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val sourceName = asmgen.asmIdentifierName(variable)
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when(target.kind) {
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TargetStorageKind.VARIABLE -> {
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@ -253,7 +246,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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private fun assignFromFloatVariable(target: AsmAssignTarget, variable: IdentifierReference) {
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private fun assignVariableFloat(target: AsmAssignTarget, variable: IdentifierReference) {
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val sourceName = asmgen.asmIdentifierName(variable)
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when(target.kind) {
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TargetStorageKind.VARIABLE -> {
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@ -281,7 +274,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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private fun assignFromByteVariable(target: AsmAssignTarget, variable: IdentifierReference) {
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private fun assignVariableByte(target: AsmAssignTarget, variable: IdentifierReference) {
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val sourceName = asmgen.asmIdentifierName(variable)
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when(target.kind) {
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TargetStorageKind.VARIABLE -> {
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@ -307,7 +300,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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private fun assignByteFromRegister(target: AsmAssignTarget, register: CpuRegister) {
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private fun assignRegisterByte(target: AsmAssignTarget, register: CpuRegister) {
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require(target.datatype in ByteDatatypes)
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when(target.kind) {
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TargetStorageKind.VARIABLE -> {
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@ -365,80 +358,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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private fun storeByteViaRegisterAInMemoryAddress(ldaInstructionArg: String, memoryAddress: DirectMemoryWrite) {
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val addressExpr = memoryAddress.addressExpression
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val addressLv = addressExpr as? NumericLiteralValue
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when {
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addressLv != null -> {
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asmgen.out(" lda $ldaInstructionArg | sta ${addressLv.number.toHex()}")
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}
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addressExpr is IdentifierReference -> {
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val pointerVarName = asmgen.asmIdentifierName(addressExpr)
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asmgen.out("""
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lda $pointerVarName
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sta ${C64Zeropage.SCRATCH_W2}
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lda $pointerVarName+1
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sta ${C64Zeropage.SCRATCH_W2+1}
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lda $ldaInstructionArg
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ldy #0
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sta (${C64Zeropage.SCRATCH_W2}),y""")
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}
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else -> {
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asmgen.translateExpression(addressExpr)
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asmgen.out("""
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inx
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lda $ESTACK_LO_HEX,x
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sta ${C64Zeropage.SCRATCH_W2}
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lda $ESTACK_HI_HEX,x
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sta ${C64Zeropage.SCRATCH_W2+1}
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lda $ldaInstructionArg
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ldy #0
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sta (${C64Zeropage.SCRATCH_W2}),y""")
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}
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}
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}
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private fun storeRegisterInMemoryAddress(register: CpuRegister, memoryAddress: DirectMemoryWrite) {
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// this is optimized for register A.
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val addressExpr = memoryAddress.addressExpression
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val addressLv = addressExpr as? NumericLiteralValue
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val registerName = register.name.toLowerCase()
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when {
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addressLv != null -> {
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asmgen.out(" st$registerName ${addressLv.number.toHex()}")
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}
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addressExpr is IdentifierReference -> {
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val targetName = asmgen.asmIdentifierName(addressExpr)
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when (register) {
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CpuRegister.A -> {}
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CpuRegister.X -> asmgen.out(" txa")
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CpuRegister.Y -> asmgen.out(" tya")
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}
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asmgen.out("""
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ldy $targetName
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sty ${C64Zeropage.SCRATCH_W1}
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ldy $targetName+1
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sty ${C64Zeropage.SCRATCH_W1+1}
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ldy #0
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sta (${C64Zeropage.SCRATCH_W1}),y""")
|
||||
}
|
||||
else -> {
|
||||
asmgen.saveRegister(register)
|
||||
asmgen.translateExpression(addressExpr)
|
||||
asmgen.restoreRegister(CpuRegister.A)
|
||||
asmgen.out("""
|
||||
inx
|
||||
ldy $ESTACK_LO_HEX,x
|
||||
sty ${C64Zeropage.SCRATCH_W1}
|
||||
ldy $ESTACK_HI_HEX,x
|
||||
sty ${C64Zeropage.SCRATCH_W1+1}
|
||||
ldy #0
|
||||
sta (${C64Zeropage.SCRATCH_W1}),y""")
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
private fun assignFromWordConstant(target: AsmAssignTarget, word: Int) {
|
||||
private fun assignConstantWord(target: AsmAssignTarget, word: Int) {
|
||||
when(target.kind) {
|
||||
TargetStorageKind.VARIABLE -> {
|
||||
if (word ushr 8 == word and 255) {
|
||||
@ -480,7 +400,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
|
||||
}
|
||||
}
|
||||
|
||||
private fun assignFromByteConstant(target: AsmAssignTarget, byte: Short) {
|
||||
private fun assignConstantByte(target: AsmAssignTarget, byte: Short) {
|
||||
when(target.kind) {
|
||||
TargetStorageKind.VARIABLE -> {
|
||||
asmgen.out(" lda #${byte.toHex()} | sta ${target.asmName} ")
|
||||
@ -503,7 +423,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
|
||||
}
|
||||
}
|
||||
|
||||
private fun assignFromFloatConstant(target: AsmAssignTarget, float: Double) {
|
||||
private fun assignConstantFloat(target: AsmAssignTarget, float: Double) {
|
||||
if (float == 0.0) {
|
||||
// optimized case for float zero
|
||||
when(target.kind) {
|
||||
@ -597,7 +517,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
|
||||
}
|
||||
}
|
||||
|
||||
private fun assignFromMemoryByte(target: AsmAssignTarget, address: Int?, identifier: IdentifierReference?) {
|
||||
private fun assignMemoryByte(target: AsmAssignTarget, address: Int?, identifier: IdentifierReference?) {
|
||||
if (address != null) {
|
||||
when(target.kind) {
|
||||
TargetStorageKind.VARIABLE -> {
|
||||
@ -643,19 +563,92 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
|
||||
}
|
||||
}
|
||||
|
||||
private fun popAndWriteArrayvalueWithIndexA(arrayDt: DataType, variablename: String) {
|
||||
private fun storeByteViaRegisterAInMemoryAddress(ldaInstructionArg: String, memoryAddress: DirectMemoryWrite) {
|
||||
val addressExpr = memoryAddress.addressExpression
|
||||
val addressLv = addressExpr as? NumericLiteralValue
|
||||
when {
|
||||
addressLv != null -> {
|
||||
asmgen.out(" lda $ldaInstructionArg | sta ${addressLv.number.toHex()}")
|
||||
}
|
||||
addressExpr is IdentifierReference -> {
|
||||
val pointerVarName = asmgen.asmIdentifierName(addressExpr)
|
||||
asmgen.out("""
|
||||
lda $pointerVarName
|
||||
sta ${C64Zeropage.SCRATCH_W2}
|
||||
lda $pointerVarName+1
|
||||
sta ${C64Zeropage.SCRATCH_W2+1}
|
||||
lda $ldaInstructionArg
|
||||
ldy #0
|
||||
sta (${C64Zeropage.SCRATCH_W2}),y""")
|
||||
}
|
||||
else -> {
|
||||
asmgen.translateExpression(addressExpr)
|
||||
asmgen.out("""
|
||||
inx
|
||||
lda $ESTACK_LO_HEX,x
|
||||
sta ${C64Zeropage.SCRATCH_W2}
|
||||
lda $ESTACK_HI_HEX,x
|
||||
sta ${C64Zeropage.SCRATCH_W2+1}
|
||||
lda $ldaInstructionArg
|
||||
ldy #0
|
||||
sta (${C64Zeropage.SCRATCH_W2}),y""")
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
private fun storeRegisterInMemoryAddress(register: CpuRegister, memoryAddress: DirectMemoryWrite) {
|
||||
// this is optimized for register A.
|
||||
val addressExpr = memoryAddress.addressExpression
|
||||
val addressLv = addressExpr as? NumericLiteralValue
|
||||
val registerName = register.name.toLowerCase()
|
||||
when {
|
||||
addressLv != null -> {
|
||||
asmgen.out(" st$registerName ${addressLv.number.toHex()}")
|
||||
}
|
||||
addressExpr is IdentifierReference -> {
|
||||
val targetName = asmgen.asmIdentifierName(addressExpr)
|
||||
when (register) {
|
||||
CpuRegister.A -> {}
|
||||
CpuRegister.X -> asmgen.out(" txa")
|
||||
CpuRegister.Y -> asmgen.out(" tya")
|
||||
}
|
||||
asmgen.out("""
|
||||
ldy $targetName
|
||||
sty ${C64Zeropage.SCRATCH_W1}
|
||||
ldy $targetName+1
|
||||
sty ${C64Zeropage.SCRATCH_W1+1}
|
||||
ldy #0
|
||||
sta (${C64Zeropage.SCRATCH_W1}),y""")
|
||||
}
|
||||
else -> {
|
||||
asmgen.saveRegister(register)
|
||||
asmgen.translateExpression(addressExpr)
|
||||
asmgen.restoreRegister(CpuRegister.A)
|
||||
asmgen.out("""
|
||||
inx
|
||||
ldy $ESTACK_LO_HEX,x
|
||||
sty ${C64Zeropage.SCRATCH_W1}
|
||||
ldy $ESTACK_HI_HEX,x
|
||||
sty ${C64Zeropage.SCRATCH_W1+1}
|
||||
ldy #0
|
||||
sta (${C64Zeropage.SCRATCH_W1}),y""")
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
private fun popAndWriteArrayvalueWithIndexA(arrayDt: DataType, arrayvarname: String) {
|
||||
when (arrayDt) {
|
||||
DataType.STR, DataType.ARRAY_UB, DataType.ARRAY_B ->
|
||||
asmgen.out(" tay | inx | lda $ESTACK_LO_HEX,x | sta $variablename,y")
|
||||
asmgen.out(" tay | inx | lda $ESTACK_LO_HEX,x | sta $arrayvarname,y")
|
||||
DataType.ARRAY_UW, DataType.ARRAY_W ->
|
||||
asmgen.out(" asl a | tay | inx | lda $ESTACK_LO_HEX,x | sta $variablename,y | lda $ESTACK_HI_HEX,x | sta $variablename+1,y")
|
||||
asmgen.out(" asl a | tay | inx | lda $ESTACK_LO_HEX,x | sta $arrayvarname,y | lda $ESTACK_HI_HEX,x | sta $arrayvarname+1,y")
|
||||
DataType.ARRAY_F ->
|
||||
// index * 5 is done in the subroutine that's called
|
||||
asmgen.out("""
|
||||
sta $ESTACK_LO_HEX,x
|
||||
dex
|
||||
lda #<$variablename
|
||||
ldy #>$variablename
|
||||
lda #<$arrayvarname
|
||||
ldy #>$arrayvarname
|
||||
jsr c64flt.pop_float_to_indexed_var
|
||||
""")
|
||||
else ->
|
||||
|
||||
@ -173,7 +173,7 @@ internal class FunctionCallAsmGen(private val program: Program, private val asmg
|
||||
register!=null && register.name.length==1 -> {
|
||||
when (value) {
|
||||
is NumericLiteralValue -> {
|
||||
asmgen.assignToRegister(CpuRegister.valueOf(register.name), value.number.toShort(), null)
|
||||
asmgen.assignToRegister(CpuRegister.valueOf(register.name), value.number.toInt(), null)
|
||||
}
|
||||
is IdentifierReference -> {
|
||||
asmgen.assignToRegister(CpuRegister.valueOf(register.name), null, value)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user