mirror of
https://github.com/irmen/prog8.git
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fix parameter passing bug introduced recently (byte not converted to word)
This commit is contained in:
Irmen de Jong
parent
16b24fadea
commit
d54ab856e7
@ -563,7 +563,7 @@ class AsmGen6502Internal (
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when(reg) {
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RegisterOrPair.A,
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RegisterOrPair.X,
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RegisterOrPair.Y -> assignmentAsmGen.assignRegisterByte(target, reg.asCpuRegister(), target.datatype in SignedDatatypes)
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RegisterOrPair.Y -> assignmentAsmGen.assignRegisterByte(target, reg.asCpuRegister(), target.datatype in SignedDatatypes, true)
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RegisterOrPair.AX,
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RegisterOrPair.AY,
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RegisterOrPair.XY,
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@ -110,8 +110,8 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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val var3name = asmgen.asmVariableName(fcall.args[3] as PtIdentifier)
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val divisionTarget = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, DataType.UBYTE, fcall.definingISub(), fcall.args[2].position, var2name)
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val remainderTarget = AsmAssignTarget(TargetStorageKind.VARIABLE, asmgen, DataType.UBYTE, fcall.definingISub(), fcall.args[3].position, var3name)
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assignAsmGen.assignRegisterByte(remainderTarget, CpuRegister.A, false)
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assignAsmGen.assignRegisterByte(divisionTarget, CpuRegister.Y, false)
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assignAsmGen.assignRegisterByte(remainderTarget, CpuRegister.A, false, false)
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assignAsmGen.assignRegisterByte(divisionTarget, CpuRegister.Y, false, false)
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}
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private fun funcDivmodW(fcall: PtBuiltinFunctionCall) {
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@ -273,11 +273,11 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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when(fcall.args[0].type) {
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DataType.UBYTE -> {
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asmgen.out(" ldy #0 | jsr prog8_lib.func_sqrt16_into_A")
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, fcall.position, scope, asmgen), CpuRegister.A, false)
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, fcall.position, scope, asmgen), CpuRegister.A, false, false)
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}
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DataType.UWORD -> {
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asmgen.out(" jsr prog8_lib.func_sqrt16_into_A")
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, fcall.position, scope, asmgen), CpuRegister.A, false)
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, fcall.position, scope, asmgen), CpuRegister.A, false, false)
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}
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DataType.FLOAT -> {
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asmgen.out(" jsr floats.func_sqrt_into_FAC1")
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@ -686,7 +686,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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assignAsmGen.assignConstantByte(target, 0)
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} else {
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asmgen.assignExpressionToRegister(fcall.args[1], RegisterOrPair.A, false)
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assignAsmGen.assignRegisterByte(target, CpuRegister.A, false)
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assignAsmGen.assignRegisterByte(target, CpuRegister.A, false, false)
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}
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}
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@ -701,7 +701,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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DataType.FLOAT -> asmgen.out(" jsr floats.func_sign_f_into_A")
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else -> throw AssemblyError("weird type $dt")
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}
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, fcall.position, scope, asmgen), CpuRegister.A, true)
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, fcall.position, scope, asmgen), CpuRegister.A, true, true)
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}
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private fun funcAnyAll(fcall: PtBuiltinFunctionCall, resultRegister: RegisterOrPair?, scope: IPtSubroutine?) {
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@ -714,7 +714,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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in SplitWordArrayTypes -> TODO("split word any/all")
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else -> throw AssemblyError("weird type $dt")
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}
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, fcall.position, scope, asmgen), CpuRegister.A, dt in SignedDatatypes)
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, fcall.position, scope, asmgen), CpuRegister.A, dt in SignedDatatypes, true)
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}
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private fun funcAbs(fcall: PtBuiltinFunctionCall, resultRegister: RegisterOrPair?, scope: IPtSubroutine?) {
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@ -723,7 +723,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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when (dt) {
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DataType.BYTE -> {
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asmgen.out(" jsr prog8_lib.abs_b_into_A")
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, fcall.position, scope, asmgen), CpuRegister.A,false)
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assignAsmGen.assignRegisterByte(AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, false, fcall.position, scope, asmgen), CpuRegister.A,false, true)
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}
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DataType.WORD -> {
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asmgen.out(" jsr prog8_lib.abs_w_into_AY")
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@ -871,7 +871,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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assignAsmGen.assignExpressionToRegister(fcall.args[0], RegisterOrPair.A, signed) // value
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asmgen.out(" jsr prog8_lib.func_clamp_${fcall.type.toString().lowercase()}")
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val targetReg = AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, signed, fcall.position, fcall.definingISub(), asmgen)
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assignAsmGen.assignRegisterByte(targetReg, CpuRegister.A, signed)
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assignAsmGen.assignRegisterByte(targetReg, CpuRegister.A, signed, true)
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}
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in WordDatatypes -> {
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assignAsmGen.assignExpressionToVariable(fcall.args[1], "P8ZP_SCRATCH_W1", fcall.args[1].type) // minimum
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@ -887,7 +887,8 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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private fun funcMin(fcall: PtBuiltinFunctionCall, resultRegister: RegisterOrPair?) {
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val signed = fcall.type in SignedDatatypes
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if(fcall.type in ByteDatatypes) {
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when (fcall.type) {
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in ByteDatatypes -> {
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asmgen.assignExpressionToVariable(fcall.args[1], "P8ZP_SCRATCH_B1", fcall.type) // right
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asmgen.assignExpressionToRegister(fcall.args[0], RegisterOrPair.A) // left
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asmgen.out(" cmp P8ZP_SCRATCH_B1")
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@ -897,7 +898,8 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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+""")
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val targetReg = AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.A, signed, fcall.position, fcall.definingISub(), asmgen)
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asmgen.assignRegister(RegisterOrPair.A, targetReg)
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} else if(fcall.type in WordDatatypes) {
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}
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in WordDatatypes -> {
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asmgen.assignExpressionToVariable(fcall.args[0], "P8ZP_SCRATCH_W1", fcall.type) // left
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asmgen.assignExpressionToVariable(fcall.args[1], "P8ZP_SCRATCH_W2", fcall.type) // right
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if(signed) {
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@ -934,10 +936,12 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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}
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val targetReg = AsmAssignTarget.fromRegisters(resultRegister ?: RegisterOrPair.AY, signed, fcall.position, fcall.definingISub(), asmgen)
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asmgen.assignRegister(RegisterOrPair.AY, targetReg)
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} else {
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}
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else -> {
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throw AssemblyError("min float not supported")
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}
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}
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}
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private fun funcMax(fcall: PtBuiltinFunctionCall, resultRegister: RegisterOrPair?) {
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val signed = fcall.type in SignedDatatypes
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@ -84,7 +84,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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asmgen.out(" lda (P8ZP_SCRATCH_W1),y")
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}
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}
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assignRegisterByte(assign.target, CpuRegister.A, elementDt in SignedDatatypes)
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assignRegisterByte(assign.target, CpuRegister.A, elementDt in SignedDatatypes, false)
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return
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}
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@ -109,7 +109,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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when (elementDt) {
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in ByteDatatypes -> {
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asmgen.out(" lda $arrayVarName+$indexValue")
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assignRegisterByte(assign.target, CpuRegister.A, elementDt in SignedDatatypes)
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assignRegisterByte(assign.target, CpuRegister.A, elementDt in SignedDatatypes, false)
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}
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in WordDatatypes -> {
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asmgen.out(" lda $arrayVarName+$indexValue | ldy $arrayVarName+$indexValue+1")
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@ -127,7 +127,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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in ByteDatatypes -> {
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asmgen.loadScaledArrayIndexIntoRegister(value, elementDt, CpuRegister.Y)
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asmgen.out(" lda $arrayVarName,y")
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assignRegisterByte(assign.target, CpuRegister.A, elementDt in SignedDatatypes)
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assignRegisterByte(assign.target, CpuRegister.A, elementDt in SignedDatatypes, true)
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}
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in WordDatatypes -> {
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asmgen.loadScaledArrayIndexIntoRegister(value, elementDt, CpuRegister.Y)
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@ -154,7 +154,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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fun assignViaExprEval(expression: PtExpression) {
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assignExpressionToVariable(expression, "P8ZP_SCRATCH_W2", DataType.UWORD)
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asmgen.loadAFromZpPointerVar("P8ZP_SCRATCH_W2")
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assignRegisterByte(assign.target, CpuRegister.A, false)
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assignRegisterByte(assign.target, CpuRegister.A, false, true)
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}
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val value = assign.source.memory!!
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@ -169,7 +169,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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is PtBinaryExpression -> {
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val addrExpr = value.address as PtBinaryExpression
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if(asmgen.tryOptimizedPointerAccessWithA(addrExpr, addrExpr.operator, false)) {
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assignRegisterByte(assign.target, CpuRegister.A, false)
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assignRegisterByte(assign.target, CpuRegister.A, false, true)
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} else {
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assignViaExprEval(value.address)
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}
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@ -223,9 +223,9 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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else -> {
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// do NOT restore X register before assigning the result values first
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when (returnValue.first.registerOrPair) {
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RegisterOrPair.A -> assignRegisterByte(assign.target, CpuRegister.A, returnValue.second in SignedDatatypes)
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RegisterOrPair.X -> assignRegisterByte(assign.target, CpuRegister.X, returnValue.second in SignedDatatypes)
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RegisterOrPair.Y -> assignRegisterByte(assign.target, CpuRegister.Y, returnValue.second in SignedDatatypes)
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RegisterOrPair.A -> assignRegisterByte(assign.target, CpuRegister.A, returnValue.second in SignedDatatypes, true)
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RegisterOrPair.X -> assignRegisterByte(assign.target, CpuRegister.X, returnValue.second in SignedDatatypes, true)
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RegisterOrPair.Y -> assignRegisterByte(assign.target, CpuRegister.Y, returnValue.second in SignedDatatypes, true)
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RegisterOrPair.AX -> assignVirtualRegister(assign.target, RegisterOrPair.AX)
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RegisterOrPair.AY -> assignVirtualRegister(assign.target, RegisterOrPair.AY)
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RegisterOrPair.XY -> assignVirtualRegister(assign.target, RegisterOrPair.XY)
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@ -261,7 +261,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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if(assign.target.register==null) {
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// still need to assign the result to the target variable/etc.
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when(returnDt) {
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in ByteDatatypes -> assignRegisterByte(assign.target, CpuRegister.A, returnDt in SignedDatatypes) // function's byte result is in A
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in ByteDatatypes -> assignRegisterByte(assign.target, CpuRegister.A, returnDt in SignedDatatypes, false) // function's byte result is in A
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in WordDatatypes -> assignRegisterpairWord(assign.target, RegisterOrPair.AY) // function's word result is in AY
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DataType.STR -> {
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when (assign.target.datatype) {
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@ -306,7 +306,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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"not" -> throw AssemblyError("not should have been replaced in the Ast by ==0")
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else -> throw AssemblyError("invalid prefix operator")
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}
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assignRegisterByte(assign.target, CpuRegister.A, signed)
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assignRegisterByte(assign.target, CpuRegister.A, signed, false)
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} else {
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assignExpressionToRegister(value.value, RegisterOrPair.AY, signed)
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when(value.operator) {
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@ -376,7 +376,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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}
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is PtContainmentCheck -> {
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containmentCheckIntoA(value)
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assignRegisterByte(assign.target, CpuRegister.A, false)
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assignRegisterByte(assign.target, CpuRegister.A, false, true)
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}
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is PtBinaryExpression -> {
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if(!attemptAssignOptimizedBinexpr(value, assign)) {
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@ -415,7 +415,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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when(target.datatype) {
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in ByteDatatypes -> {
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asmgen.out(" lda cx16.${register.toString().lowercase()}L")
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assignRegisterByte(target, CpuRegister.A, false)
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assignRegisterByte(target, CpuRegister.A, false, false)
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}
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in WordDatatypes -> assignRegisterpairWord(target, register)
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else -> throw AssemblyError("expected byte or word")
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@ -493,7 +493,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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if(target.register==RegisterOrPair.A)
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asmgen.out(" cmp #0") // fix the status register
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else
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assignRegisterByte(target, CpuRegister.A, false)
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assignRegisterByte(target, CpuRegister.A, false, true)
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return true
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}
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DataType.UWORD -> {
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@ -513,7 +513,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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asmgen.out(" pha")
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assignExpressionToRegister(expr.right, RegisterOrPair.Y, false)
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asmgen.out(" pla | jsr math.divmod_ub_asm")
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assignRegisterByte(target, CpuRegister.Y, false)
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assignRegisterByte(target, CpuRegister.Y, false, true)
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return true
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}
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DataType.BYTE -> {
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@ -521,7 +521,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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asmgen.out(" pha")
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assignExpressionToRegister(expr.right, RegisterOrPair.Y, true)
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asmgen.out(" pla | jsr math.divmod_b_asm")
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assignRegisterByte(target, CpuRegister.Y, true)
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assignRegisterByte(target, CpuRegister.Y, true, true)
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return true
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}
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DataType.UWORD -> {
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@ -549,7 +549,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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asmgen.out(" pha")
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assignExpressionToRegister(expr.right, RegisterOrPair.Y, expr.type in SignedDatatypes)
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asmgen.out(" pla | jsr math.multiply_bytes")
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assignRegisterByte(target, CpuRegister.A, false)
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assignRegisterByte(target, CpuRegister.A, false, true)
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return true
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}
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in WordDatatypes -> {
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@ -587,7 +587,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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asmgen.out(" jsr math.mul_byte_${value}")
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else
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asmgen.out(" ldy #$value | jsr math.multiply_bytes")
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assignRegisterByte(target, CpuRegister.A, false)
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assignRegisterByte(target, CpuRegister.A, false, true)
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return true
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}
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in WordDatatypes -> {
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@ -647,7 +647,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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asmgen.out(" jsr math.lsr_ubyte_A")
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else
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asmgen.out(" jsr math.asl_byte_A")
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assignRegisterByte(target, CpuRegister.A, signed)
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assignRegisterByte(target, CpuRegister.A, signed, true)
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return true
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} else {
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assignExpressionToRegister(expr.left, RegisterOrPair.AY, signed)
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@ -682,7 +682,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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}
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}
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}
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assignRegisterByte(target, CpuRegister.A, signed)
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assignRegisterByte(target, CpuRegister.A, signed, true)
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return true
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}
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else -> {
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@ -691,7 +691,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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} else {
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asmgen.out(" lda #0")
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}
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assignRegisterByte(target, CpuRegister.A, signed)
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assignRegisterByte(target, CpuRegister.A, signed, true)
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return true
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}
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}
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@ -764,7 +764,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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asmgen.out(" clc | adc $symname")
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else
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asmgen.out(" sec | sbc $symname")
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assignRegisterByte(target, CpuRegister.A, dt in SignedDatatypes)
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assignRegisterByte(target, CpuRegister.A, dt in SignedDatatypes, true)
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return true
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}
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is PtNumber -> {
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@ -773,7 +773,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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asmgen.out(" clc | adc #${right.number.toHex()}")
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else
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asmgen.out(" sec | sbc #${right.number.toHex()}")
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assignRegisterByte(target, CpuRegister.A, dt in SignedDatatypes)
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assignRegisterByte(target, CpuRegister.A, dt in SignedDatatypes, true)
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return true
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}
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else -> {
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@ -804,7 +804,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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else
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asmgen.out(" sec | sbc $arrayvarname,y")
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}
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assignRegisterByte(target, CpuRegister.A, dt in SignedDatatypes)
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assignRegisterByte(target, CpuRegister.A, dt in SignedDatatypes, true)
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} else {
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assignExpressionToVariable(right, "P8ZP_SCRATCH_B1", right.type)
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assignExpressionToRegister(left, RegisterOrPair.A, left.type==DataType.BYTE)
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@ -812,7 +812,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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asmgen.out(" clc | adc P8ZP_SCRATCH_B1")
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else
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asmgen.out(" sec | sbc P8ZP_SCRATCH_B1")
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assignRegisterByte(target, CpuRegister.A, dt in SignedDatatypes)
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assignRegisterByte(target, CpuRegister.A, dt in SignedDatatypes, true)
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}
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return true
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}
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@ -1005,7 +1005,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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"^", "xor" -> asmgen.out(" eor P8ZP_SCRATCH_B1")
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else -> throw AssemblyError("invalid operator")
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}
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assignRegisterByte(target, CpuRegister.A, false)
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assignRegisterByte(target, CpuRegister.A, false, true)
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return true
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}
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else if (expr.left.type in WordDatatypes && expr.right.type in WordDatatypes) {
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@ -1044,7 +1044,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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else -> return false
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}
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assignRegisterByte(assign.target, CpuRegister.A, false)
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assignRegisterByte(assign.target, CpuRegister.A, false, true)
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return true
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}
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@ -1558,7 +1558,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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else -> return false
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}
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|
||||
assignRegisterByte(assign.target, CpuRegister.A, signed)
|
||||
assignRegisterByte(assign.target, CpuRegister.A, signed, true)
|
||||
return true
|
||||
}
|
||||
|
||||
@ -1575,7 +1575,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
"^", "xor" -> asmgen.out(" eor $operand")
|
||||
else -> throw AssemblyError("invalid operator")
|
||||
}
|
||||
assignRegisterByte(target, CpuRegister.A, false)
|
||||
assignRegisterByte(target, CpuRegister.A, false, true)
|
||||
}
|
||||
|
||||
private fun assignLogicalWithSimpleRightOperandWord(target: AsmAssignTarget, left: PtExpression, operator: String, right: PtExpression) {
|
||||
@ -1614,7 +1614,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
beq +
|
||||
lda #1
|
||||
+ eor #1""")
|
||||
assignRegisterByte(assign.target, CpuRegister.A, false)
|
||||
assignRegisterByte(assign.target, CpuRegister.A, false, false)
|
||||
return true
|
||||
}
|
||||
in WordDatatypes -> {
|
||||
@ -1625,13 +1625,13 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
beq +
|
||||
lda #1
|
||||
+ eor #1""")
|
||||
assignRegisterByte(assign.target, CpuRegister.A, false)
|
||||
assignRegisterByte(assign.target, CpuRegister.A, false, false)
|
||||
return true
|
||||
}
|
||||
DataType.FLOAT -> {
|
||||
assignExpressionToRegister(expr.left, RegisterOrPair.FAC1, true)
|
||||
asmgen.out(" jsr floats.SIGN | and #1 | eor #1")
|
||||
assignRegisterByte(assign.target, CpuRegister.A, false)
|
||||
assignRegisterByte(assign.target, CpuRegister.A, false, false)
|
||||
return true
|
||||
}
|
||||
else->{
|
||||
@ -1645,7 +1645,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
assignExpressionToRegister(expr.left, RegisterOrPair.A, dt==DataType.BYTE)
|
||||
asmgen.out(" beq + | lda #1")
|
||||
asmgen.out("+")
|
||||
assignRegisterByte(assign.target, CpuRegister.A, false)
|
||||
assignRegisterByte(assign.target, CpuRegister.A, false, false)
|
||||
return true
|
||||
}
|
||||
in WordDatatypes -> {
|
||||
@ -1653,13 +1653,13 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
asmgen.out(" sty P8ZP_SCRATCH_B1 | ora P8ZP_SCRATCH_B1")
|
||||
asmgen.out(" beq + | lda #1")
|
||||
asmgen.out("+")
|
||||
assignRegisterByte(assign.target, CpuRegister.A, false)
|
||||
assignRegisterByte(assign.target, CpuRegister.A, false, false)
|
||||
return true
|
||||
}
|
||||
DataType.FLOAT -> {
|
||||
assignExpressionToRegister(expr.left, RegisterOrPair.FAC1, true)
|
||||
asmgen.out(" jsr floats.SIGN")
|
||||
assignRegisterByte(assign.target, CpuRegister.A, true)
|
||||
assignRegisterByte(assign.target, CpuRegister.A, true, false)
|
||||
return true
|
||||
}
|
||||
else->{
|
||||
@ -1731,7 +1731,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
}
|
||||
else -> throw AssemblyError("can't use Z or N flags as return 'values'")
|
||||
}
|
||||
assignRegisterByte(target, CpuRegister.A, false)
|
||||
assignRegisterByte(target, CpuRegister.A, false, true)
|
||||
}
|
||||
|
||||
private fun assignTypeCastedValue(target: AsmAssignTarget, targetDt: DataType, value: PtExpression, origTypeCastExpression: PtTypeCast) {
|
||||
@ -1840,7 +1840,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
RegisterOrPair.XY,
|
||||
in Cx16VirtualRegisters -> {
|
||||
assignExpressionToRegister(value, RegisterOrPair.A, false)
|
||||
assignRegisterByte(target, CpuRegister.A, false)
|
||||
assignRegisterByte(target, CpuRegister.A, false, true)
|
||||
return
|
||||
}
|
||||
else -> {}
|
||||
@ -2770,13 +2770,33 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
}
|
||||
}
|
||||
|
||||
internal fun assignRegisterByte(target: AsmAssignTarget, register: CpuRegister, signed: Boolean) {
|
||||
private fun extendToMSBofVirtualReg(cpuRegister: CpuRegister, vreg: String, signed: Boolean) {
|
||||
if(signed) {
|
||||
when(cpuRegister) {
|
||||
CpuRegister.A -> { }
|
||||
CpuRegister.X -> asmgen.out(" txa")
|
||||
CpuRegister.Y -> asmgen.out(" tya")
|
||||
}
|
||||
asmgen.out("""
|
||||
ora #$7f
|
||||
bmi +
|
||||
lda #0
|
||||
+ sta $vreg+1""")
|
||||
} else {
|
||||
if(asmgen.isTargetCpu(CpuType.CPU65c02))
|
||||
asmgen.out(" stz $vreg+1")
|
||||
else
|
||||
asmgen.out(" lda #0 | sta $vreg+1")
|
||||
}
|
||||
}
|
||||
|
||||
internal fun assignRegisterByte(target: AsmAssignTarget, register: CpuRegister, signed: Boolean, extendWord: Boolean) {
|
||||
val assignAsWord = target.datatype in WordDatatypes
|
||||
|
||||
when(target.kind) {
|
||||
TargetStorageKind.VARIABLE -> {
|
||||
asmgen.out(" st${register.name.lowercase()} ${target.asmVarname}")
|
||||
if(assignAsWord) {
|
||||
if(assignAsWord && extendWord) {
|
||||
if(target.datatype in SignedDatatypes) {
|
||||
if(register!=CpuRegister.A)
|
||||
asmgen.out(" t${register.name.lowercase()}a")
|
||||
@ -2801,7 +2821,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
TargetStorageKind.ARRAY -> {
|
||||
if(assignAsWord)
|
||||
TODO("assign register byte as word into Array not yet supported")
|
||||
assignRegisterByteToArray(target, register)
|
||||
assignRegisterByteToByteArray(target, register)
|
||||
}
|
||||
TargetStorageKind.REGISTER -> {
|
||||
when(register) {
|
||||
@ -2810,6 +2830,9 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
RegisterOrPair.X -> { asmgen.out(" tax") }
|
||||
RegisterOrPair.Y -> { asmgen.out(" tay") }
|
||||
RegisterOrPair.AY -> {
|
||||
require(extendWord) {
|
||||
"no extend"
|
||||
}
|
||||
if(signed)
|
||||
asmgen.out("""
|
||||
ldy #0
|
||||
@ -2821,6 +2844,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
asmgen.out(" ldy #0")
|
||||
}
|
||||
RegisterOrPair.AX -> {
|
||||
require(extendWord)
|
||||
if(signed)
|
||||
asmgen.out("""
|
||||
ldx #0
|
||||
@ -2832,6 +2856,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
asmgen.out(" ldx #0")
|
||||
}
|
||||
RegisterOrPair.XY -> {
|
||||
require(extendWord)
|
||||
if(signed)
|
||||
asmgen.out("""
|
||||
tax
|
||||
@ -2845,8 +2870,10 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
}
|
||||
RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected type cast to float")
|
||||
in Cx16VirtualRegisters -> {
|
||||
// only assign a single byte to the virtual register's Lsb
|
||||
asmgen.out(" sta cx16.${target.register.toString().lowercase()}")
|
||||
val reg = "cx16.${target.register.toString().lowercase()}"
|
||||
asmgen.out(" sta $reg")
|
||||
if(extendWord)
|
||||
extendToMSBofVirtualReg(CpuRegister.A, reg, signed)
|
||||
}
|
||||
else -> throw AssemblyError("weird register")
|
||||
}
|
||||
@ -2855,6 +2882,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
RegisterOrPair.X -> { }
|
||||
RegisterOrPair.Y -> { asmgen.out(" txy") }
|
||||
RegisterOrPair.AY -> {
|
||||
require(extendWord)
|
||||
if(signed)
|
||||
asmgen.out("""
|
||||
txa
|
||||
@ -2867,6 +2895,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
asmgen.out(" txa | ldy #0")
|
||||
}
|
||||
RegisterOrPair.AX -> {
|
||||
require(extendWord)
|
||||
if(signed)
|
||||
asmgen.out("""
|
||||
txa
|
||||
@ -2879,6 +2908,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
asmgen.out(" txa | ldx #0")
|
||||
}
|
||||
RegisterOrPair.XY -> {
|
||||
require(extendWord)
|
||||
if(signed)
|
||||
asmgen.out("""
|
||||
ldy #0
|
||||
@ -2891,8 +2921,10 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
}
|
||||
RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected type cast to float")
|
||||
in Cx16VirtualRegisters -> {
|
||||
// only assign a single byte to the virtual register's Lsb
|
||||
asmgen.out(" stx cx16.${target.register.toString().lowercase()}")
|
||||
val reg = "cx16.${target.register.toString().lowercase()}"
|
||||
asmgen.out(" stx $reg")
|
||||
if(extendWord)
|
||||
extendToMSBofVirtualReg(CpuRegister.X, reg, signed)
|
||||
}
|
||||
else -> throw AssemblyError("weird register")
|
||||
}
|
||||
@ -2901,6 +2933,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
RegisterOrPair.X -> { asmgen.out(" tyx") }
|
||||
RegisterOrPair.Y -> { }
|
||||
RegisterOrPair.AY -> {
|
||||
require(extendWord)
|
||||
if(signed)
|
||||
asmgen.out("""
|
||||
tya
|
||||
@ -2913,6 +2946,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
asmgen.out(" tya | ldy #0")
|
||||
}
|
||||
RegisterOrPair.AX -> {
|
||||
require(extendWord)
|
||||
if(signed)
|
||||
asmgen.out("""
|
||||
tya
|
||||
@ -2925,6 +2959,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
asmgen.out(" tya | ldx #0")
|
||||
}
|
||||
RegisterOrPair.XY -> {
|
||||
require(extendWord)
|
||||
if(signed)
|
||||
asmgen.out("""
|
||||
tya
|
||||
@ -2939,8 +2974,10 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
}
|
||||
RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected type cast to float")
|
||||
in Cx16VirtualRegisters -> {
|
||||
// only assign a single byte to the virtual register's Lsb
|
||||
asmgen.out(" sty cx16.${target.register.toString().lowercase()}")
|
||||
val reg = "cx16.${target.register.toString().lowercase()}"
|
||||
asmgen.out(" sty $reg")
|
||||
if(extendWord)
|
||||
extendToMSBofVirtualReg(CpuRegister.Y, reg, signed)
|
||||
}
|
||||
else -> throw AssemblyError("weird register")
|
||||
}
|
||||
@ -2949,7 +2986,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
}
|
||||
}
|
||||
|
||||
private fun assignRegisterByteToArray(target: AsmAssignTarget, register: CpuRegister) {
|
||||
private fun assignRegisterByteToByteArray(target: AsmAssignTarget, register: CpuRegister) {
|
||||
if(target.array!!.splitWords)
|
||||
throw AssemblyError("cannot assign byte to split word array here ${target.position}")
|
||||
|
||||
@ -3553,7 +3590,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
}
|
||||
TargetStorageKind.ARRAY -> {
|
||||
asmgen.out(" lda ${address.toHex()}")
|
||||
assignRegisterByte(target, CpuRegister.A, false)
|
||||
assignRegisterByte(target, CpuRegister.A, false, true)
|
||||
}
|
||||
TargetStorageKind.REGISTER -> when(target.register!!) {
|
||||
RegisterOrPair.A -> asmgen.out(" lda ${address.toHex()}")
|
||||
@ -3587,7 +3624,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
}
|
||||
TargetStorageKind.ARRAY -> {
|
||||
asmgen.loadByteFromPointerIntoA(identifier)
|
||||
assignRegisterByte(target, CpuRegister.A, false)
|
||||
assignRegisterByte(target, CpuRegister.A, false, true)
|
||||
}
|
||||
TargetStorageKind.REGISTER -> {
|
||||
asmgen.loadByteFromPointerIntoA(identifier)
|
||||
|
||||
@ -1,8 +1,6 @@
|
||||
TODO
|
||||
====
|
||||
|
||||
- fix the parameter passing bug intruduced recently. Example: cx16.FB_cursor_position(math.rnd(), math.rnd())
|
||||
|
||||
- add a %zpallowed option to specify the range of zeropage register that can be used (intersect with the actual available zp registers ofcourse)
|
||||
|
||||
- [on branch: shortcircuit] investigate McCarthy evaluation again? this may also reduce code size perhaps for things like if a>4 or a<2 ....
|
||||
|
||||
Loading…
Reference in New Issue
Block a user