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fix rounding errors in signed divide by power-of-two

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The optimized bit-shifting division is removed (for now)
This commit is contained in:
Irmen de Jong
2022-07-24 12:21:10 +02:00
parent 05f935b598
commit dcc1f00048
5 changed files with 35 additions and 49 deletions
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codeGenVirtual/src/prog8/codegen/virtual/CodeGen.kt
+4 -4
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@@ -511,14 +511,14 @@ class CodeGen(internal val program: PtProgram,
if(factor==1)
return code
val pow2 = powersOfTwo.indexOf(factor)
if(pow2==1) {
if(pow2==1 && !signed) {
// just shift 1 bit
code += if(signed)
VmCodeInstruction(Opcode.ASR, dt, reg1=reg)
else
VmCodeInstruction(Opcode.LSR, dt, reg1=reg)
}
else if(pow2>=1) {
else if(pow2>=1 &&!signed) {
// just shift multiple bits
val pow2reg = vmRegisters.nextFree()
code += VmCodeInstruction(Opcode.LOAD, dt, reg1=pow2reg, value=pow2)
@@ -544,14 +544,14 @@ class CodeGen(internal val program: PtProgram,
if(factor==1)
return code
val pow2 = powersOfTwo.indexOf(factor)
if(pow2==1) {
if(pow2==1 && !signed) {
// just shift 1 bit
code += if(signed)
VmCodeInstruction(Opcode.ASRM, dt, value=address)
else
VmCodeInstruction(Opcode.LSRM, dt, value=address)
}
else if(pow2>=1) {
else if(pow2>=1 && !signed) {
// just shift multiple bits
val pow2reg = vmRegisters.nextFree()
code += VmCodeInstruction(Opcode.LOAD, dt, reg1=pow2reg, value=pow2)