vm: split off assignment codegen to its own file

2026-04-19 20:16:51 +00:00 · 2022-05-17 22:38:31 +02:00
parent dc6475c91b
commit e52d9e3210
6 changed files with 180 additions and 222 deletions
@@ -0,0 +1,136 @@
+package prog8.codegen.virtual
+
+import prog8.code.ast.*
+import prog8.code.core.AssemblyError
+import prog8.code.core.DataType
+import prog8.vm.Opcode
+import prog8.vm.VmDataType
+
+internal class AssignmentGen(private val codeGen: CodeGen, private val expressionEval: ExpressionGen) {
+
+    internal fun translate(assignment: PtAssignment): VmCodeChunk {
+        return if (assignment.isInplaceAssign)
+            translateInplaceAssign(assignment)
+        else
+            translateRegularAssign(assignment)
+    }
+
+    private fun translateInplaceAssign(assignment: PtAssignment): VmCodeChunk {
+        // TODO can in-place assignments be optimized more? use special memory versions of instructions instead of register ones?
+        return translateRegularAssign(assignment)
+    }
+
+    private fun translateRegularAssign(assignment: PtAssignment): VmCodeChunk {
+        // note: assigning array and string values is done via an explicit memcopy/stringcopy function call.
+        if(assignment.target.children.single() is PtMachineRegister)
+            throw AssemblyError("assigning to a register should be done by just evaluating the expression into resultregister")
+        val ident = assignment.target.identifier
+        val memory = assignment.target.memory
+        val array = assignment.target.array
+        val vmDt = codeGen.vmType(assignment.value.type)
+
+        val code = VmCodeChunk()
+        var resultRegister = -1
+        var resultFpRegister = -1
+        val zero = codeGen.isZero(assignment.value)
+        if(!zero) {
+            // calculate the assignment value
+            if (vmDt == VmDataType.FLOAT) {
+                resultFpRegister = codeGen.vmRegisters.nextFreeFloat()
+                code += expressionEval.translateExpression(assignment.value, -1, resultFpRegister)
+            } else {
+                resultRegister = if (assignment.value is PtMachineRegister) {
+                    (assignment.value as PtMachineRegister).register
+                } else {
+                    val reg = codeGen.vmRegisters.nextFree()
+                    code += expressionEval.translateExpression(assignment.value, reg, -1)
+                    reg
+                }
+            }
+        }
+        if(ident!=null) {
+            val address = codeGen.allocations.get(ident.targetName)
+            code += if(zero) {
+                VmCodeInstruction(Opcode.STOREZM, vmDt, value = address)
+            } else {
+                if (vmDt == VmDataType.FLOAT)
+                    VmCodeInstruction(Opcode.STOREM, vmDt, fpReg1 = resultFpRegister, value = address)
+                else
+                    VmCodeInstruction(Opcode.STOREM, vmDt, reg1 = resultRegister, value = address)
+            }
+        }
+        else if(array!=null) {
+            val variable = array.variable.targetName
+            var variableAddr = codeGen.allocations.get(variable)
+            val itemsize = codeGen.program.memsizer.memorySize(array.type)
+            val fixedIndex = constIntValue(array.index)
+            if(zero) {
+                if(fixedIndex!=null) {
+                    variableAddr += fixedIndex*itemsize
+                    code += VmCodeInstruction(Opcode.STOREZM, VmDataType.FLOAT, value=variableAddr)
+                } else {
+                    val indexReg = codeGen.vmRegisters.nextFree()
+                    code += loadIndexReg(array, itemsize, indexReg)
+                    code += VmCodeInstruction(Opcode.STOREZX, VmDataType.FLOAT, reg1=indexReg, value=variableAddr)
+                }
+            } else {
+                if(vmDt== VmDataType.FLOAT) {
+                    if(fixedIndex!=null) {
+                        variableAddr += fixedIndex*itemsize
+                        code += VmCodeInstruction(Opcode.STOREM, vmDt, fpReg1 = resultFpRegister, value=variableAddr)
+                    } else {
+                        val indexReg = codeGen.vmRegisters.nextFree()
+                        code += loadIndexReg(array, itemsize, indexReg)
+                        code += VmCodeInstruction(Opcode.STOREX, vmDt, reg1 = resultRegister, reg2=indexReg, value=variableAddr)
+                    }
+                } else {
+                    if(fixedIndex!=null) {
+                        variableAddr += fixedIndex*itemsize
+                        code += VmCodeInstruction(Opcode.STOREM, vmDt, reg1 = resultRegister, value=variableAddr)
+                    } else {
+                        val indexReg = codeGen.vmRegisters.nextFree()
+                        code += loadIndexReg(array, itemsize, indexReg)
+                        code += VmCodeInstruction(Opcode.STOREX, vmDt, reg1 = resultRegister, reg2=indexReg, value=variableAddr)
+                    }
+                }
+            }
+        }
+        else if(memory!=null) {
+            require(vmDt== VmDataType.BYTE)
+            if(zero) {
+                if(memory.address is PtNumber) {
+                    code += VmCodeInstruction(Opcode.STOREZM, vmDt, value=(memory.address as PtNumber).number.toInt())
+                } else {
+                    val addressReg = codeGen.vmRegisters.nextFree()
+                    code += expressionEval.translateExpression(memory.address, addressReg, -1)
+                    code += VmCodeInstruction(Opcode.STOREZI, vmDt, reg1=addressReg)
+                }
+            } else {
+                if(memory.address is PtNumber) {
+                    code += VmCodeInstruction(Opcode.STOREM, vmDt, reg1=resultRegister, value=(memory.address as PtNumber).number.toInt())
+                } else {
+                    val addressReg = codeGen.vmRegisters.nextFree()
+                    code += expressionEval.translateExpression(memory.address, addressReg, -1)
+                    code += VmCodeInstruction(Opcode.STOREI, vmDt, reg1=resultRegister, reg2=addressReg)
+                }
+            }
+        }
+        else
+            throw AssemblyError("weird assigntarget")
+        return code
+    }
+
+    private fun loadIndexReg(array: PtArrayIndexer, itemsize: Int, indexReg: Int): VmCodeChunk {
+        val code = VmCodeChunk()
+        if(itemsize==1) {
+            code += expressionEval.translateExpression(array.index, indexReg, -1)
+        }
+        else {
+            val mult = PtBinaryExpression("*", DataType.UBYTE, array.position)
+            mult.children += array.index
+            mult.children += PtNumber(DataType.UBYTE, itemsize.toDouble(), array.position)
+            code += expressionEval.translateExpression(mult, indexReg, -1)
+        }
+        return code
+    }
+}
@@ -43,6 +43,7 @@ class CodeGen(internal val program: PtProgram,
    internal val allocations = VariableAllocator(symbolTable, program, errors)
    private val expressionEval = ExpressionGen(this)
    private val builtinFuncGen = BuiltinFuncGen(this, expressionEval)
+    private val assignmentGen = AssignmentGen(this, expressionEval)
    internal val vmRegisters = VmRegisterPool()

    override fun compileToAssembly(): IAssemblyProgram? {
@@ -52,7 +53,7 @@ class CodeGen(internal val program: PtProgram,
            // collect global variables initializers
            program.allBlocks().forEach {
                val code = VmCodeChunk()
-                it.children.filterIsInstance<PtAssignment>().forEach { assign -> code += translate(assign) }
+                it.children.filterIsInstance<PtAssignment>().forEach { assign -> code += assignmentGen.translate(assign) }
                vmprog.addGlobalInits(code)
            }
        }
@@ -75,7 +76,7 @@ class CodeGen(internal val program: PtProgram,
            is PtVariable -> VmCodeChunk() // var should be looked up via symbol table
            is PtMemMapped -> VmCodeChunk() // memmapped var should be looked up via symbol table
            is PtConstant -> VmCodeChunk() // constants have all been folded into the code
-            is PtAssignment -> translate(node)
+            is PtAssignment -> assignmentGen.translate(node)
            is PtNodeGroup -> translateGroup(node.children)
            is PtBuiltinFunctionCall -> translateBuiltinFunc(node, 0)
            is PtFunctionCall -> expressionEval.translate(node, 0, 0)
@@ -651,120 +652,6 @@ class CodeGen(internal val program: PtProgram,
        return code
    }

-    private fun translate(assignment: PtAssignment): VmCodeChunk {
-        // TODO can in-place assignments be optimized more? use special memory versions of instructions instead of register ones?
-        // note: assigning array and string values is done via an explicit memcopy/stringcopy function call.
-        if(assignment.target.children.single() is PtMachineRegister)
-            throw AssemblyError("assigning to a register should be done by just evaluating the expression into resultregister")
-        val code = VmCodeChunk()
-        val ident = assignment.target.identifier
-        val memory = assignment.target.memory
-        val array = assignment.target.array
-        val vmDt = vmType(assignment.value.type)
-        var resultRegister = -1
-        var resultFpRegister = -1
-        val zero = isZero(assignment.value)
-        if(!zero) {
-            // calculate the assignment value
-            if (vmDt == VmDataType.FLOAT) {
-                resultFpRegister = vmRegisters.nextFreeFloat()
-                code += expressionEval.translateExpression(assignment.value, -1, resultFpRegister)
-            } else {
-                resultRegister = if (assignment.value is PtMachineRegister) {
-                    (assignment.value as PtMachineRegister).register
-                } else {
-                    val reg = vmRegisters.nextFree()
-                    code += expressionEval.translateExpression(assignment.value, reg, -1)
-                    reg
-                }
-            }
-        }
-        if(ident!=null) {
-            val address = allocations.get(ident.targetName)
-            code += if(zero) {
-                VmCodeInstruction(Opcode.STOREZM, vmDt, value = address)
-            } else {
-                if (vmDt == VmDataType.FLOAT)
-                    VmCodeInstruction(Opcode.STOREM, vmDt, fpReg1 = resultFpRegister, value = address)
-                else
-                    VmCodeInstruction(Opcode.STOREM, vmDt, reg1 = resultRegister, value = address)
-            }
-        }
-        else if(array!=null) {
-            val variable = array.variable.targetName
-            var variableAddr = allocations.get(variable)
-            val itemsize = program.memsizer.memorySize(array.type)
-            val fixedIndex = constIntValue(array.index)
-            if(zero) {
-                if(fixedIndex!=null) {
-                    variableAddr += fixedIndex*itemsize
-                    code += VmCodeInstruction(Opcode.STOREZM, VmDataType.FLOAT, value=variableAddr)
-                } else {
-                    val indexReg = vmRegisters.nextFree()
-                    code += loadIndexReg(array, itemsize, indexReg)
-                    code += VmCodeInstruction(Opcode.STOREZX, VmDataType.FLOAT, reg1=indexReg, value=variableAddr)
-                }
-            } else {
-                if(vmDt==VmDataType.FLOAT) {
-                    if(fixedIndex!=null) {
-                        variableAddr += fixedIndex*itemsize
-                        code += VmCodeInstruction(Opcode.STOREM, vmDt, fpReg1 = resultFpRegister, value=variableAddr)
-                    } else {
-                        val indexReg = vmRegisters.nextFree()
-                        code += loadIndexReg(array, itemsize, indexReg)
-                        code += VmCodeInstruction(Opcode.STOREX, vmDt, reg1 = resultRegister, reg2=indexReg, value=variableAddr)
-                    }
-                } else {
-                    if(fixedIndex!=null) {
-                        variableAddr += fixedIndex*itemsize
-                        code += VmCodeInstruction(Opcode.STOREM, vmDt, reg1 = resultRegister, value=variableAddr)
-                    } else {
-                        val indexReg = vmRegisters.nextFree()
-                        code += loadIndexReg(array, itemsize, indexReg)
-                        code += VmCodeInstruction(Opcode.STOREX, vmDt, reg1 = resultRegister, reg2=indexReg, value=variableAddr)
-                    }
-                }
-            }
-        }
-        else if(memory!=null) {
-            require(vmDt==VmDataType.BYTE)
-            if(zero) {
-                if(memory.address is PtNumber) {
-                    code += VmCodeInstruction(Opcode.STOREZM, vmDt, value=(memory.address as PtNumber).number.toInt())
-                } else {
-                    val addressReg = vmRegisters.nextFree()
-                    code += expressionEval.translateExpression(memory.address, addressReg, -1)
-                    code += VmCodeInstruction(Opcode.STOREZI, vmDt, reg1=addressReg)
-                }
-            } else {
-                if(memory.address is PtNumber) {
-                    code += VmCodeInstruction(Opcode.STOREM, vmDt, reg1=resultRegister, value=(memory.address as PtNumber).number.toInt())
-                } else {
-                    val addressReg = vmRegisters.nextFree()
-                    code += expressionEval.translateExpression(memory.address, addressReg, -1)
-                    code += VmCodeInstruction(Opcode.STOREI, vmDt, reg1=resultRegister, reg2=addressReg)
-                }
-            }
-        }
-        else
-            throw AssemblyError("weird assigntarget")
-        return code
-    }
-
-    private fun loadIndexReg(array: PtArrayIndexer, itemsize: Int, indexReg: Int): VmCodeChunk {
-        val code = VmCodeChunk()
-        if(itemsize==1) {
-            code += expressionEval.translateExpression(array.index, indexReg, -1)
-        }
-        else {
-            val mult = PtBinaryExpression("*", DataType.UBYTE, array.position)
-            mult.children += array.index
-            mult.children += PtNumber(DataType.UBYTE, itemsize.toDouble(), array.position)
-            code += expressionEval.translateExpression(mult, indexReg, -1)
-        }
-        return code
-    }
-
    private fun translate(ret: PtReturn): VmCodeChunk {
        val code = VmCodeChunk()
        val value = ret.value
@@ -828,3 +715,4 @@ class CodeGen(internal val program: PtProgram,

    internal fun isOne(expression: PtExpression): Boolean = expression is PtNumber && expression.number==1.0
 }
+