mirror of
https://github.com/irmen/prog8.git
synced 2024-06-25 15:29:45 +00:00
vm instructions now contain info on input/output registers
This commit is contained in:
Irmen de Jong
parent
1e441c2ddf
commit
e560e2ab3f
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@ -68,7 +68,7 @@ class CodeGen(internal val program: PtProgram,
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}
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if(options.optimize) {
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val optimizer = VmPeepholeOptimizer(vmprog, allocations)
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val optimizer = VmPeepholeOptimizer(vmprog)
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optimizer.optimize()
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}
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@ -4,10 +4,8 @@ import prog8.vm.Instruction
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import prog8.vm.Opcode
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import prog8.vm.VmDataType
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internal class VmOptimizerException(msg: String): Exception(msg)
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class VmPeepholeOptimizer(private val vmprog: AssemblyProgram, private val allocations: VariableAllocator) {
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class VmPeepholeOptimizer(private val vmprog: AssemblyProgram) {
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fun optimize() {
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vmprog.getBlocks().forEach { block ->
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do {
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@ -26,19 +26,19 @@ class TestVmPeepholeOpt: FunSpec({
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fun AssemblyProgram.lines(): List<VmCodeLine> = this.getBlocks().flatMap { it.lines }
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test("remove nops") {
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val(asm, allocations) = makeVmProgram(listOf(
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val(asm, _) = makeVmProgram(listOf(
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VmCodeInstruction(Opcode.JUMP, labelSymbol = listOf("dummy")),
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VmCodeInstruction(Opcode.NOP),
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VmCodeInstruction(Opcode.NOP)
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))
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asm.lines().size shouldBe 3
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val opt = VmPeepholeOptimizer(asm, allocations)
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val opt = VmPeepholeOptimizer(asm)
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opt.optimize()
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asm.lines().size shouldBe 1
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}
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test("remove jmp to label below") {
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val(asm, allocations) = makeVmProgram(listOf(
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val(asm, _) = makeVmProgram(listOf(
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VmCodeInstruction(Opcode.JUMP, labelSymbol = listOf("label")), // removed
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VmCodeLabel(listOf("label")),
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VmCodeInstruction(Opcode.JUMP, labelSymbol = listOf("label2")), // removed
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@ -49,7 +49,7 @@ class TestVmPeepholeOpt: FunSpec({
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VmCodeLabel(listOf("label3"))
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))
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asm.lines().size shouldBe 8
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val opt = VmPeepholeOptimizer(asm, allocations)
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val opt = VmPeepholeOptimizer(asm)
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opt.optimize()
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val lines = asm.lines()
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lines.size shouldBe 5
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@ -61,7 +61,7 @@ class TestVmPeepholeOpt: FunSpec({
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}
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test("remove double sec/clc") {
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val(asm, allocations) = makeVmProgram(listOf(
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val(asm, _) = makeVmProgram(listOf(
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VmCodeInstruction(Opcode.SEC),
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VmCodeInstruction(Opcode.SEC),
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VmCodeInstruction(Opcode.SEC),
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@ -70,7 +70,7 @@ class TestVmPeepholeOpt: FunSpec({
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VmCodeInstruction(Opcode.CLC)
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))
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asm.lines().size shouldBe 6
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val opt = VmPeepholeOptimizer(asm, allocations)
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val opt = VmPeepholeOptimizer(asm)
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opt.optimize()
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val lines = asm.lines()
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lines.size shouldBe 1
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@ -78,14 +78,14 @@ class TestVmPeepholeOpt: FunSpec({
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}
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test("push followed by pop") {
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val(asm, allocations) = makeVmProgram(listOf(
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val(asm, _) = makeVmProgram(listOf(
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VmCodeInstruction(Opcode.PUSH, VmDataType.BYTE, reg1=42),
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VmCodeInstruction(Opcode.POP, VmDataType.BYTE, reg1=42),
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VmCodeInstruction(Opcode.PUSH, VmDataType.BYTE, reg1=99),
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VmCodeInstruction(Opcode.POP, VmDataType.BYTE, reg1=222)
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))
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asm.lines().size shouldBe 4
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val opt = VmPeepholeOptimizer(asm, allocations)
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val opt = VmPeepholeOptimizer(asm)
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opt.optimize()
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val lines = asm.lines()
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lines.size shouldBe 1
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@ -95,7 +95,7 @@ class TestVmPeepholeOpt: FunSpec({
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}
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test("remove useless div/mul, add/sub") {
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val(asm, allocations) = makeVmProgram(listOf(
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val(asm, _) = makeVmProgram(listOf(
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VmCodeInstruction(Opcode.DIV, VmDataType.BYTE, reg1=42, value = 1),
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VmCodeInstruction(Opcode.DIVS, VmDataType.BYTE, reg1=42, value = 1),
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VmCodeInstruction(Opcode.MUL, VmDataType.BYTE, reg1=42, value = 1),
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@ -108,19 +108,19 @@ class TestVmPeepholeOpt: FunSpec({
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VmCodeInstruction(Opcode.SUB, VmDataType.BYTE, reg1=42, value = 0)
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))
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asm.lines().size shouldBe 10
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val opt = VmPeepholeOptimizer(asm, allocations)
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val opt = VmPeepholeOptimizer(asm)
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opt.optimize()
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val lines = asm.lines()
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lines.size shouldBe 4
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}
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test("replace add/sub 1 by inc/dec") {
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val(asm, allocations) = makeVmProgram(listOf(
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val(asm, _) = makeVmProgram(listOf(
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VmCodeInstruction(Opcode.ADD, VmDataType.BYTE, reg1=42, value = 1),
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VmCodeInstruction(Opcode.SUB, VmDataType.BYTE, reg1=42, value = 1)
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))
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asm.lines().size shouldBe 2
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val opt = VmPeepholeOptimizer(asm, allocations)
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val opt = VmPeepholeOptimizer(asm)
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opt.optimize()
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val lines = asm.lines()
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lines.size shouldBe 2
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@ -129,7 +129,7 @@ class TestVmPeepholeOpt: FunSpec({
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}
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test("remove useless and/or/xor") {
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val(asm, allocations) = makeVmProgram(listOf(
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val(asm, _) = makeVmProgram(listOf(
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VmCodeInstruction(Opcode.AND, VmDataType.BYTE, reg1=42, value = 255),
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VmCodeInstruction(Opcode.AND, VmDataType.WORD, reg1=42, value = 65535),
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VmCodeInstruction(Opcode.OR, VmDataType.BYTE, reg1=42, value = 0),
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@ -140,21 +140,21 @@ class TestVmPeepholeOpt: FunSpec({
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VmCodeInstruction(Opcode.XOR, VmDataType.BYTE, reg1=42, value = 1)
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))
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asm.lines().size shouldBe 8
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val opt = VmPeepholeOptimizer(asm, allocations)
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val opt = VmPeepholeOptimizer(asm)
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opt.optimize()
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val lines = asm.lines()
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lines.size shouldBe 4
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}
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test("replace and/or/xor by constant number") {
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val(asm, allocations) = makeVmProgram(listOf(
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val(asm, _) = makeVmProgram(listOf(
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VmCodeInstruction(Opcode.AND, VmDataType.BYTE, reg1=42, value = 0),
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VmCodeInstruction(Opcode.AND, VmDataType.WORD, reg1=42, value = 0),
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VmCodeInstruction(Opcode.OR, VmDataType.BYTE, reg1=42, value = 255),
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VmCodeInstruction(Opcode.OR, VmDataType.WORD, reg1=42, value = 65535)
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))
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asm.lines().size shouldBe 4
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val opt = VmPeepholeOptimizer(asm, allocations)
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val opt = VmPeepholeOptimizer(asm)
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opt.optimize()
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val lines = asm.lines()
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lines.size shouldBe 4
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@ -84,7 +84,7 @@ sub log2(float value) -> float {
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sub sqrt(float value) -> float {
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%asm {{
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loadm.f fr0,{floats.sqrt.value}
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fsqrt.f fr0,fr0
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sqrt.f fr0,fr0
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return
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}}
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}
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@ -16,7 +16,6 @@ Need help with
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Future Things and Ideas
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^^^^^^^^^^^^^^^^^^^^^^^
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Compiler:
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- vm Instructions needs to know what the read-registers/memory are, and what the write-register/memory is. This info is needed for more advanced optimizations and later code generation steps.
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- vm: implement remaining sin/cos functions in math.p8
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- vm: find a solution for the cx16.r0..r15 that "overlap" (r0, r0L, r0H etc) but in the vm each get their own separate variable location now
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- vm: encode romsub & romsub call in VM IR (but just crash in virtualmachine itself.) ExpressionGen.kt
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@ -29,7 +28,7 @@ Compiler:
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How is it for the vm target? -> just 2 special cases in CodeGen.
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- when the vm is stable and *if* its language can get promoted to prog8 IL, the variable allocation should be changed.
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It's now done before the vm code generation, but the IL should probably not depend on the allocations already performed.
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So the CodeGen doesn't do VariableAlloc *before* the codegen, but as a last step.
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So the CodeGen doesn't do VariableAlloc *before* the codegen, but as a last step instead.
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- generate WASM from the new ast (or from vm code?) to run prog8 on a browser canvas?
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- createAssemblyAndAssemble(): make it possible to actually get rid of the VarDecl nodes by fixing the rest of the code mentioned there.
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but probably better to rewrite the 6502 codegen on top of the new Ast.
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@ -208,7 +208,7 @@ class Assembler {
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if(format.fpValue)
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floatValue = value!!
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program.add(Instruction(opcode, type, reg1, reg2, fpReg1, fpReg2, value = intValue, fpValue = floatValue))
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program.add(Instruction(opcode, type, reg1, reg2, fpReg1, fpReg2, intValue, floatValue))
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}
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}
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@ -128,31 +128,31 @@ All have type b or w.
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andr reg1, reg2 - reg1 = reg1 bitwise and reg2
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and reg1, value - reg1 = reg1 bitwise and value
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andm reg1 address - memory = memory bitwise and reg1
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orr reg1, reg2 - reg1 = reg1 bitwise or reg2
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or reg1, value - reg1 = reg1 bitwise or value
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orm reg1, address - memory = memory bitwise or reg1
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xorr reg1, reg2 - reg1 = reg1 bitwise xor reg2
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xor reg1, value - reg1 = reg1 bitwise xor value
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xorm reg1, address - memory = memory bitwise xor reg1
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inv reg1 - reg1 = bitwise invert of reg1 (all bits flipped)
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lsrn reg1, reg2 - reg1 = multi-shift reg1 right by reg2 bits + set Carry to shifted bit
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invm address - memory = bitwise invert of that memory (all bits flipped)
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asrn reg1, reg2 - reg1 = multi-shift reg1 right by reg2 bits (signed) + set Carry to shifted bit
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lsrn reg1, reg2 - reg1 = multi-shift reg1 right by reg2 bits + set Carry to shifted bit
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lsln reg1, reg2 - reg1 = multi-shift reg1 left by reg2 bits + set Carry to shifted bit
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lsr reg1 - shift reg1 right by 1 bits + set Carry to shifted bit
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asrnm reg1, address - multi-shift memory right by reg1 bits (signed) + set Carry to shifted bit
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lsrnm reg1, address - multi-shift memoryright by reg1 bits + set Carry to shifted bit
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lslnm reg1, address - multi-shift memory left by reg1 bits + set Carry to shifted bit
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asr reg1 - shift reg1 right by 1 bits (signed) + set Carry to shifted bit
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lsr reg1 - shift reg1 right by 1 bits + set Carry to shifted bit
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lsl reg1 - shift reg1 left by 1 bits + set Carry to shifted bit
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lsrm address - shift memory right by 1 bits + set Carry to shifted bit
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asrm address - shift memory right by 1 bits (signed) + set Carry to shifted bit
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lslm address - shift memory left by 1 bits + set Carry to shifted bit
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ror reg1 - rotate reg1 right by 1 bits, not using carry + set Carry to shifted bit
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roxr reg1 - rotate reg1 right by 1 bits, using carry + set Carry to shifted bit
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rol reg1 - rotate reg1 left by 1 bits, not using carry + set Carry to shifted bit
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roxl reg1 - rotate reg1 left by 1 bits, using carry, + set Carry to shifted bit
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andm reg1 address - memory = memory bitwise and reg1
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orm reg1, address - memory = memory bitwise or reg1
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xorm reg1, address - memory = memory bitwise xor reg1
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invm address - memory = bitwise invert of that memory (all bits flipped)
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lsrnm reg1, address - multi-shift memoryright by reg1 bits + set Carry to shifted bit
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asrnm reg1, address - multi-shift memory right by reg1 bits (signed) + set Carry to shifted bit
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lslnm reg1, address - multi-shift memory left by reg1 bits + set Carry to shifted bit
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lsrm address - shift memory right by 1 bits + set Carry to shifted bit
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asrm address - shift memory right by 1 bits (signed) + set Carry to shifted bit
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lslm address - shift memory left by 1 bits + set Carry to shifted bit
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rorm address - rotate memory right by 1 bits, not using carry + set Carry to shifted bit
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roxrm address - rotate memory right by 1 bits, using carry + set Carry to shifted bit
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rolm address - rotate memory left by 1 bits, not using carry + set Carry to shifted bit
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@ -172,6 +172,15 @@ ftosw reg1, fpreg1 - reg1 = fpreg1 as signed word
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fpow fpreg1, fpreg2 - fpreg1 = fpreg1 to the power of fpreg2
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fabs fpreg1, fpreg2 - fpreg1 = abs(fpreg2)
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fcomp reg1, fpreg1, fpreg2 - reg1 = result of comparison of fpreg1 and fpreg2: 0=equal, 1=fpreg1 is greater, -1=fpreg1 is smaller
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fsin fpreg1, fpreg2 - fpreg1 = sin(fpreg2)
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fcos fpreg1, fpreg2 - fpreg1 = cos(fpreg2)
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ftan fpreg1, fpreg2 - fpreg1 = tan(fpreg2)
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fatan fpreg1, fpreg2 - fpreg1 = atan(fpreg2)
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fln fpreg1, fpreg2 - fpreg1 = ln(fpreg2) ; natural logarithm
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flog fpreg1, fpreg2 - fpreg1 = log(fpreg2) ; base 2 logarithm
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fround fpreg1, fpreg2 - fpreg1 = round(fpreg2)
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ffloor fpreg1, fpreg2 - fpreg1 = floor(fpreg2)
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fceil fpreg1, fpreg2 - fpreg1 = ceil(fpreg2)
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MISC
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@ -316,7 +325,6 @@ enum class Opcode {
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FATAN,
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FLN,
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FLOG,
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FSQRT,
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FROUND,
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FFLOOR,
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FCEIL,
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@ -382,6 +390,11 @@ data class Instruction(
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val fpValue: Float?=null,
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val labelSymbol: List<String>?=null // symbolic label name as alternative to value (so only for Branch/jump/call Instructions!)
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) {
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// reg1 and fpreg1 can be IN/OUT/INOUT (all others are readonly INPUT)
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// This knowledge is useful in IL assembly optimizers to see how registers are used.
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val reg1direction: OperandDirection
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val fpReg1direction: OperandDirection
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init {
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val formats = instructionFormats.getValue(opcode)
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if(type==null && !formats.containsKey(null))
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@ -410,6 +423,9 @@ data class Instruction(
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throw IllegalArgumentException("$opcode: integer point instruction can't use floating point registers")
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}
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reg1direction = format.reg1direction
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fpReg1direction = format.fpReg1direction
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if(opcode in setOf(Opcode.BEQ, Opcode.BNE, Opcode.BLT, Opcode.BLTS,
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Opcode.BGT, Opcode.BGTS, Opcode.BLE, Opcode.BLES,
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Opcode.BGE, Opcode.BGES,
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@ -464,184 +480,203 @@ data class Instruction(
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}
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}
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enum class OperandDirection {
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INPUT,
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OUTPUT,
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INOUT
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}
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data class InstructionFormat(val datatype: VmDataType?,
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val reg1: Boolean, val reg2: Boolean,
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val fpReg1: Boolean, val fpReg2: Boolean,
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val value: Boolean,
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val fpValue: Boolean) {
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val reg1: Boolean, val reg1direction: OperandDirection, // reg1 can be IN/OUT/INOUT
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val reg2: Boolean, // always only IN
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val fpReg1: Boolean, val fpReg1direction: OperandDirection, // fpreg1 can be IN/OUT/INOUT
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val fpReg2: Boolean, // always only IN
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val value: Boolean, // always only IN
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val fpValue: Boolean // always only IN
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) {
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companion object {
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fun from(spec: String): Map<VmDataType?, InstructionFormat> {
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val result = mutableMapOf<VmDataType?, InstructionFormat>()
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for(part in spec.split('|').map{ it.trim() }) {
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var reg1 = false
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var reg2 = false
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var fpreg1 = false
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var fpreg2 = false
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var value = false
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var fpvalue = false
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var reg1 = false // read/write/modify possible
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var reg1Direction = OperandDirection.INPUT
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var reg2 = false // strictly read-only
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var fpreg1 = false // read/write/modify possible
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var fpreg1Direction = OperandDirection.INPUT
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var fpreg2 = false // strictly read-only
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var value = false // strictly read-only
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var fpvalue = false // strictly read-only
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val splits = part.splitToSequence(',').iterator()
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val typespec = splits.next()
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while(splits.hasNext()) {
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when(splits.next()) {
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"r1" -> reg1=true
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"r2" -> reg2=true
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"fr1" -> fpreg1=true
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"fr2" -> fpreg2=true
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"v" -> value = true
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"fv" -> fpvalue = true
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"<r1" -> { reg1=true; reg1Direction=OperandDirection.INPUT }
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">r1" -> { reg1=true; reg1Direction=OperandDirection.OUTPUT }
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"<>r1" -> { reg1=true; reg1Direction=OperandDirection.INOUT }
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"<r2" -> reg2 = true
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"<fr1" -> { fpreg1=true; fpreg1Direction=OperandDirection.INPUT }
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">fr1" -> { fpreg1=true; fpreg1Direction=OperandDirection.OUTPUT }
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"<>fr1" -> { fpreg1=true; fpreg1Direction=OperandDirection.INOUT }
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"<fr2" -> fpreg2=true
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"<v" -> value = true
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"<fv" -> fpvalue = true
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else -> throw IllegalArgumentException(spec)
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}
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}
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if(typespec=="N")
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result[null] = InstructionFormat(null, reg1=reg1, reg2=reg2, fpReg1=fpreg1, fpReg2=fpreg2, value=value, fpValue=fpvalue)
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result[null] = InstructionFormat(null, reg1, reg1Direction, reg2, fpreg1, fpreg1Direction, fpreg2, value, fpvalue)
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if('B' in typespec)
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result[VmDataType.BYTE] = InstructionFormat(VmDataType.BYTE, reg1=reg1, reg2=reg2, fpReg1=fpreg1, fpReg2=fpreg2, value=value, fpValue=fpvalue)
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result[VmDataType.BYTE] = InstructionFormat(VmDataType.BYTE, reg1, reg1Direction, reg2, fpreg1, fpreg1Direction, fpreg2, value, fpvalue)
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if('W' in typespec)
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result[VmDataType.WORD] = InstructionFormat(VmDataType.WORD, reg1=reg1, reg2=reg2, fpReg1=fpreg1, fpReg2=fpreg2, value=value, fpValue=fpvalue)
|
||||
result[VmDataType.WORD] = InstructionFormat(VmDataType.WORD, reg1, reg1Direction, reg2, fpreg1, fpreg1Direction, fpreg2, value, fpvalue)
|
||||
if('F' in typespec)
|
||||
result[VmDataType.FLOAT] = InstructionFormat(VmDataType.FLOAT, reg1=reg1, reg2=reg2, fpReg1=fpreg1, fpReg2=fpreg2, value=value, fpValue=fpvalue)
|
||||
result[VmDataType.FLOAT] = InstructionFormat(VmDataType.FLOAT, reg1, reg1Direction, reg2, fpreg1, fpreg1Direction, fpreg2, value, fpvalue)
|
||||
}
|
||||
return result
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
<X = X is not modified (input/readonly value)
|
||||
>X = X is overwritten with output value (output value)
|
||||
<>X = X is modified (input + output)
|
||||
TODO: also encode if memory is read/written/modified?
|
||||
*/
|
||||
@Suppress("BooleanLiteralArgument")
|
||||
val instructionFormats = mutableMapOf(
|
||||
Opcode.NOP to InstructionFormat.from("N"),
|
||||
Opcode.LOAD to InstructionFormat.from("BW,r1,v | F,fr1,fv"),
|
||||
Opcode.LOADM to InstructionFormat.from("BW,r1,v | F,fr1,v"),
|
||||
Opcode.LOADI to InstructionFormat.from("BW,r1,r2 | F,fr1,r1"),
|
||||
Opcode.LOADX to InstructionFormat.from("BW,r1,r2,v | F,fr1,r1,v"),
|
||||
Opcode.LOADIX to InstructionFormat.from("BW,r1,r2,v | F,fr1,r1,v"),
|
||||
Opcode.LOADR to InstructionFormat.from("BW,r1,r2 | F,fr1,fr2"),
|
||||
Opcode.STOREM to InstructionFormat.from("BW,r1,v | F,fr1,v"),
|
||||
Opcode.STOREI to InstructionFormat.from("BW,r1,r2 | F,fr1,r1"),
|
||||
Opcode.STOREX to InstructionFormat.from("BW,r1,r2,v | F,fr1,r1,v"),
|
||||
Opcode.STOREIX to InstructionFormat.from("BW,r1,r2,v | F,fr1,r1,v"),
|
||||
Opcode.STOREZM to InstructionFormat.from("BW,v | F,v"),
|
||||
Opcode.STOREZI to InstructionFormat.from("BW,r1 | F,r1"),
|
||||
Opcode.STOREZX to InstructionFormat.from("BW,r1,v | F,r1,v"),
|
||||
Opcode.JUMP to InstructionFormat.from("N,v"),
|
||||
Opcode.CALL to InstructionFormat.from("N,v"),
|
||||
Opcode.SYSCALL to InstructionFormat.from("N,v"),
|
||||
Opcode.LOAD to InstructionFormat.from("BW,>r1,<v | F,>fr1,<fv"),
|
||||
Opcode.LOADM to InstructionFormat.from("BW,>r1,<v | F,>fr1,<v"),
|
||||
Opcode.LOADI to InstructionFormat.from("BW,>r1,<r2 | F,>fr1,<r1"),
|
||||
Opcode.LOADX to InstructionFormat.from("BW,>r1,<r2,<v | F,>fr1,<r1,<v"),
|
||||
Opcode.LOADIX to InstructionFormat.from("BW,>r1,<r2,<v | F,>fr1,<r1,<v"),
|
||||
Opcode.LOADR to InstructionFormat.from("BW,>r1,<r2 | F,>fr1,<fr2"),
|
||||
Opcode.STOREM to InstructionFormat.from("BW,<r1,<v | F,<fr1,<v"),
|
||||
Opcode.STOREI to InstructionFormat.from("BW,<r1,<r2 | F,<fr1,<r1"),
|
||||
Opcode.STOREX to InstructionFormat.from("BW,<r1,<r2,<v | F,<fr1,<r1,<v"),
|
||||
Opcode.STOREIX to InstructionFormat.from("BW,<r1,<r2,<v | F,<fr1,<r1,<v"),
|
||||
Opcode.STOREZM to InstructionFormat.from("BW,<v | F,<v"),
|
||||
Opcode.STOREZI to InstructionFormat.from("BW,<r1 | F,<r1"),
|
||||
Opcode.STOREZX to InstructionFormat.from("BW,<r1,<v | F,<r1,<v"),
|
||||
Opcode.JUMP to InstructionFormat.from("N,<v"),
|
||||
Opcode.CALL to InstructionFormat.from("N,<v"),
|
||||
Opcode.SYSCALL to InstructionFormat.from("N,<v"),
|
||||
Opcode.RETURN to InstructionFormat.from("N"),
|
||||
Opcode.BSTCC to InstructionFormat.from("N,v"),
|
||||
Opcode.BSTCS to InstructionFormat.from("N,v"),
|
||||
Opcode.BSTEQ to InstructionFormat.from("N,v"),
|
||||
Opcode.BSTNE to InstructionFormat.from("N,v"),
|
||||
Opcode.BSTNEG to InstructionFormat.from("N,v"),
|
||||
Opcode.BSTPOS to InstructionFormat.from("N,v"),
|
||||
Opcode.BZ to InstructionFormat.from("BW,r1,v"),
|
||||
Opcode.BNZ to InstructionFormat.from("BW,r1,v"),
|
||||
Opcode.BEQ to InstructionFormat.from("BW,r1,r2,v"),
|
||||
Opcode.BNE to InstructionFormat.from("BW,r1,r2,v"),
|
||||
Opcode.BLT to InstructionFormat.from("BW,r1,r2,v"),
|
||||
Opcode.BLTS to InstructionFormat.from("BW,r1,r2,v"),
|
||||
Opcode.BGT to InstructionFormat.from("BW,r1,r2,v"),
|
||||
Opcode.BGTS to InstructionFormat.from("BW,r1,r2,v"),
|
||||
Opcode.BLE to InstructionFormat.from("BW,r1,r2,v"),
|
||||
Opcode.BLES to InstructionFormat.from("BW,r1,r2,v"),
|
||||
Opcode.BGE to InstructionFormat.from("BW,r1,r2,v"),
|
||||
Opcode.BGES to InstructionFormat.from("BW,r1,r2,v"),
|
||||
Opcode.SEQ to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.SNE to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.SLT to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.SLTS to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.SGT to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.SGTS to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.SLE to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.SLES to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.SGE to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.SGES to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.INC to InstructionFormat.from("BW,r1"),
|
||||
Opcode.INCM to InstructionFormat.from("BW,v"),
|
||||
Opcode.DEC to InstructionFormat.from("BW,r1"),
|
||||
Opcode.DECM to InstructionFormat.from("BW,v"),
|
||||
Opcode.NEG to InstructionFormat.from("BW,r1 | F,fr1"),
|
||||
Opcode.NEGM to InstructionFormat.from("BW,v | F,v"),
|
||||
Opcode.ADDR to InstructionFormat.from("BW,r1,r2 | F,fr1,fr2"),
|
||||
Opcode.ADD to InstructionFormat.from("BW,r1,v | F,fr1,v"),
|
||||
Opcode.ADDM to InstructionFormat.from("BW,r1,v | F,fr1,v"),
|
||||
Opcode.SUBR to InstructionFormat.from("BW,r1,r2 | F,fr1,fr2"),
|
||||
Opcode.SUB to InstructionFormat.from("BW,r1,v | F,fr1,v"),
|
||||
Opcode.SUBM to InstructionFormat.from("BW,r1,v | F,fr1,v"),
|
||||
Opcode.MULR to InstructionFormat.from("BW,r1,r2 | F,fr1,fr2"),
|
||||
Opcode.MUL to InstructionFormat.from("BW,r1,v | F,fr1,v"),
|
||||
Opcode.MULM to InstructionFormat.from("BW,r1,v | F,fr1,v"),
|
||||
Opcode.DIVR to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.DIV to InstructionFormat.from("BW,r1,v"),
|
||||
Opcode.DIVM to InstructionFormat.from("BW,r1,v"),
|
||||
Opcode.DIVSR to InstructionFormat.from("BW,r1,r2 | F,fr1,fr2"),
|
||||
Opcode.DIVS to InstructionFormat.from("BW,r1,v | F,fr1,v"),
|
||||
Opcode.DIVSM to InstructionFormat.from("BW,r1,v | F,fr1,v"),
|
||||
Opcode.SQRT to InstructionFormat.from("BW,r1,r2 | F,fr1,fr2"),
|
||||
Opcode.SGN to InstructionFormat.from("BW,r1,r2 | F,fr1,fr2"),
|
||||
Opcode.RND to InstructionFormat.from("BW,r1 | F,fr1"),
|
||||
Opcode.MODR to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.MOD to InstructionFormat.from("BW,r1,v"),
|
||||
Opcode.CMP to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.EXT to InstructionFormat.from("BW,r1"),
|
||||
Opcode.EXTS to InstructionFormat.from("BW,r1"),
|
||||
Opcode.ANDR to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.AND to InstructionFormat.from("BW,r1,v"),
|
||||
Opcode.ANDM to InstructionFormat.from("BW,r1,v"),
|
||||
Opcode.ORR to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.OR to InstructionFormat.from("BW,r1,v"),
|
||||
Opcode.ORM to InstructionFormat.from("BW,r1,v"),
|
||||
Opcode.XORR to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.XOR to InstructionFormat.from("BW,r1,v"),
|
||||
Opcode.XORM to InstructionFormat.from("BW,r1,v"),
|
||||
Opcode.INV to InstructionFormat.from("BW,r1"),
|
||||
Opcode.INVM to InstructionFormat.from("BW,v"),
|
||||
Opcode.ASRN to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.ASRNM to InstructionFormat.from("BW,r1,v"),
|
||||
Opcode.LSRN to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.LSRNM to InstructionFormat.from("BW,r1,v"),
|
||||
Opcode.LSLN to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.LSLNM to InstructionFormat.from("BW,r1,v"),
|
||||
Opcode.ASR to InstructionFormat.from("BW,r1"),
|
||||
Opcode.ASRM to InstructionFormat.from("BW,v"),
|
||||
Opcode.LSR to InstructionFormat.from("BW,r1"),
|
||||
Opcode.LSRM to InstructionFormat.from("BW,v"),
|
||||
Opcode.LSL to InstructionFormat.from("BW,r1"),
|
||||
Opcode.LSLM to InstructionFormat.from("BW,v"),
|
||||
Opcode.ROR to InstructionFormat.from("BW,r1"),
|
||||
Opcode.RORM to InstructionFormat.from("BW,v"),
|
||||
Opcode.ROXR to InstructionFormat.from("BW,r1"),
|
||||
Opcode.ROXRM to InstructionFormat.from("BW,v"),
|
||||
Opcode.ROL to InstructionFormat.from("BW,r1"),
|
||||
Opcode.ROLM to InstructionFormat.from("BW,v"),
|
||||
Opcode.ROXL to InstructionFormat.from("BW,r1"),
|
||||
Opcode.ROXLM to InstructionFormat.from("BW,v"),
|
||||
Opcode.BSTCC to InstructionFormat.from("N,<v"),
|
||||
Opcode.BSTCS to InstructionFormat.from("N,<v"),
|
||||
Opcode.BSTEQ to InstructionFormat.from("N,<v"),
|
||||
Opcode.BSTNE to InstructionFormat.from("N,<v"),
|
||||
Opcode.BSTNEG to InstructionFormat.from("N,<v"),
|
||||
Opcode.BSTPOS to InstructionFormat.from("N,<v"),
|
||||
Opcode.BZ to InstructionFormat.from("BW,<r1,<v"),
|
||||
Opcode.BNZ to InstructionFormat.from("BW,<r1,<v"),
|
||||
Opcode.BEQ to InstructionFormat.from("BW,<r1,<r2,<v"),
|
||||
Opcode.BNE to InstructionFormat.from("BW,<r1,<r2,<v"),
|
||||
Opcode.BLT to InstructionFormat.from("BW,<r1,<r2,<v"),
|
||||
Opcode.BLTS to InstructionFormat.from("BW,<r1,<r2,<v"),
|
||||
Opcode.BGT to InstructionFormat.from("BW,<r1,<r2,<v"),
|
||||
Opcode.BGTS to InstructionFormat.from("BW,<r1,<r2,<v"),
|
||||
Opcode.BLE to InstructionFormat.from("BW,<r1,<r2,<v"),
|
||||
Opcode.BLES to InstructionFormat.from("BW,<r1,<r2,<v"),
|
||||
Opcode.BGE to InstructionFormat.from("BW,<r1,<r2,<v"),
|
||||
Opcode.BGES to InstructionFormat.from("BW,<r1,<r2,<v"),
|
||||
Opcode.SEQ to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.SNE to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.SLT to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.SLTS to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.SGT to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.SGTS to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.SLE to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.SLES to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.SGE to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.SGES to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.INC to InstructionFormat.from("BW,<>r1"),
|
||||
Opcode.INCM to InstructionFormat.from("BW,<v"),
|
||||
Opcode.DEC to InstructionFormat.from("BW,<>r1"),
|
||||
Opcode.DECM to InstructionFormat.from("BW,<v"),
|
||||
Opcode.NEG to InstructionFormat.from("BW,<>r1 | F,<>fr1"),
|
||||
Opcode.NEGM to InstructionFormat.from("BW,<v | F,<v"),
|
||||
Opcode.ADDR to InstructionFormat.from("BW,<>r1,<r2 | F,<>fr1,<fr2"),
|
||||
Opcode.ADD to InstructionFormat.from("BW,<>r1,<v | F,<>fr1,<v"),
|
||||
Opcode.ADDM to InstructionFormat.from("BW,<r1,<v | F,<fr1,<v"),
|
||||
Opcode.SUBR to InstructionFormat.from("BW,<>r1,<r2 | F,<>fr1,<fr2"),
|
||||
Opcode.SUB to InstructionFormat.from("BW,<>r1,<v | F,<>fr1,<v"),
|
||||
Opcode.SUBM to InstructionFormat.from("BW,<r1,<v | F,<fr1,<v"),
|
||||
Opcode.MULR to InstructionFormat.from("BW,<>r1,<r2 | F,<>fr1,<fr2"),
|
||||
Opcode.MUL to InstructionFormat.from("BW,<>r1,<v | F,<>fr1,<v"),
|
||||
Opcode.MULM to InstructionFormat.from("BW,<r1,<v | F,<fr1,<v"),
|
||||
Opcode.DIVR to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.DIV to InstructionFormat.from("BW,<>r1,<v"),
|
||||
Opcode.DIVM to InstructionFormat.from("BW,<r1,<v"),
|
||||
Opcode.DIVSR to InstructionFormat.from("BW,<>r1,<r2 | F,<>fr1,<fr2"),
|
||||
Opcode.DIVS to InstructionFormat.from("BW,<>r1,<v | F,<>fr1,<v"),
|
||||
Opcode.DIVSM to InstructionFormat.from("BW,<r1,<v | F,<fr1,<v"),
|
||||
Opcode.SQRT to InstructionFormat.from("BW,>r1,<r2 | F,>fr1,<fr2"),
|
||||
Opcode.SGN to InstructionFormat.from("BW,>r1,<r2 | F,>fr1,<fr2"),
|
||||
Opcode.RND to InstructionFormat.from("BW,>r1 | F,>fr1"),
|
||||
Opcode.MODR to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.MOD to InstructionFormat.from("BW,<>r1,<v"),
|
||||
Opcode.CMP to InstructionFormat.from("BW,<r1,<r2"),
|
||||
Opcode.EXT to InstructionFormat.from("BW,<>r1"),
|
||||
Opcode.EXTS to InstructionFormat.from("BW,<>r1"),
|
||||
Opcode.ANDR to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.AND to InstructionFormat.from("BW,<>r1,<v"),
|
||||
Opcode.ANDM to InstructionFormat.from("BW,<r1,<v"),
|
||||
Opcode.ORR to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.OR to InstructionFormat.from("BW,<>r1,<v"),
|
||||
Opcode.ORM to InstructionFormat.from("BW,<r1,<v"),
|
||||
Opcode.XORR to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.XOR to InstructionFormat.from("BW,<>r1,<v"),
|
||||
Opcode.XORM to InstructionFormat.from("BW,<r1,<v"),
|
||||
Opcode.INV to InstructionFormat.from("BW,<>r1"),
|
||||
Opcode.INVM to InstructionFormat.from("BW,<v"),
|
||||
Opcode.ASRN to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.ASRNM to InstructionFormat.from("BW,<r1,<v"),
|
||||
Opcode.LSRN to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.LSRNM to InstructionFormat.from("BW,<r1,<v"),
|
||||
Opcode.LSLN to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.LSLNM to InstructionFormat.from("BW,<r1,<v"),
|
||||
Opcode.ASR to InstructionFormat.from("BW,<>r1"),
|
||||
Opcode.ASRM to InstructionFormat.from("BW,<v"),
|
||||
Opcode.LSR to InstructionFormat.from("BW,<>r1"),
|
||||
Opcode.LSRM to InstructionFormat.from("BW,<v"),
|
||||
Opcode.LSL to InstructionFormat.from("BW,<>r1"),
|
||||
Opcode.LSLM to InstructionFormat.from("BW,<v"),
|
||||
Opcode.ROR to InstructionFormat.from("BW,<>r1"),
|
||||
Opcode.RORM to InstructionFormat.from("BW,<v"),
|
||||
Opcode.ROXR to InstructionFormat.from("BW,<>r1"),
|
||||
Opcode.ROXRM to InstructionFormat.from("BW,<v"),
|
||||
Opcode.ROL to InstructionFormat.from("BW,<>r1"),
|
||||
Opcode.ROLM to InstructionFormat.from("BW,<v"),
|
||||
Opcode.ROXL to InstructionFormat.from("BW,<>r1"),
|
||||
Opcode.ROXLM to InstructionFormat.from("BW,<v"),
|
||||
|
||||
Opcode.FFROMUB to InstructionFormat.from("F,fr1,r1"),
|
||||
Opcode.FFROMSB to InstructionFormat.from("F,fr1,r1"),
|
||||
Opcode.FFROMUW to InstructionFormat.from("F,fr1,r1"),
|
||||
Opcode.FFROMSW to InstructionFormat.from("F,fr1,r1"),
|
||||
Opcode.FTOUB to InstructionFormat.from("F,r1,fr1"),
|
||||
Opcode.FTOSB to InstructionFormat.from("F,r1,fr1"),
|
||||
Opcode.FTOUW to InstructionFormat.from("F,r1,fr1"),
|
||||
Opcode.FTOSW to InstructionFormat.from("F,r1,fr1"),
|
||||
Opcode.FPOW to InstructionFormat.from("F,fr1,fr2"),
|
||||
Opcode.FABS to InstructionFormat.from("F,fr1,fr2"),
|
||||
Opcode.FSIN to InstructionFormat.from("F,fr1,fr2"),
|
||||
Opcode.FCOS to InstructionFormat.from("F,fr1,fr2"),
|
||||
Opcode.FTAN to InstructionFormat.from("F,fr1,fr2"),
|
||||
Opcode.FATAN to InstructionFormat.from("F,fr1,fr2"),
|
||||
Opcode.FLN to InstructionFormat.from("F,fr1,fr2"),
|
||||
Opcode.FLOG to InstructionFormat.from("F,fr1,fr2"),
|
||||
Opcode.FSQRT to InstructionFormat.from("F,fr1,fr2"),
|
||||
Opcode.FROUND to InstructionFormat.from("F,fr1,fr2"),
|
||||
Opcode.FFLOOR to InstructionFormat.from("F,fr1,fr2"),
|
||||
Opcode.FCEIL to InstructionFormat.from("F,fr1,fr2"),
|
||||
Opcode.FCOMP to InstructionFormat.from("F,r1,fr1,fr2"),
|
||||
Opcode.FFROMUB to InstructionFormat.from("F,>fr1,<r1"),
|
||||
Opcode.FFROMSB to InstructionFormat.from("F,>fr1,<r1"),
|
||||
Opcode.FFROMUW to InstructionFormat.from("F,>fr1,<r1"),
|
||||
Opcode.FFROMSW to InstructionFormat.from("F,>fr1,<r1"),
|
||||
Opcode.FTOUB to InstructionFormat.from("F,>r1,<fr1"),
|
||||
Opcode.FTOSB to InstructionFormat.from("F,>r1,<fr1"),
|
||||
Opcode.FTOUW to InstructionFormat.from("F,>r1,<fr1"),
|
||||
Opcode.FTOSW to InstructionFormat.from("F,>r1,<fr1"),
|
||||
Opcode.FPOW to InstructionFormat.from("F,<>fr1,<fr2"),
|
||||
Opcode.FABS to InstructionFormat.from("F,>fr1,<fr2"),
|
||||
Opcode.FCOMP to InstructionFormat.from("F,>r1,<fr1,<fr2"),
|
||||
Opcode.FSIN to InstructionFormat.from("F,>fr1,<fr2"),
|
||||
Opcode.FCOS to InstructionFormat.from("F,>fr1,<fr2"),
|
||||
Opcode.FTAN to InstructionFormat.from("F,>fr1,<fr2"),
|
||||
Opcode.FATAN to InstructionFormat.from("F,>fr1,<fr2"),
|
||||
Opcode.FLN to InstructionFormat.from("F,>fr1,<fr2"),
|
||||
Opcode.FLOG to InstructionFormat.from("F,>fr1,<fr2"),
|
||||
Opcode.FROUND to InstructionFormat.from("F,>fr1,<fr2"),
|
||||
Opcode.FFLOOR to InstructionFormat.from("F,>fr1,<fr2"),
|
||||
Opcode.FCEIL to InstructionFormat.from("F,>fr1,<fr2"),
|
||||
|
||||
Opcode.MSIG to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.PUSH to InstructionFormat.from("BW,r1"),
|
||||
Opcode.POP to InstructionFormat.from("BW,r1"),
|
||||
Opcode.CONCAT to InstructionFormat.from("BW,r1,r2"),
|
||||
Opcode.MSIG to InstructionFormat.from("BW,>r1,<r2"),
|
||||
Opcode.PUSH to InstructionFormat.from("BW,<r1"),
|
||||
Opcode.POP to InstructionFormat.from("BW,>r1"),
|
||||
Opcode.CONCAT to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.CLC to InstructionFormat.from("N"),
|
||||
Opcode.SEC to InstructionFormat.from("N"),
|
||||
Opcode.BREAKPOINT to InstructionFormat.from("N"),
|
||||
|
|
|
|||
|
|
@ -218,7 +218,6 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
Opcode.FATAN -> InsFATAN(ins)
|
||||
Opcode.FLN -> InsFLN(ins)
|
||||
Opcode.FLOG -> InsFLOG(ins)
|
||||
Opcode.FSQRT -> InsFSQRT(ins)
|
||||
Opcode.FROUND -> InsFROUND(ins)
|
||||
Opcode.FFLOOR -> InsFFLOOR(ins)
|
||||
Opcode.FCEIL -> InsFCEIL(ins)
|
||||
|
|
@ -1887,12 +1886,6 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
pc++
|
||||
}
|
||||
|
||||
private fun InsFSQRT(i: Instruction) {
|
||||
val value = registers.getFloat(i.fpReg2!!)
|
||||
registers.setFloat(i.fpReg1!!, sqrt(value))
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsFCOMP(i: Instruction) {
|
||||
val left = registers.getFloat(i.fpReg1!!)
|
||||
val right = registers.getFloat(i.fpReg2!!)
|
||||
|
|
|
|||
|
|
@ -2,10 +2,7 @@ import io.kotest.assertions.throwables.shouldThrow
|
|||
import io.kotest.core.spec.style.FunSpec
|
||||
import io.kotest.matchers.shouldBe
|
||||
import io.kotest.matchers.shouldNotBe
|
||||
import prog8.vm.Instruction
|
||||
import prog8.vm.Opcode
|
||||
import prog8.vm.VmDataType
|
||||
import prog8.vm.instructionFormats
|
||||
import prog8.vm.*
|
||||
|
||||
|
||||
class TestInstructions: FunSpec({
|
||||
|
|
@ -18,6 +15,8 @@ class TestInstructions: FunSpec({
|
|||
ins.reg2 shouldBe null
|
||||
ins.value shouldBe null
|
||||
ins.labelSymbol shouldBe null
|
||||
ins.reg1direction shouldBe OperandDirection.INPUT
|
||||
ins.fpReg1direction shouldBe OperandDirection.INPUT
|
||||
ins.toString() shouldBe "nop"
|
||||
}
|
||||
|
||||
|
|
@ -29,6 +28,8 @@ class TestInstructions: FunSpec({
|
|||
ins.reg2 shouldBe null
|
||||
ins.value shouldBe 9999
|
||||
ins.labelSymbol shouldBe null
|
||||
ins.reg1direction shouldBe OperandDirection.INPUT
|
||||
ins.fpReg1direction shouldBe OperandDirection.INPUT
|
||||
ins.toString() shouldBe "bz.b r42,9999"
|
||||
}
|
||||
|
||||
|
|
@ -40,9 +41,36 @@ class TestInstructions: FunSpec({
|
|||
ins.reg2 shouldBe null
|
||||
ins.value shouldBe null
|
||||
ins.labelSymbol shouldBe listOf("a","b","c")
|
||||
ins.reg1direction shouldBe OperandDirection.INPUT
|
||||
ins.fpReg1direction shouldBe OperandDirection.INPUT
|
||||
ins.toString() shouldBe "bz.w r11,_a.b.c"
|
||||
}
|
||||
|
||||
test("with output registers") {
|
||||
val ins = Instruction(Opcode.ADDR, VmDataType.WORD, reg1=11, reg2=22)
|
||||
ins.opcode shouldBe Opcode.ADDR
|
||||
ins.type shouldBe VmDataType.WORD
|
||||
ins.reg1 shouldBe 11
|
||||
ins.reg2 shouldBe 22
|
||||
ins.value shouldBe null
|
||||
ins.labelSymbol shouldBe null
|
||||
ins.reg1direction shouldBe OperandDirection.INOUT
|
||||
ins.fpReg1direction shouldBe OperandDirection.INPUT
|
||||
ins.toString() shouldBe "addr.w r11,r22"
|
||||
|
||||
val ins2 = Instruction(Opcode.SQRT, VmDataType.BYTE, reg1=11, reg2=22)
|
||||
ins2.opcode shouldBe Opcode.SQRT
|
||||
ins2.type shouldBe VmDataType.BYTE
|
||||
ins2.reg1 shouldBe 11
|
||||
ins2.reg2 shouldBe 22
|
||||
ins2.value shouldBe null
|
||||
ins2.labelSymbol shouldBe null
|
||||
ins2.reg1direction shouldBe OperandDirection.OUTPUT
|
||||
ins2.fpReg1direction shouldBe OperandDirection.INPUT
|
||||
ins2.toString() shouldBe "sqrt.b r11,r22"
|
||||
}
|
||||
|
||||
|
||||
test("missing type should fail") {
|
||||
shouldThrow<IllegalArgumentException> {
|
||||
Instruction(Opcode.BZ, reg1=42, value=9999)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user