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fix builtins rejecting a cx16 virtual register as their result register
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Irmen de Jong committed
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@@ -20,6 +20,25 @@ import prog8.codegen.cpu6502.assignment.*
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translateFunctioncall(fcall, null, discardResult = true)
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}
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/**
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* Several builtins can only produce their result in a CPU register, and which one that is
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* depends on the width of the result: the byte-returning ones (lsb/msb) take a single register,
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* the word-returning ones (lsw/msw) and popw take a register pair, and the builtin picks the
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* specific register. [hardwareReg] is the register to fall back on when the caller has no
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* preference, or when it asked for something the builtin cannot deliver to directly.
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*
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* The caller's requested register is honoured when it is a real CPU register. A CX16 virtual
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* register (for example an asmsub parameter declared as @R0) is not: those are memory locations,
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* so the builtin produces its result in [hardwareReg] and the caller's assignment then stores it
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* into the virtual register. Passing the virtual register through would make the builtin reject
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* it as an invalid result register.
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*
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* (funcPeekW and funcMkword already handle virtual registers themselves.)
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*/
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private fun withResultRegister(requested: RegisterOrPair?, hardwareReg: RegisterOrPair, compute: (RegisterOrPair) -> Array<RegisterOrPair>): Array<RegisterOrPair> =
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if (requested != null && requested !in Cx16VirtualRegisters) compute(requested)
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else compute(hardwareReg)
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private fun translateFunctioncall(fcall: PtFunctionCall, firstReturnRegister: RegisterOrPair?, discardResult: Boolean): Array<RegisterOrPair> {
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// Note: returns the actual register(s) that the return value is in, so the caller should still make sure to place it into the actual correct destination.
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@@ -31,12 +50,12 @@ import prog8.codegen.cpu6502.assignment.*
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val sscope = fcall.definingISub()
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return when (fcall.name) {
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"msw" -> funcMsw(fcall, firstReturnRegister ?: RegisterOrPair.AY)
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"lsw" -> funcLsw(fcall, firstReturnRegister ?: RegisterOrPair.AY)
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"msb" -> funcMsb(fcall, false, firstReturnRegister ?: RegisterOrPair.A)
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"msb__long" -> funcMsb(fcall, true, firstReturnRegister ?: RegisterOrPair.A)
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"lsb" -> funcLsb(fcall, false, firstReturnRegister ?: RegisterOrPair.A)
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"lsb__long" -> funcLsb(fcall,true, firstReturnRegister ?: RegisterOrPair.A)
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"msw" -> withResultRegister(firstReturnRegister, RegisterOrPair.AY) { funcMsw(fcall, it) }
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"lsw" -> withResultRegister(firstReturnRegister, RegisterOrPair.AY) { funcLsw(fcall, it) }
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"msb" -> withResultRegister(firstReturnRegister, RegisterOrPair.A) { funcMsb(fcall, false, it) }
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"msb__long" -> withResultRegister(firstReturnRegister, RegisterOrPair.A) { funcMsb(fcall, true, it) }
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"lsb" -> withResultRegister(firstReturnRegister, RegisterOrPair.A) { funcLsb(fcall, false, it) }
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"lsb__long" -> withResultRegister(firstReturnRegister, RegisterOrPair.A) { funcLsb(fcall, true, it) }
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"mkword" -> funcMkword(fcall, firstReturnRegister ?: RegisterOrPair.AY)
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"mklong", "mklong2" -> funcMklong(fcall, firstReturnRegister ?: RegisterOrPair.R14R15)
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"clamp__byte", "clamp__ubyte" -> funcClamp(fcall)
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@@ -98,8 +117,8 @@ import prog8.codegen.cpu6502.assignment.*
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"pushw" -> funcPushW(fcall)
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"pushl" -> funcPushL(fcall)
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"pushf" -> funcPushF(fcall)
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"pop" -> funcPop(firstReturnRegister ?: RegisterOrPair.A)
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"popw" -> funcPopW(firstReturnRegister ?: RegisterOrPair.AY)
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"pop" -> withResultRegister(firstReturnRegister, RegisterOrPair.A) { funcPop(it) }
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"popw" -> withResultRegister(firstReturnRegister, RegisterOrPair.AY) { funcPopW(it) }
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"popl" -> funcPopL()
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"popf" -> funcPopF()
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else -> throw AssemblyError("sizeof must have been replaced with a constant ${fcall.position}")
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@@ -990,4 +990,69 @@ class TestExecution6502 : FunSpec({
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machine.assertMemory(0x04, 0x77)
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machine.assertMemory(0x05, 0x00)
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}
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test("lsb/msb/lsw/msw result delivered to a cx16 virtual register parameter") {
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val src = $$"""
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%option no_sysinit
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%launcher none
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%address $1000
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main {
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&ubyte poweroff = $f203
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; each routine copies the value it received in the @R0 virtual register to a probe address
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asmsub recordLsb(ubyte c @R0) {
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%asm {{
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lda cx16.r0L
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sta $3000
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rts
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}}
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}
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asmsub recordMsb(ubyte c @R0) {
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%asm {{
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lda cx16.r0L
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sta $3001
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rts
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}}
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}
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asmsub recordLsw(uword c @R0) {
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%asm {{
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lda cx16.r0
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sta $3002
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lda cx16.r0+1
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sta $3003
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rts
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}}
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}
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asmsub recordMsw(uword c @R0) {
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%asm {{
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lda cx16.r0
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sta $3004
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lda cx16.r0+1
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sta $3005
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rts
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}}
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}
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sub start() {
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uword @shared l
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l = $1234
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recordLsb(lsb(l))
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recordMsb(msb(l))
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recordLsw(lsw(l))
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recordMsw(msw(l))
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poweroff = 1
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}
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}
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""".trimIndent()
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val compileResult = compileText(Cx16Target(), false, src, outputDir)
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val machine = compileResult!!.simulate()
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machine.assertMemory(0x3000, 0x34) // lsb($1234)
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machine.assertMemory(0x3001, 0x12) // msb($1234)
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machine.assertMemory(0x3002, 0x34) // lsw($1234) low
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machine.assertMemory(0x3003, 0x12) // lsw($1234) high
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machine.assertMemory(0x3004, 0x00) // msw($1234) low
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machine.assertMemory(0x3005, 0x00) // msw($1234) high
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}
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})
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