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c128: better ZP definition
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@ -39,9 +39,9 @@ class AtariZeropage(options: CompilationOptions) : Zeropage(options) {
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}
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}
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val distictFree = free.distinct()
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val distinctFree = free.distinct()
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free.clear()
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free.addAll(distictFree)
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free.addAll(distinctFree)
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removeReservedFromFreePool()
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}
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@ -6,14 +6,15 @@ import prog8.code.core.Zeropage
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import prog8.code.core.ZeropageType
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// reference: "Mapping the C128" zero page chapter.
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class C128Zeropage(options: CompilationOptions) : Zeropage(options) {
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override val SCRATCH_B1 = 0x9bu // temp storage for a single byte
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override val SCRATCH_REG = 0x9cu // temp storage for a register, must be B1+1
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override val SCRATCH_B1 = 0x74u // temp storage for a single byte
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override val SCRATCH_REG = 0x75u // temp storage for a register, must be B1+1
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override val SCRATCH_W1 = 0xfbu // temp storage 1 for a word $fb+$fc
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override val SCRATCH_W2 = 0xfdu // temp storage 2 for a word $fd+$fe
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init {
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if (options.floats && options.zeropage !in arrayOf(
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ZeropageType.FLOATSAFE,
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@ -24,23 +25,42 @@ class C128Zeropage(options: CompilationOptions) : Zeropage(options) {
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when (options.zeropage) {
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ZeropageType.FULL -> {
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// TODO all c128 usable zero page locations, except the ones used by the system's IRQ routine
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free.addAll(0x0au..0xffu) // TODO c128 what about $02-$09?
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// TODO c128 free.removeAll(setOf(0xa0u, 0xa1u, 0xa2u, 0x91u, 0xc0u, 0xc5u, 0xcbu, 0xf5u, 0xf6u)) // these are updated by IRQ
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// $00/$01 are data port IO registers, // $02-$09 are storage locations for JSRFAR and such
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free.addAll(0x0au..0xffu)
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free.removeAll(listOf(0x90u, 0x91u, 0xa0u, 0xa1u, 0xa2u, 0xc0u, 0xccu, 0xcdu, 0xd0u, 0xd1u, 0xd2u, 0xd3u, 0xd4u, 0xd5u, 0xf7u)) // these are updated/used by IRQ
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}
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ZeropageType.KERNALSAFE -> {
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free.addAll(0x0au..0x8fu) // BASIC variables
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free.addAll(listOf(0x92u, 0x96u, 0x9bu, 0x9cu, 0x9eu, 0x9fu, 0xa4u, 0xa7u, 0xa8u, 0xa9u, 0xaau, 0xabu,
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0xb0u, 0xb1u, 0xb4u, 0xb5u, 0xb6u))
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}
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ZeropageType.KERNALSAFE,
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ZeropageType.FLOATSAFE,
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ZeropageType.BASICSAFE -> {
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free.clear() // TODO c128 usable zero page addresses
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free.addAll(listOf(0x0bu, 0x0cu, 0x0du, 0x0eu, 0x0fu, 0x10u, 0x11u, 0x12u, 0x16u, 0x17u, 0x18u, 0x19u, 0x1au))
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free.addAll(0x1bu..0x23u)
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free.addAll(listOf(0x3fu, 0x40u, 0x41u, 0x42u, 0x43u, 0x44u, 0x47u, 0x48u, 0x49u, 0x4au, 0x4bu, 0x4cu, 0x4fu,
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0x55u, 0x56u, 0x57u, 0x58u,
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0x74u, 0x75u, 0x78u, 0x80u, 0x83u, 0x87u, 0x88u, 0x89u, 0x8au, 0x8bu, 0x8cu, 0x8du, 0x8eu, 0x8fu,
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0x92u, 0x96u, 0x9bu, 0x9cu, 0x9eu, 0x9fu, 0xa4u, 0xa7u, 0xa8u, 0xa9u, 0xaau, 0xabu,
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0xb0u, 0xb1u, 0xb4u, 0xb5u, 0xb6u
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))
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if(options.zeropage==ZeropageType.BASICSAFE) {
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// can also clobber the FP locations
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free.addAll(listOf(0x14u, 0x28u, 0x29u, 0x2au, 0x2bu, 0x2cu,
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0x50u, 0x51u, 0x52u, 0x53u, 0x54u, 0x59u, 0x5au, 0x5bu, 0x5cu, 0x5du, 0x5eu, 0x5fu, 0x60u, 0x61u, 0x62u,
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0x63u, 0x64u, 0x65u, 0x66u, 0x67u, 0x68u,
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0x6au, 0x6bu, 0x6cu, 0x6du, 0x6eu, 0x6fu, 0x71u))
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}
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}
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ZeropageType.DONTUSE -> {
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free.clear() // don't use zeropage at all
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}
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}
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val distictFree = free.distinct()
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val distinctFree = free.distinct()
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free.clear()
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free.addAll(distictFree)
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free.addAll(distinctFree)
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removeReservedFromFreePool()
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}
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@ -65,9 +65,9 @@ class C64Zeropage(options: CompilationOptions) : Zeropage(options) {
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}
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}
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val distictFree = free.distinct()
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val distinctFree = free.distinct()
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free.clear()
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free.addAll(distictFree)
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free.addAll(distinctFree)
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removeReservedFromFreePool()
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@ -43,9 +43,9 @@ class CX16Zeropage(options: CompilationOptions) : Zeropage(options) {
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else -> throw InternalCompilerException("for this machine target, zero page type 'floatsafe' is not available. ${options.zeropage}")
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}
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val distictFree = free.distinct()
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val distinctFree = free.distinct()
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free.clear()
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free.addAll(distictFree)
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free.addAll(distinctFree)
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removeReservedFromFreePool()
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