mirror of
https://github.com/irmen/prog8.git
synced 2024-06-25 15:29:45 +00:00
removed redundant branch opcodes in IR: BLT(S), BLE(S). Just use swapped BGT(S), BGE(S).
This commit is contained in:
Irmen de Jong
parent
7ee777f405
commit
eb4cff202c
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@ -551,8 +551,9 @@ class IRCodeGen(
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result += labelFirstChunk(translateNode(forLoop.statements), loopLabel)
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result += addConstMem(loopvarDtIr, null, loopvarSymbol, step)
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addInstr(result, IRInstruction(Opcode.LOADM, loopvarDtIr, reg1 = indexReg, labelSymbol = loopvarSymbol), null)
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val branchOpcode = if(loopvarDt in SignedDatatypes) Opcode.BLES else Opcode.BLE
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addInstr(result, IRInstruction(branchOpcode, loopvarDtIr, reg1=indexReg, reg2=endvalueReg, labelSymbol=loopLabel), null)
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// if endvalue >= index, iterate loop
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val branchOpcode = if(loopvarDt in SignedDatatypes) Opcode.BGES else Opcode.BGE
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addInstr(result, IRInstruction(branchOpcode, loopvarDtIr, reg1=endvalueReg, reg2=indexReg, labelSymbol=loopLabel), null)
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result += IRCodeChunk(labelAfterFor, null)
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return result
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@ -907,56 +908,117 @@ class IRCodeGen(
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if(ifElse.condition.operator !in ComparisonOperators)
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throw AssemblyError("if condition should only be a binary comparison expression")
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val signed = ifElse.condition.left.type in arrayOf(DataType.BYTE, DataType.WORD, DataType.FLOAT)
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val signed = ifElse.condition.left.type in SignedDatatypes
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val irDt = irType(ifElse.condition.left.type)
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val goto = ifElse.ifScope.children.firstOrNull() as? PtJump
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if(goto!=null && ifElse.elseScope.children.isEmpty()) {
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// special case the form: if <condition> goto <place>
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val result = mutableListOf<IRCodeChunkBase>()
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val leftReg = registers.nextFree()
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val rightReg = registers.nextFree()
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result += expressionEval.translateExpression(ifElse.condition.left, leftReg, -1)
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result += expressionEval.translateExpression(ifElse.condition.right, rightReg, -1)
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val opcode = when(ifElse.condition.operator) {
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"==" -> Opcode.BEQ
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"!=" -> Opcode.BNE
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"<" -> Opcode.BLT
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">" -> Opcode.BGT
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"<=" -> Opcode.BLE
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">=" -> Opcode.BGE
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val leftRegNum = registers.nextFree()
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val rightRegNum = registers.nextFree()
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result += expressionEval.translateExpression(ifElse.condition.left, leftRegNum, -1)
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result += expressionEval.translateExpression(ifElse.condition.right, rightRegNum, -1)
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val opcode: Opcode
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val firstReg: Int
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val secondReg: Int
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when(ifElse.condition.operator) {
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"==" -> {
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opcode = Opcode.BEQ
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firstReg = leftRegNum
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secondReg = rightRegNum
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}
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"!=" -> {
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opcode = Opcode.BNE
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firstReg = leftRegNum
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secondReg = rightRegNum
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}
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"<" -> {
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// swapped '>'
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opcode = if(signed) Opcode.BGTS else Opcode.BGT
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firstReg = rightRegNum
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secondReg = leftRegNum
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}
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">" -> {
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opcode = if(signed) Opcode.BGTS else Opcode.BGT
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firstReg = leftRegNum
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secondReg = rightRegNum
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}
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"<=" -> {
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// swapped '>='
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opcode = if(signed) Opcode.BGES else Opcode.BGE
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firstReg = rightRegNum
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secondReg = leftRegNum
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}
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">=" -> {
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opcode = if(signed) Opcode.BGES else Opcode.BGE
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firstReg = leftRegNum
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secondReg = rightRegNum
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}
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else -> throw AssemblyError("invalid comparison operator")
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}
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if(goto.address!=null)
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addInstr(result, IRInstruction(opcode, irDt, reg1=leftReg, reg2=rightReg, value = goto.address?.toInt()), null)
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addInstr(result, IRInstruction(opcode, irDt, reg1=firstReg, reg2=secondReg, value = goto.address?.toInt()), null)
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else if(goto.generatedLabel!=null)
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addInstr(result, IRInstruction(opcode, irDt, reg1=leftReg, reg2=rightReg, labelSymbol = goto.generatedLabel), null)
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addInstr(result, IRInstruction(opcode, irDt, reg1=firstReg, reg2=secondReg, labelSymbol = goto.generatedLabel), null)
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else
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addInstr(result, IRInstruction(opcode, irDt, reg1=leftReg, reg2=rightReg, labelSymbol = goto.identifier!!.targetName.joinToString(".")), null)
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addInstr(result, IRInstruction(opcode, irDt, reg1=firstReg, reg2=secondReg, labelSymbol = goto.identifier!!.targetName.joinToString(".")), null)
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return result
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}
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fun translateNonZeroComparison(): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val elseBranch = when(ifElse.condition.operator) {
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"==" -> Opcode.BNE
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"!=" -> Opcode.BEQ
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"<" -> if(signed) Opcode.BGES else Opcode.BGE
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">" -> if(signed) Opcode.BLES else Opcode.BLE
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"<=" -> if(signed) Opcode.BGTS else Opcode.BGT
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">=" -> if(signed) Opcode.BLTS else Opcode.BLT
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val leftRegNum = registers.nextFree()
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val rightRegNum = registers.nextFree()
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result += expressionEval.translateExpression(ifElse.condition.left, leftRegNum, -1)
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result += expressionEval.translateExpression(ifElse.condition.right, rightRegNum, -1)
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val elseBranchOpcode: Opcode
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val elseBranchFirstReg: Int
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val elseBranchSecondReg: Int
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when(ifElse.condition.operator) {
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"==" -> {
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elseBranchOpcode = Opcode.BNE
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elseBranchFirstReg = leftRegNum
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elseBranchSecondReg = rightRegNum
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}
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"!=" -> {
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elseBranchOpcode = Opcode.BEQ
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elseBranchFirstReg = leftRegNum
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elseBranchSecondReg = rightRegNum
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}
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"<" -> {
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// else part when left >= right
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elseBranchOpcode = if(signed) Opcode.BGES else Opcode.BGE
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elseBranchFirstReg = leftRegNum
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elseBranchSecondReg = rightRegNum
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}
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">" -> {
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// else part when left <= right --> right >= left
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elseBranchOpcode = if(signed) Opcode.BGES else Opcode.BGE
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elseBranchFirstReg = rightRegNum
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elseBranchSecondReg = leftRegNum
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}
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"<=" -> {
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// else part when left > right
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elseBranchOpcode = if(signed) Opcode.BGTS else Opcode.BGT
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elseBranchFirstReg = leftRegNum
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elseBranchSecondReg = rightRegNum
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}
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">=" -> {
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// else part when left < right --> right > left
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elseBranchOpcode = if(signed) Opcode.BGTS else Opcode.BGT
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elseBranchFirstReg = rightRegNum
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elseBranchSecondReg = leftRegNum
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}
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else -> throw AssemblyError("invalid comparison operator")
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}
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val leftReg = registers.nextFree()
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val rightReg = registers.nextFree()
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result += expressionEval.translateExpression(ifElse.condition.left, leftReg, -1)
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result += expressionEval.translateExpression(ifElse.condition.right, rightReg, -1)
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if(ifElse.elseScope.children.isNotEmpty()) {
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// if and else parts
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val elseLabel = createLabelName()
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val afterIfLabel = createLabelName()
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addInstr(result, IRInstruction(elseBranch, irDt, reg1=leftReg, reg2=rightReg, labelSymbol = elseLabel), null)
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addInstr(result, IRInstruction(elseBranchOpcode, irDt, reg1=elseBranchFirstReg, reg2=elseBranchSecondReg, labelSymbol = elseLabel), null)
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result += translateNode(ifElse.ifScope)
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addInstr(result, IRInstruction(Opcode.JUMP, labelSymbol = afterIfLabel), null)
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result += labelFirstChunk(translateNode(ifElse.elseScope), elseLabel)
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@ -964,7 +1026,7 @@ class IRCodeGen(
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} else {
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// only if part
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val afterIfLabel = createLabelName()
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addInstr(result, IRInstruction(elseBranch, irDt, reg1=leftReg, reg2=rightReg, labelSymbol = afterIfLabel), null)
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addInstr(result, IRInstruction(elseBranchOpcode, irDt, reg1=elseBranchFirstReg, reg2=elseBranchSecondReg, labelSymbol = afterIfLabel), null)
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result += translateNode(ifElse.ifScope)
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result += IRCodeChunk(afterIfLabel, null)
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}
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@ -1006,6 +1068,7 @@ class IRCodeGen(
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}
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else -> {
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// another comparison against 0, just use regular codegen for this.
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// TODO optimize this
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translateNonZeroComparison()
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}
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}
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@ -3,7 +3,7 @@ TODO
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For next release
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^^^^^^^^^^^^^^^^
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- remove redundant branch opcodes in IR: BLT(S), BLE(S). Replace by swapped BGT(S), BGE(S).
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- try to optimize IR for branching on signed <0, >0, <=0, >=0 by using new branch instructions like we have BNZ. To avoid explicit compares. See translateZeroComparison()
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- make sure bool value is always 0 or 1 (all casts should convert), then:
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- rewrite bool=bool^1 into bool=not bool
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- should solve: bool bb = not bb -> larger code than bool bb ^= 1
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@ -76,20 +76,17 @@ bz reg1, address - branch to location if reg1 is zero
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bnz reg1, address - branch to location if reg1 is not zero
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beq reg1, reg2, address - jump to location in program given by location, if reg1 == reg2
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bne reg1, reg2, address - jump to location in program given by location, if reg1 != reg2
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blt reg1, reg2, address - jump to location in program given by location, if reg1 < reg2 (unsigned) TODO REMOVE
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blts reg1, reg2, address - jump to location in program given by location, if reg1 < reg2 (signed) TODO REMOVE
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ble reg1, reg2, address - jump to location in program given by location, if reg1 <= reg2 (unsigned) TODO REMOVE
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bles reg1, reg2, address - jump to location in program given by location, if reg1 <= reg2 (signed) TODO REMOVE
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bgt reg1, reg2, address - jump to location in program given by location, if reg1 > reg2 (unsigned)
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bgts reg1, reg2, address - jump to location in program given by location, if reg1 > reg2 (signed)
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bge reg1, reg2, address - jump to location in program given by location, if reg1 >= reg2 (unsigned)
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bges reg1, reg2, address - jump to location in program given by location, if reg1 >= reg2 (signed)
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( NOTE: there are no blt/ble instructions because these are equivalent to bgt/bge with the operands swapped around.)
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seq reg1, reg2 - set reg=1 if reg1 == reg2, otherwise set reg1=0
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sne reg1, reg2 - set reg=1 if reg1 != reg2, otherwise set reg1=0
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slt reg1, reg2 - set reg=1 if reg1 < reg2 (unsigned), otherwise set reg1=0 TODO REMOVE
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slts reg1, reg2 - set reg=1 if reg1 < reg2 (signed), otherwise set reg1=0 TODO REMOVE
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sle reg1, reg2 - set reg=1 if reg1 <= reg2 (unsigned), otherwise set reg1=0 TODO REMOVE
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sles reg1, reg2 - set reg=1 if reg1 <= reg2 (signed), otherwise set reg1=0 TODO REMOVE
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slt reg1, reg2 - set reg=1 if reg1 < reg2 (unsigned), otherwise set reg1=0
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slts reg1, reg2 - set reg=1 if reg1 < reg2 (signed), otherwise set reg1=0
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sle reg1, reg2 - set reg=1 if reg1 <= reg2 (unsigned), otherwise set reg1=0
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sles reg1, reg2 - set reg=1 if reg1 <= reg2 (signed), otherwise set reg1=0
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sgt reg1, reg2 - set reg=1 if reg1 > reg2 (unsigned), otherwise set reg1=0
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sgts reg1, reg2 - set reg=1 if reg1 > reg2 (signed), otherwise set reg1=0
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sge reg1, reg2 - set reg=1 if reg1 >= reg2 (unsigned), otherwise set reg1=0
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@ -244,22 +241,18 @@ enum class Opcode {
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BNZ,
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BEQ,
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BNE,
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BLT, // TODO REMOVE
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BLTS, // TODO REMOVE
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BGT,
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BGTS,
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BLE, // TODO REMOVE
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BLES, // TODO REMOVE
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BGE,
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BGES,
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SEQ,
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SNE,
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SLT, // TODO REMOVE ?
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SLTS, // TODO REMOVE ?
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SLT,
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SLTS,
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SGT,
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SGTS,
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SLE, // TODO REMOVE ?
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SLES, // TODO REMOVE ?
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SLE,
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SLES,
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SGE,
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SGES,
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@ -379,12 +372,8 @@ val OpcodesThatBranch = setOf(
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Opcode.BNZ,
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Opcode.BEQ,
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Opcode.BNE,
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Opcode.BLT,
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Opcode.BLTS,
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Opcode.BGT,
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Opcode.BGTS,
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Opcode.BLE,
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Opcode.BLES,
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Opcode.BGE,
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Opcode.BGES
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)
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@ -419,12 +408,8 @@ val OpcodesWithMemoryAddressAsValue = setOf(
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Opcode.BNZ,
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Opcode.BEQ,
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Opcode.BNE,
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Opcode.BLT,
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Opcode.BLTS,
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Opcode.BGT,
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Opcode.BGTS,
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Opcode.BLE,
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Opcode.BLES,
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Opcode.BGE,
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Opcode.BGES,
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Opcode.INCM,
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@ -560,12 +545,8 @@ val instructionFormats = mutableMapOf(
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Opcode.BNZ to InstructionFormat.from("BW,<r1,<v"),
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Opcode.BEQ to InstructionFormat.from("BW,<r1,<r2,<v"),
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Opcode.BNE to InstructionFormat.from("BW,<r1,<r2,<v"),
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Opcode.BLT to InstructionFormat.from("BW,<r1,<r2,<v"),
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Opcode.BLTS to InstructionFormat.from("BW,<r1,<r2,<v"),
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Opcode.BGT to InstructionFormat.from("BW,<r1,<r2,<v"),
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Opcode.BGTS to InstructionFormat.from("BW,<r1,<r2,<v"),
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Opcode.BLE to InstructionFormat.from("BW,<r1,<r2,<v"),
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Opcode.BLES to InstructionFormat.from("BW,<r1,<r2,<v"),
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Opcode.BGE to InstructionFormat.from("BW,<r1,<r2,<v"),
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Opcode.BGES to InstructionFormat.from("BW,<r1,<r2,<v"),
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Opcode.SEQ to InstructionFormat.from("BW,<>r1,<r2"),
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@ -734,8 +715,8 @@ data class IRInstruction(
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fpReg1direction = format.fpReg1
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fpReg2direction = format.fpReg2
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if(opcode in setOf(Opcode.BEQ, Opcode.BNE, Opcode.BLT, Opcode.BLTS,
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Opcode.BGT, Opcode.BGTS, Opcode.BLE, Opcode.BLES,
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if(opcode in setOf(Opcode.BEQ, Opcode.BNE,
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Opcode.BGT, Opcode.BGTS,
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Opcode.BGE, Opcode.BGES,
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Opcode.SEQ, Opcode.SNE, Opcode.SLT, Opcode.SLTS,
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Opcode.SGT, Opcode.SGTS, Opcode.SLE, Opcode.SLES,
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@ -178,12 +178,8 @@ class VirtualMachine(irProgram: IRProgram) {
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Opcode.BNZ -> InsBNZ(ins)
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Opcode.BEQ -> InsBEQ(ins)
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Opcode.BNE -> InsBNE(ins)
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Opcode.BLT -> InsBLTU(ins)
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Opcode.BLTS -> InsBLTS(ins)
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Opcode.BGT -> InsBGTU(ins)
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Opcode.BGTS -> InsBGTS(ins)
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Opcode.BLE -> InsBLEU(ins)
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Opcode.BLES -> InsBLES(ins)
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Opcode.BGE -> InsBGEU(ins)
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Opcode.BGES -> InsBGES(ins)
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Opcode.SEQ -> InsSEQ(ins)
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@ -676,22 +672,6 @@ class VirtualMachine(irProgram: IRProgram) {
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nextPc()
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}
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private fun InsBLTU(i: IRInstruction) {
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val (left: UInt, right: UInt) = getBranchOperandsU(i)
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if(left<right)
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branchTo(i)
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else
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nextPc()
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}
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private fun InsBLTS(i: IRInstruction) {
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val (left: Int, right: Int) = getBranchOperands(i)
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if(left<right)
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branchTo(i)
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else
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nextPc()
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}
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private fun InsBGTU(i: IRInstruction) {
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val (left: UInt, right: UInt) = getBranchOperandsU(i)
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if(left>right)
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@ -709,23 +689,6 @@ class VirtualMachine(irProgram: IRProgram) {
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nextPc()
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}
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private fun InsBLEU(i: IRInstruction) {
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val (left: UInt, right: UInt) = getBranchOperandsU(i)
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if(left<=right)
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branchTo(i)
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else
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nextPc()
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}
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private fun InsBLES(i: IRInstruction) {
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val (left: Int, right: Int) = getBranchOperands(i)
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if(left<=right)
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branchTo(i)
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else
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nextPc()
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}
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private fun InsBGEU(i: IRInstruction) {
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val (left: UInt, right: UInt) = getBranchOperandsU(i)
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if(left>=right)
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