diff --git a/codeGenM68k/src/prog8/codegen/m68k/InstrArithmetic.kt b/codeGenM68k/src/prog8/codegen/m68k/InstrArithmetic.kt index 6c5fb2fa3..1eb3ad9a5 100644 --- a/codeGenM68k/src/prog8/codegen/m68k/InstrArithmetic.kt +++ b/codeGenM68k/src/prog8/codegen/m68k/InstrArithmetic.kt @@ -50,8 +50,8 @@ internal fun AsmGen.translateArithmetic(insn: IRInstruction) { Opcode.ADDR -> { val dstReg = r1 ?: error("ADDR needs reg1") val srcReg = r2 ?: error("ADDR needs reg2") - emitLine("move${memSuffix(type)} ${regAddr(srcReg)}, d0") - emitLine("add${memSuffix(type)} d0, ${regAddr(dstReg)}") + emitLine("move${dtSuffix(type)} ${regAddr(srcReg)}, d0") + emitLine("add${dtSuffix(type)} d0, ${regAddr(dstReg)}") } Opcode.ADD -> { diff --git a/codeGenM68k/src/prog8/codegen/m68k/InstrControl.kt b/codeGenM68k/src/prog8/codegen/m68k/InstrControl.kt index dd932ab7e..813e9582a 100644 --- a/codeGenM68k/src/prog8/codegen/m68k/InstrControl.kt +++ b/codeGenM68k/src/prog8/codegen/m68k/InstrControl.kt @@ -259,16 +259,14 @@ internal fun AsmGen.translateControl(insn: IRInstruction) { // r1 = WORD(r2 as MSB, r3 as LSB) emitLine("move.b ${regAddr(srcReg2)}, d0") emitLine("lsl.w #8, d0") - emitLine("move.b ${regAddr(srcReg3)}, d1") - emitLine("or.w d1, d0") + emitLine("or.b ${regAddr(srcReg3)}, d0") emitLine("move.w d0, ${regAddr(dstReg)}") } IRDataType.WORD -> { // r1 = LONG(r2 as MSW, r3 as LSW) emitLine("move.w ${regAddr(srcReg2)}, d0") emitLine("lsl.l #16, d0") - emitLine("move.w ${regAddr(srcReg3)}, d1") - emitLine("or.l d1, d0") + emitLine("or.w ${regAddr(srcReg3)}, d0") emitLine("move.l d0, ${regAddr(dstReg)}") } else -> TODO("CONCAT for ${type.name}")