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474 lines
23 KiB
Kotlin
474 lines
23 KiB
Kotlin
package prog8tests.codegen.m68k
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import io.kotest.core.spec.style.FunSpec
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import io.kotest.engine.spec.tempdir
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import io.kotest.matchers.shouldBe
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import prog8.code.core.*
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import prog8.code.target.Qemu68kTarget
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import prog8.codegen.m68k.AsmGen
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import prog8.intermediate.*
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import prog8tests.helpers.DummyStringEncoder
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import prog8tests.helpers.ErrorReporterForTests
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import kotlin.io.path.exists
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import kotlin.io.path.readText
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// Vertical Slice Prototype: m68k backend lowering of FrameSlot memory references
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// and the link/unlk frame prologue/epilogue.
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class TestStackFrameEmission : FunSpec({
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val tempRoot = tempdir().toPath()
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fun generateAsmWithIncoming(
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frameSize: Int,
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instructions: List<IRInstruction>,
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incomingSize: Int = 0,
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subLabel: String = "test.start",
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frameVregSlots: Map<Int, Int> = emptyMap(),
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errors: ErrorReporterForTests? = null,
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params: List<IRSubroutine.IRParam>? = null
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): List<String> {
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val options = CompilationOptions.builder(Qemu68kTarget())
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.output(OutputType.RAW)
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.zeropage(ZeropageType.DONTUSE)
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.floats(false)
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.compilerVersion("test")
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.memtopAddress(0xffffu)
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.optimize(true)
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.build()
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val program = IRProgram("test", IRSymbolTable(), options, DummyStringEncoder)
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program.options.outputDir = tempRoot
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val chunk = IRCodeChunk(subLabel, null)
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chunk.instructions.addAll(instructions)
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// word-packed slots: give callers a way to declare each parameter's real type,
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// since the default derivation from the incoming area size assumes uniform slots
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val paramList = params
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?: if (incomingSize > 0)
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List(incomingSize / 2) { IRSubroutine.IRParam("p8v_p$it", DataType.UBYTE) }
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else emptyList()
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val sub = IRSubroutine(subLabel, paramList, emptyList(), Position.DUMMY, frameSize, incomingSize, frameVregSlots)
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sub.chunks.add(chunk)
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val block = IRBlock("test", false, IRBlock.Options(), Position.DUMMY)
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block.children.add(sub)
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program.blocks.add(block)
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tempRoot.toFile().deleteRecursively()
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tempRoot.toFile().mkdirs()
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AsmGen(program, Qemu68kTarget(), errors).generate()
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val asmFile = tempRoot.resolve("test.asm")
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check(asmFile.exists()) { "Assembly file not written: $asmFile" }
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return asmFile.readText().lines().map { it.trim() }
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}
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fun generateAsm(frameSize: Int, instructions: List<IRInstruction>): List<String> =
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generateAsmWithIncoming(frameSize, instructions, 0, "test.start")
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// builds a subroutine with a chunk per extra chunk label, for jump-target scope tests
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fun sub(label: String, frameSize: Int, instructions: List<IRInstruction>, extraChunks: List<IRCodeChunkBase> = emptyList()): IRSubroutine {
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val first = IRCodeChunk(label, null)
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first.instructions.addAll(instructions)
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val sub = IRSubroutine(label, emptyList(), emptyList(), Position.DUMMY, frameSize, 0, emptyMap())
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sub.chunks.add(first)
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sub.chunks.addAll(extraChunks)
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return sub
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}
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fun generateAsmForSubs(vararg subs: IRSubroutine): List<String> {
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val options = CompilationOptions.builder(Qemu68kTarget())
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.output(OutputType.RAW)
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.zeropage(ZeropageType.DONTUSE)
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.floats(false)
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.compilerVersion("test")
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.memtopAddress(0xffffu)
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.optimize(true)
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.build()
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val program = IRProgram("test", IRSymbolTable(), options, DummyStringEncoder)
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program.options.outputDir = tempRoot
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val block = IRBlock("test", false, IRBlock.Options(), Position.DUMMY)
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block.children.addAll(subs)
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program.blocks.add(block)
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program.linkChunks()
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tempRoot.toFile().deleteRecursively()
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tempRoot.toFile().mkdirs()
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AsmGen(program, Qemu68kTarget(), null).generate()
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return tempRoot.resolve("test.asm").readText().lines().map { it.trim() }
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}
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test("frameless subroutine emits no frame setup") {
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val lines = generateAsm(0, listOf(
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IRInstructions.loadMemory(Opcode.LOADM, IRDataType.BYTE, 1, IRMemory.direct("some.var")),
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IRInstructions.simple(Opcode.RETURN)
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))
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lines.any { it.startsWith("link") } shouldBe false
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lines.any { it.startsWith("unlk") } shouldBe false
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}
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test("framed subroutine emits link prologue and unlk epilogue") {
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val lines = generateAsm(16, listOf(
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IRInstructions.storeZero(Opcode.STOREZM, IRDataType.BYTE, IRMemory.frameDirect(-1)),
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IRInstructions.simple(Opcode.RETURN)
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))
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lines.any { it == "link a5,#-16" } shouldBe true
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lines.count { it == "unlk a5" } shouldBe 1
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lines.any { "-1(a5)" in it } shouldBe true
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// epilogue must directly precede the subroutine's return
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lines[lines.indexOf("unlk a5") + 1] shouldBe "rts"
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}
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test("frame slot direct references lower to displacements relative to a5") {
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val lines = generateAsm(16, listOf(
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IRInstructions.storeImmediate(IRDataType.WORD, 5, IRMemory.frameDirect(-4)),
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IRInstructions.loadMemory(Opcode.LOADM, IRDataType.BYTE, 1, IRMemory.frameDirect(-1)),
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IRInstructions.memoryOpImmediate(Opcode.ADDIM, IRDataType.BYTE, IRMemory.frameDirect(-1), 3),
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IRInstructions.simple(Opcode.RETURN)
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))
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lines.any { it.contains("-4(a5)") && it.startsWith("move.w") } shouldBe true
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lines.any { it.contains("-1(a5)") } shouldBe true
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lines.any { it.startsWith("addq.b") || it.startsWith("add.b") } shouldBe true
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}
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test("indexed frame slot access uses lea of the slot base plus index") {
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val lines = generateAsm(16, listOf(
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IRInstructions.loadMemory(Opcode.LOADX, IRDataType.BYTE, 1, IRMemory.frameIndexed(-8, 3, IRDataType.WORD, scale = 1)),
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IRInstructions.storeZero(Opcode.STOREZX, IRDataType.BYTE, IRMemory.frameIndexed(-8, 3, IRDataType.WORD, scale = 1)),
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IRInstructions.simple(Opcode.RETURN)
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))
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lines.any { it.startsWith("lea") && "-8(a5)" in it } shouldBe true
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lines.count { it.contains("(a0,d0.w)") } shouldBe 2
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}
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test("frame displacement combines slot offset and reference displacement") {
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val lines = generateAsm(16, listOf(
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IRInstructions.storeZero(Opcode.STOREZM, IRDataType.BYTE, IRMemory.frameDirect(-8, 4)),
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IRInstructions.simple(Opcode.RETURN)
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))
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// -8 slot + 4 displacement = -4(a5), a single combined displacement
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lines.any { it.contains("-4(a5)") } shouldBe true
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lines.any { it.contains("-8(a5)+4") } shouldBe false
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}
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test("incoming-only frame still emits link and unlk") {
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val lines = generateAsmWithIncoming(0, listOf(IRInstructions.simple(Opcode.RETURN)), incomingSize = 12)
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lines.any { it == "link a5,#0" } shouldBe true
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lines.any { it == "unlk a5" } shouldBe true
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}
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test("stack arguments are pushed word-aligned into their slots and popped by the caller") {
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val calls = listOf(
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IRInstructions.call(CallSite(
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target = CallTarget.Direct(CodeReference.Label("test.sub")),
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arguments = listOf(
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Calls.argument(1, IRDataType.BYTE, CallLocation.FrameSlot(16)),
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Calls.argument(2, IRDataType.WORD, CallLocation.FrameSlot(12)),
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Calls.argument(3, IRDataType.LONG, CallLocation.FrameSlot(8))
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)
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)),
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IRInstructions.simple(Opcode.RETURN)
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)
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val lines = generateAsmWithIncoming(0, calls, incomingSize = 12, subLabel = "test.caller")
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// word-packed pushes: byte arguments use the single move.b predecrement instruction
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// (the byte lands at the slot's base byte), word and long push as themselves
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lines.count { it.startsWith("move.b ") && it.contains(",-(sp)") && it.contains("pushed as a word") } shouldBe 1
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lines.count { it.startsWith("move.w ") && it.contains(",-(sp)") } shouldBe 1
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lines.count { it.startsWith("move.l ") && it.contains(",-(sp)") } shouldBe 1
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lines.none { it == "subq.l #2,sp" } shouldBe true
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lines.any { it.startsWith("bsr") } shouldBe true
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lines.any { it == "addq.l #8,sp" } shouldBe true // 2+2+4 bytes
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// small argument areas use the short addq form
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val smallCalls = listOf(
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IRInstructions.call(CallSite(
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target = CallTarget.Direct(CodeReference.Label("test.sub")),
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arguments = listOf(Calls.argument(1, IRDataType.BYTE, CallLocation.FrameSlot(8)))
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)),
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IRInstructions.simple(Opcode.RETURN)
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)
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val smallLines = generateAsmWithIncoming(0, smallCalls, incomingSize = 4, subLabel = "test.caller")
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smallLines.any { it == "addq.l #2,sp" } shouldBe true
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}
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test("status-flag results use CCR-preserving cleanup") {
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val calls = listOf(
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IRInstructions.call(CallSite(
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target = CallTarget.Direct(CodeReference.Label("test.sub")),
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arguments = listOf(Calls.argument(1, IRDataType.BYTE, CallLocation.FrameSlot(8))),
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results = listOf(CallResult(null, CallLocation.StatusFlag(Statusflag.Pz)))
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)),
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IRInstructions.simple(Opcode.RETURN)
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)
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val lines = generateAsmWithIncoming(0, calls, incomingSize = 4, subLabel = "test.caller")
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// a single byte argument (2-byte slot) would normally use addq.l #2,sp, but that
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// clobbers CCR, so status-flag returns must use lea instead.
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lines.any { it == "lea 2(sp),sp" } shouldBe true
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lines.none { it == "addq.l #2,sp" } shouldBe true
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}
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test("float stack arguments travel through the FPU accumulator") {
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val calls = listOf(
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IRInstructions.call(CallSite(
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target = CallTarget.Direct(CodeReference.Label("test.sub")),
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arguments = listOf(Calls.argument(1, IRDataType.FLOAT, CallLocation.FrameSlot(8)))
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)),
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IRInstructions.simple(Opcode.RETURN)
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)
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val lines = generateAsmWithIncoming(0, calls, incomingSize = 4, subLabel = "test.caller")
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// the 68881 has no absolute-long addressing mode: the value must pass through fp0,
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// and the store itself reserves the slot via predecrement
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lines.any { it.startsWith("fmove.s p8_fregfile+0,fp0") } shouldBe true
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lines.any { it == "fmove.s fp0,-(sp)" } shouldBe true
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lines.none { it == "subq.l #4,sp" } shouldBe true
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}
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test("per-activation virtual registers are addressed through the frame") {
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// a re-entrant subroutine keeps its virtual registers in its own frame (slice 3), so they
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// are addressed relative to a5 instead of the flat program-static register file
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val lines = generateAsmWithIncoming(8, listOf(
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IRInstructions.loadMemory(Opcode.LOADM, IRDataType.WORD, 5, IRMemory.direct("main.var")),
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IRInstructions.returnRegister(IRDataType.WORD, 5)
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), frameVregSlots = mapOf(5 to -2, 6 to -4))
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lines.any { it.startsWith("link ") } shouldBe true
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lines.any { it.startsWith("move") && it.contains("-2(a5)") } shouldBe true
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lines.none { it.startsWith("move") && it.contains("p8_regfile") } shouldBe true
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}
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test("virtual registers without a frame slot keep using the static register file") {
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val lines = generateAsmWithIncoming(8, listOf(
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IRInstructions.loadMemory(Opcode.LOADM, IRDataType.WORD, 5, IRMemory.direct("main.var")),
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IRInstructions.returnRegister(IRDataType.WORD, 5)
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), frameVregSlots = mapOf(6 to -4))
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// register 5 has no frame slot, so it stays in the static register file
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lines.any { it.startsWith("move") && it.contains("p8_regfile") } shouldBe true
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lines.any { it.startsWith("move") && it.contains("(a5)") && it.contains("p8_regfile") } shouldBe false
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}
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test("a byte-sized frame-resident register is addressed with its byte offset") {
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val lines = generateAsmWithIncoming(4, listOf(
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IRInstructions.loadMemory(Opcode.LOADM, IRDataType.BYTE, 5, IRMemory.direct("main.var")),
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IRInstructions.returnRegister(IRDataType.BYTE, 5)
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), frameVregSlots = mapOf(5 to -4))
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lines.any { it.startsWith("move.b") && it.contains("-4(a5)") } shouldBe true
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}
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test("sub-byte extraction of a frame-resident register uses a valid a5 displacement") {
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// MSIGB on a long goes through regAddrByte, which must not emit "$(-4)(a5)"
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val lines = generateAsmWithIncoming(4, listOf(
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IRInstructions.binary(Opcode.MSIGB, IRDataType.LONG, 6, 5),
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IRInstructions.returnRegister(IRDataType.BYTE, 6)
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), frameVregSlots = mapOf(5 to -4))
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lines.any { it.startsWith("move.b") && it.contains("-4(a5)") } shouldBe true
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lines.none { it.contains("\$(-4)(a5)") } shouldBe true
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}
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test("framed subroutine emits a stack frame listing comment") {
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val lines = generateAsmWithIncoming(24, listOf(
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IRInstructions.storeZero(Opcode.STOREZM, IRDataType.BYTE, IRMemory.frameDirect(-1)),
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IRInstructions.simple(Opcode.RETURN)
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), incomingSize = 8)
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lines.any { it == "; stack frame: 24 bytes of locals, 8 bytes of arguments" } shouldBe true
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}
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test("incoming-only frame emits a stack frame listing comment with zero locals") {
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val lines = generateAsmWithIncoming(0, listOf(IRInstructions.simple(Opcode.RETURN)), incomingSize = 8)
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lines.any { it == "; stack frame: 0 bytes of locals, 8 bytes of arguments" } shouldBe true
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}
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test("frameless subroutine emits no stack frame listing comment") {
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val lines = generateAsm(0, listOf(
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IRInstructions.loadMemory(Opcode.LOADM, IRDataType.BYTE, 1, IRMemory.direct("some.var")),
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IRInstructions.simple(Opcode.RETURN)
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))
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lines.none { it.startsWith("; stack frame:") } shouldBe true
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}
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test("subroutine boundary markers are emitted exactly once per subroutine") {
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val lines = generateAsm(16, listOf(
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IRInstructions.storeZero(Opcode.STOREZM, IRDataType.BYTE, IRMemory.frameDirect(-1)),
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IRInstructions.simple(Opcode.RETURN)
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))
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lines.count { it == "; ---- Subroutine: test.start ----" } shouldBe 1
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lines.count { it == "; End of subroutine: test.start" } shouldBe 1
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}
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test("large frames report an informational message") {
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val errors = ErrorReporterForTests()
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generateAsmWithIncoming(900, listOf(
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IRInstructions.storeZero(Opcode.STOREZM, IRDataType.BYTE, IRMemory.frameDirect(-1)),
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IRInstructions.simple(Opcode.RETURN)
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), subLabel = "p8b_main.p8s_worker", errors = errors)
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errors.infos.any { it.contains("subroutine 'main.worker' uses a 900 byte stack frame; deep recursion multiplies this per call") } shouldBe true
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}
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test("small frames produce no informational message") {
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val errors = ErrorReporterForTests()
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generateAsmWithIncoming(24, listOf(
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IRInstructions.storeZero(Opcode.STOREZM, IRDataType.BYTE, IRMemory.frameDirect(-1)),
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IRInstructions.simple(Opcode.RETURN)
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), incomingSize = 8, errors = errors)
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errors.infos shouldBe emptyList()
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}
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test("a long run of longword zero-clears lowers to a dbra loop") {
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val stores = (0 until 17).map { i ->
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IRInstructions.storeZero(Opcode.STOREZM, IRDataType.LONG, IRMemory.frameDirect(-68 + i * 4))
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}
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val lines = generateAsm(68, stores + IRInstructions.simple(Opcode.RETURN))
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lines.any { it == "moveq #0,d0" } shouldBe true
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lines.any { it == "lea -68(a5),a0" } shouldBe true
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lines.any { it == "moveq #16,d1" } shouldBe true
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lines.any { it == "move.l d0,(a0)+" } shouldBe true
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lines.count { it.startsWith("dbra d1,zeroloop_") } shouldBe 1
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lines.none { it.startsWith("clr.l") } shouldBe true
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}
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test("a short run of longword zero-clears keeps straight stores") {
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val stores = (0 until 15).map { i ->
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IRInstructions.storeZero(Opcode.STOREZM, IRDataType.LONG, IRMemory.frameDirect(-60 + i * 4))
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}
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val lines = generateAsm(60, stores + IRInstructions.simple(Opcode.RETURN))
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lines.count { it.startsWith("clr.l") } shouldBe 15
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lines.none { it.startsWith("dbra") } shouldBe true
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}
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test("an interleaved store splits the zero-clear run") {
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val first = (0 until 8).map { i ->
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IRInstructions.storeZero(Opcode.STOREZM, IRDataType.LONG, IRMemory.frameDirect(-68 + i * 4))
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}
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val second = (0 until 8).map { i ->
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IRInstructions.storeZero(Opcode.STOREZM, IRDataType.LONG, IRMemory.frameDirect(-32 + i * 4))
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}
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val instructions = first +
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IRInstructions.storeImmediate(IRDataType.BYTE, 0, IRMemory.frameDirect(-36)) +
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second +
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IRInstructions.simple(Opcode.RETURN)
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val lines = generateAsm(68, instructions)
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// two runs of 8 stay below the loop threshold
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lines.none { it.startsWith("dbra") } shouldBe true
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lines.count { it.startsWith("clr.l") } shouldBe 16
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lines.any { it == "clr.b -36(a5)" } shouldBe true
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}
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test("dispatch jump in a framed subroutine pops the frame before jumping") {
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// an on..goto leaves the subroutine for good, so the target's rts must find our caller's
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// return address: leaving our frame behind would make it pop garbage
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val lines = generateAsm(16, listOf(
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IRInstructions.jumpIndirect(5),
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IRInstructions.simple(Opcode.RETURN)
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))
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val unlkIdx = lines.indexOf("unlk a5")
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unlkIdx shouldBe lines.indexOfFirst { it.startsWith("jmp") } - 1
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}
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test("dispatch jump in a frameless subroutine emits no frame teardown") {
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val lines = generateAsm(0, listOf(
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IRInstructions.jumpIndirect(5),
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IRInstructions.simple(Opcode.RETURN)
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))
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lines.none { it.startsWith("unlk") } shouldBe true
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}
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test("jump to an absolute address pops the frame before jumping") {
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// a fixed address can't be resolved to a chunk of this subroutine, so it must be assumed
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// to leave for good and the frame must be gone before the target's eventual rts
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val lines = generateAsm(16, listOf(
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IRInstructions.jump(codeAddress(0x1234u)),
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IRInstructions.simple(Opcode.RETURN)
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))
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val jmpIdx = lines.indexOfFirst { it.startsWith("jmp") }
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(jmpIdx > 0) shouldBe true
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lines[jmpIdx - 1] shouldBe "unlk a5"
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}
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test("jump to an absolute address in a frameless subroutine emits no frame teardown") {
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val lines = generateAsm(0, listOf(
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IRInstructions.jump(codeAddress(0x1234u)),
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IRInstructions.simple(Opcode.RETURN)
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))
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lines.none { it.startsWith("unlk") } shouldBe true
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}
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test("conditional branch to an absolute address tears down only the taken path") {
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val lines = generateAsm(16, listOf(
|
|
IRInstructions.branch(Opcode.BSTEQ, codeAddress(0x1234u)),
|
|
IRInstructions.simple(Opcode.RETURN)
|
|
))
|
|
val branchIdx = lines.indexOfFirst { it.startsWith("bne") }
|
|
val jmpIdx = lines.indexOfFirst { it.startsWith("jmp") && "$1234" in it }
|
|
(branchIdx >= 0) shouldBe true
|
|
(jmpIdx > branchIdx) shouldBe true
|
|
lines[jmpIdx - 1] shouldBe "unlk a5"
|
|
lines.count { it == "unlk a5" } shouldBe 2
|
|
}
|
|
|
|
test("conditional branch to an external non-entry label tears down only the taken path") {
|
|
val outsideInner = IRCodeChunk("test.outside.inner", null).also {
|
|
it.instructions.add(IRInstructions.simple(Opcode.RETURN))
|
|
}
|
|
val lines = generateAsmForSubs(
|
|
sub("test.start", frameSize = 16, instructions = listOf(
|
|
IRInstructions.branch(Opcode.BSTEQ, CodeReference.Label("test.outside.inner")),
|
|
IRInstructions.simple(Opcode.RETURN)
|
|
)),
|
|
sub("test.outside", frameSize = 0, instructions = listOf(IRInstructions.simple(Opcode.RETURN)),
|
|
extraChunks = listOf(outsideInner))
|
|
)
|
|
val jmpIdx = lines.indexOfFirst { it.startsWith("jmp") && "outside.inner" in it }
|
|
(jmpIdx > 0) shouldBe true
|
|
lines[jmpIdx - 1] shouldBe "unlk a5"
|
|
lines.any { it.startsWith("bne") } shouldBe true
|
|
}
|
|
|
|
test("signed comparison branch to an absolute address tears down only the taken path") {
|
|
val lines = generateAsm(16, listOf(
|
|
IRInstructions.branchImmediate(Opcode.BGTS, IRDataType.WORD, 1, 1, codeAddress(0x1234u)),
|
|
IRInstructions.simple(Opcode.RETURN)
|
|
))
|
|
lines.any { it.startsWith("cmpi.w") } shouldBe true
|
|
val branchIdx = lines.indexOfFirst { it.startsWith("ble") }
|
|
val jmpIdx = lines.indexOfFirst { it.startsWith("jmp") && "$1234" in it }
|
|
(branchIdx >= 0) shouldBe true
|
|
(jmpIdx > branchIdx) shouldBe true
|
|
lines[jmpIdx - 1] shouldBe "unlk a5"
|
|
lines.count { it == "unlk a5" } shouldBe 2
|
|
}
|
|
|
|
test("jump to a label in another subroutine pops the frame before jumping") {
|
|
// jumping out of the subroutine is a documented way to end it, so our frame must not be
|
|
// left behind for whatever runs next (and its eventual rts) to trip over
|
|
val lines = generateAsmForSubs(
|
|
sub("test.start", frameSize = 16, instructions = listOf(
|
|
IRInstructions.jump(CodeReference.Label("test.outside")),
|
|
IRInstructions.simple(Opcode.RETURN)
|
|
)),
|
|
sub("test.outside", frameSize = 0, instructions = listOf(IRInstructions.simple(Opcode.RETURN)))
|
|
)
|
|
val braIdx = lines.indexOfFirst { it.startsWith("bra") && "test.outside" in it }
|
|
(braIdx > 0) shouldBe true
|
|
lines[braIdx - 1] shouldBe "unlk a5"
|
|
}
|
|
|
|
test("jump to a label in a chunk of the same subroutine keeps the frame") {
|
|
val lines = generateAsmForSubs(
|
|
sub("test.start", frameSize = 16, instructions = listOf(
|
|
IRInstructions.jump(CodeReference.Label("test.start.second")),
|
|
IRInstructions.simple(Opcode.RETURN)
|
|
), extraChunks = listOf(
|
|
IRCodeChunk("test.start.second", null).also {
|
|
it.instructions.add(IRInstructions.storeImmediate(IRDataType.BYTE, 0, IRMemory.direct("test.var")))
|
|
}
|
|
))
|
|
)
|
|
lines.count { it == "unlk a5" } shouldBe 1 // only the return epilogue
|
|
lines[lines.indexOf("unlk a5") + 1] shouldBe "rts"
|
|
lines.any { it.startsWith("bra") && "test.start.second" in it } shouldBe true
|
|
}
|
|
|
|
test("jump to a label inside a loop body of the same subroutine keeps the frame") {
|
|
val loopBodyChunk = IRCodeChunk("test.start.loopbody", null)
|
|
loopBodyChunk.instructions.add(IRInstructions.jump(CodeReference.Label("test.start.loopbody")))
|
|
val lines = generateAsmForSubs(
|
|
sub("test.start", frameSize = 16, instructions = listOf(
|
|
IRInstructions.simple(Opcode.RETURN)
|
|
), extraChunks = listOf(IRLoopChunk("test.start.loop", 3, mutableListOf(loopBodyChunk))))
|
|
)
|
|
lines.count { it == "unlk a5" } shouldBe 1 // the jump to the loop body label must not tear the frame down
|
|
}
|
|
|
|
})
|