mirror of
https://github.com/irmen/prog8.git
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489 lines
13 KiB
Kotlin
489 lines
13 KiB
Kotlin
package prog8tests.vm
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import io.kotest.assertions.throwables.shouldThrow
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import io.kotest.core.spec.style.FunSpec
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import io.kotest.matchers.shouldBe
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import io.kotest.matchers.shouldNotBe
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import io.kotest.matchers.string.shouldContain
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import io.kotest.matchers.string.shouldNotContain
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import prog8.ast.expressions.BuiltinFunctionCall
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import prog8.ast.statements.Assignment
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import prog8.code.target.C64Target
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import prog8.code.target.Cx16Target
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import prog8.code.target.VMTarget
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import prog8.intermediate.IRDataType
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import prog8.intermediate.IRFileReader
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import prog8.intermediate.IRSubroutine
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import prog8.intermediate.Opcode
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import prog8.vm.VmRunner
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import prog8tests.helpers.compileText
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import kotlin.io.path.readText
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class TestCompilerVirtual: FunSpec({
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test("compile virtual: array with pointers") {
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val src = """
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main {
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sub start() {
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str localstr = "hello"
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ubyte[] otherarray = [1,2,3]
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uword[] words = [1111,2222,"three",&localstr,&otherarray]
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uword @shared zz = &words
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bool result = 2222 in words
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zz = words[2]
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zz++
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zz = words[3]
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}
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}"""
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val target = VMTarget()
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val result = compileText(target, true, src, writeAssembly = true)!!
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val virtfile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".p8ir")
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VmRunner().runProgram(virtfile.readText())
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}
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test("compile virtual: str args and return type, and global var init") {
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val src = """
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main {
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ubyte @shared dvar = test.dummy()
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sub start() {
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sub testsub(str s1) -> str {
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return "result"
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}
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uword result = testsub("arg")
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}
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}
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test {
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sub dummy() -> ubyte {
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cx16.r0++
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return 80
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}
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}"""
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val target = VMTarget()
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var result = compileText(target, false, src, writeAssembly = true)!!
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var virtfile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".p8ir")
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VmRunner().runProgram(virtfile.readText())
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result = compileText(target, true, src, writeAssembly = true)!!
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virtfile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".p8ir")
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VmRunner().runProgram(virtfile.readText())
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}
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test("compile virtual: nested labels") {
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val src = """
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main {
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sub start() {
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uword i
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uword k
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repeat {
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mylabel0:
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goto mylabel0
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}
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while cx16.r0==0 {
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mylabel1:
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goto mylabel1
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}
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do {
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mylabel2:
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goto mylabel2
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} until cx16.r0==1
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repeat cx16.r0 {
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mylabel3:
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goto mylabel3
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}
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for cx16.r0L in 0 to 2 {
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mylabel4:
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goto mylabel4
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}
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for cx16.r0L in cx16.r1L to cx16.r2L {
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mylabel5:
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goto mylabel5
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}
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mylabel_outside:
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for i in 0 to 10 {
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mylabel_inside:
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if i==100 {
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goto mylabel_outside
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goto mylabel_inside
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}
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while k <= 10 {
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k++
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}
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do {
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k--
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} until k==0
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for k in 0 to 5 {
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i++
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}
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repeat 10 {
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k++
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}
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}
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}
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}"""
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val target1 = C64Target()
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compileText(target1, false, src, writeAssembly = false) shouldNotBe null
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val target = VMTarget()
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compileText(target, false, src, writeAssembly = true) shouldNotBe null
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}
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test("case sensitive symbols") {
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val src = """
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main {
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sub start() {
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ubyte @shared bytevar = 11 ; var at 0
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ubyte @shared byteVAR = 22 ; var at 1
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ubyte @shared ByteVar = 33 ; var at 2
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ubyte @shared total = bytevar+byteVAR+ByteVar ; var at 3
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goto skipLABEL
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SkipLabel:
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return
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skipLABEL:
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bytevar = 42
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}
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}"""
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val result = compileText(VMTarget(), true, src, writeAssembly = true)!!
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val virtfile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".p8ir")
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VmRunner().runAndTestProgram(virtfile.readText()) { vm ->
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vm.memory.getUB(0) shouldBe 42u
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vm.memory.getUB(3) shouldBe 66u
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}
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}
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test("memory slabs") {
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val src = """
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main {
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sub start() {
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uword slab1 = memory("slab1", 2000, 64)
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slab1[10]=42
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slab1[11]=43
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ubyte @shared value1 = slab1[10] ; var at 2
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ubyte @shared value2 = slab1[11] ; var at 3
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}
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}"""
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val target = VMTarget()
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val result = compileText(target, true, src, writeAssembly = true)!!
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val start = result.compilerAst.entrypoint
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start.statements.size shouldBe 9
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((start.statements[1] as Assignment).value as BuiltinFunctionCall).name shouldBe "memory"
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val virtfile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".p8ir")
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VmRunner().runAndTestProgram(virtfile.readText()) { vm ->
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vm.memory.getUB(2) shouldBe 42u
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vm.memory.getUB(3) shouldBe 43u
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}
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}
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test("memory mapped var as for loop counter") {
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val src = """
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main {
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sub start() {
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for cx16.r0 in 0 to 10 {
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cx16.r1++
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}
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}
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}"""
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val othertarget = Cx16Target()
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compileText(othertarget, true, src, writeAssembly = true) shouldNotBe null
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val target = VMTarget()
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var result = compileText(target, true, src, writeAssembly = true)!!
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var virtfile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".p8ir")
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VmRunner().runAndTestProgram(virtfile.readText()) { vm ->
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vm.stepCount shouldBe 59
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}
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result = compileText(target, false, src, writeAssembly = true)!!
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virtfile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".p8ir")
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VmRunner().runAndTestProgram(virtfile.readText()) { vm ->
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vm.stepCount shouldBe 59
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}
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}
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test("inline asm for virtual target should be IR") {
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val src = """
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main {
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sub start() {
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%asm {{
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lda #99
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tay
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rts
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}}
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}
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}"""
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val othertarget = Cx16Target()
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compileText(othertarget, true, src, writeAssembly = true) shouldNotBe null
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val target = VMTarget()
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val result = compileText(target, false, src, writeAssembly = true)!!
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val virtfile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".p8ir")
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val exc = shouldThrow<Exception> {
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VmRunner().runProgram(virtfile.readText())
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}
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exc.message shouldContain("encountered unconverted inline assembly chunk")
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}
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test("inline asm for virtual target with IR is accepted and converted to regular instructions") {
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val src = """
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main {
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sub start() {
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%ir {{
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incm.b $2000
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return
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}}
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}
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}"""
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val target = VMTarget()
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val result = compileText(target, false, src, writeAssembly = true)!!
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val virtfile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".p8ir")
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val irSrc = virtfile.readText()
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irSrc.shouldContain("incm.b $2000")
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irSrc.shouldNotContain("</ASM>")
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VmRunner().runProgram(irSrc)
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}
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test("addresses from labels/subroutines not yet supported in VM") {
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val src = """
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main {
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sub start() {
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mylabel:
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ubyte variable
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uword @shared pointer1 = &main.start
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uword @shared pointer2 = &start
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uword @shared pointer3 = &main.start.mylabel
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uword @shared pointer4 = &mylabel
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uword[] @shared ptrs = [&variable, &start, &main.start, &mylabel, &main.start.mylabel]
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}
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}
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"""
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val result = compileText(VMTarget(), false, src, writeAssembly = true)!!
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val virtfile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".p8ir")
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val exc = shouldThrow<Exception> {
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VmRunner().runProgram(virtfile.readText())
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}
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exc.message shouldContain("cannot yet load a label address as a value")
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}
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test("nesting with overlapping names is ok (doesn't work for 64tass)") {
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val src="""
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main {
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sub start() {
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main()
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main.start.start()
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main.main()
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sub main() {
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cx16.r0++
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}
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sub start() {
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cx16.r0++
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}
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}
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sub main() {
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cx16.r0++
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}
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}"""
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val target = VMTarget()
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compileText(target, false, src, writeAssembly = true) shouldNotBe null
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}
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test("compile virtual: short code for if-goto") {
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val src = """
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main {
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sub start() {
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if_cc
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goto ending
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if_cs
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goto ending
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if cx16.r0==0 goto ending
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if cx16.r0!=0 goto ending
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if cx16.r0s>0 goto ending
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if cx16.r0s<0 goto ending
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ending:
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}
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}"""
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val result = compileText(VMTarget(), true, src, writeAssembly = true)!!
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result.compilerAst.entrypoint.statements.size shouldBe 8
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val virtfile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".p8ir")
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val irProgram = IRFileReader().read(virtfile)
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val start = irProgram.blocks[0].children[0] as IRSubroutine
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val instructions = start.chunks.flatMap { c->c.instructions }
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instructions.size shouldBe 11
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instructions.last().opcode shouldBe Opcode.RETURN
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}
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test("repeat counts (const)") {
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val src="""
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main {
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sub start() {
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cx16.r0 = 0
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repeat 255 {
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cx16.r0++
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}
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repeat 256 {
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cx16.r0++
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}
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repeat 257 {
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cx16.r0++
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}
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repeat 1023 {
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cx16.r0++
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}
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repeat 1024 {
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cx16.r0++
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}
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repeat 1025 {
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cx16.r0++
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}
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repeat 65534 {
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cx16.r0++
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}
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repeat 65535 {
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cx16.r0++
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}
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repeat 0 {
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cx16.r0++
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}
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}
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}"""
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val result = compileText(VMTarget(), false, src, writeAssembly = true)!!
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val start = result.codegenAst!!.entrypoint()!!
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start.children.size shouldBe 11
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val virtfile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".p8ir")
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VmRunner().runAndTestProgram(virtfile.readText()) { vm ->
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vm.memory.getUW(0xff02) shouldBe 3837u // $ff02 = cx16.r0
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}
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}
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test("repeat counts (variable)") {
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val src="""
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main {
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sub start() {
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uword count
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cx16.r0 = 0
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count=255
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repeat count {
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cx16.r0++
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}
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count=256
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repeat count {
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cx16.r0++
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}
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count=257
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repeat count {
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cx16.r0++
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}
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count=1023
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repeat count {
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cx16.r0++
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}
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count=1024
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repeat count {
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cx16.r0++
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}
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count=1025
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repeat count {
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cx16.r0++
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}
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count=65534
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repeat count {
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cx16.r0++
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}
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count=65535
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repeat count {
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cx16.r0++
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}
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count=0
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repeat count {
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cx16.r0++
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}
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}
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}"""
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val result = compileText(VMTarget(), false, src, writeAssembly = true)!!
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val start = result.codegenAst!!.entrypoint()!!
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start.children.size shouldBe 22
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val virtfile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".p8ir")
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VmRunner().runAndTestProgram(virtfile.readText()) { vm ->
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vm.memory.getUW(0xff02) shouldBe 3837u // $ff02 = cx16.r0
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}
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}
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test("asm chunk labels in IR code") {
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val src="""
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main {
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sub start() {
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instructions.match()
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}
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}
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instructions {
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asmsub match() {
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%asm {{
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rts
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}}
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}
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%asm {{
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nop
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}}
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}"""
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compileText(VMTarget(), false, src, writeAssembly = true) shouldNotBe null
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}
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test("IR codegen for while loop with shortcircuit") {
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val src="""
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main {
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sub start() {
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cx16.r0L=1
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while cx16.r0L < 10 and cx16.r0L>0 {
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cx16.r0L++
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}
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}
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}"""
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compileText(VMTarget(), true, src, writeAssembly = true) shouldNotBe null
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}
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test("push() and pop() generate correct IR instructions") {
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val src="""
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main {
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sub start() {
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ubyte bb
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uword ww
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sys.push(42)
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bb++
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bb=sys.pop()
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sys.pushw(9999)
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ww++
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ww=sys.popw()
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}
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}"""
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val result = compileText(VMTarget(), true, src, writeAssembly = true)!!
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val virtfile = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".p8ir")
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val irProgram = IRFileReader().read(virtfile)
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val start = irProgram.blocks[0].children[0] as IRSubroutine
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val instructions = start.chunks.flatMap { c->c.instructions }
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instructions.size shouldBe 13
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instructions[3].opcode shouldBe Opcode.PUSH
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instructions[3].type shouldBe IRDataType.BYTE
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instructions[5].opcode shouldBe Opcode.POP
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instructions[5].type shouldBe IRDataType.BYTE
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instructions[8].opcode shouldBe Opcode.PUSH
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instructions[8].type shouldBe IRDataType.WORD
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instructions[10].opcode shouldBe Opcode.POP
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instructions[10].type shouldBe IRDataType.WORD
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}
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}) |