mirror of
https://github.com/irmen/prog8.git
synced 2024-11-27 03:50:27 +00:00
269 lines
7.7 KiB
Lua
269 lines
7.7 KiB
Lua
; optimized graphics routines for just the single screen mode: lores 320*240, 256c (8bpp)
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; bitmap image needs to start at VRAM addres $00000.
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; This is compatible with the CX16's screen mode 128. (void cx16.set_screen_mode(128))
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%import verafx
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gfx_lores {
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%option ignore_unused
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sub set_screen_mode() {
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cx16.VERA_CTRL=0
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cx16.VERA_DC_VIDEO = (cx16.VERA_DC_VIDEO & %11001111) | %00100000 ; enable only layer 1
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cx16.VERA_DC_HSCALE = 64
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cx16.VERA_DC_VSCALE = 64
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cx16.VERA_L1_CONFIG = %00000111
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cx16.VERA_L1_MAPBASE = 0
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cx16.VERA_L1_TILEBASE = 0
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clear_screen(0)
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}
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sub clear_screen(ubyte color) {
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if verafx.available() {
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; use verafx cache writes to quicly clear the screen
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const ubyte vbank = 0
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const uword vaddr = 0
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cx16.VERA_CTRL = 0
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cx16.VERA_ADDR_H = vbank | %00110000 ; 4-byte increment
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cx16.VERA_ADDR_M = msb(vaddr)
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cx16.VERA_ADDR_L = lsb(vaddr)
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cx16.VERA_CTRL = 6<<1 ; dcsel = 6, fill the 32 bits cache
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cx16.VERA_FX_CACHE_L = color
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cx16.VERA_FX_CACHE_M = color
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cx16.VERA_FX_CACHE_H = color
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cx16.VERA_FX_CACHE_U = color
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cx16.VERA_CTRL = 2<<1 ; dcsel = 2
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cx16.VERA_FX_MULT = 0
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cx16.VERA_FX_CTRL = %01000000 ; cache write enable
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repeat 320/4/4 {
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%asm {{
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ldy #240
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- stz cx16.VERA_DATA0
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stz cx16.VERA_DATA0
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stz cx16.VERA_DATA0
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stz cx16.VERA_DATA0
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dey
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bne -
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}}
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}
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cx16.VERA_FX_CTRL = 0 ; cache write disable
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cx16.VERA_CTRL = 0
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return
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}
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; fallback to cpu clear
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cx16.VERA_CTRL=0
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cx16.VERA_ADDR=0
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cx16.VERA_ADDR_H = 1<<4 ; 1 pixel auto increment
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repeat 240 {
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%asm {{
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lda p8v_color
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ldy #320/8
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- .rept 8
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sta cx16.VERA_DATA0
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.endrept
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dey
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bne -
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}}
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}
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cx16.VERA_ADDR=0
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cx16.VERA_ADDR_H = 0
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}
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asmsub plot(uword x @AX, ubyte y @Y, ubyte color @R0) {
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; x in r0, y in r1, color.
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%asm {{
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clc
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adc times320_lo,y
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sta cx16.VERA_ADDR_L
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txa
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adc times320_mid,y
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sta cx16.VERA_ADDR_M
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lda #0
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adc times320_hi,y
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sta cx16.VERA_ADDR_H
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lda cx16.r0L
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sta cx16.VERA_DATA0
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rts
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}}
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}
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sub line(uword x1, ubyte y1, uword x2, ubyte y2, ubyte color) {
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; Bresenham algorithm.
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; This code special-cases various quadrant loops to allow simple ++ and -- operations.
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; NOTE: this is about twice as fast as the kernal routine GRAPH_draw_line, and ~3-4 times as fast as gfx2.line()
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; it trades memory for speed (uses inline plot routine and multiplication lookup tables)
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;
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; NOTE: is currently still a regular 6502 routine, could likely be made much faster with the VeraFX line helper.
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cx16.r3L = y2 ; ensure zeropage
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cx16.r1L = y1 ; ensure zeropage
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if cx16.r1L > cx16.r3L {
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; make sure dy is always positive to have only 4 instead of 8 special cases
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cx16.r0 = x1
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x1 = x2
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x2 = cx16.r0
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cx16.r0L = cx16.r1L
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cx16.r1L = cx16.r3L
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cx16.r3L = cx16.r0L
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}
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word @zp dx = x2 as word
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word @zp dy = cx16.r3L
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dx -= x1
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dy -= cx16.r1L
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if dx==0 {
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vertical_line(x1, cx16.r1L, lsb(dy)+1, color)
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return
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}
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if dy==0 {
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if x1>x2
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x1=x2
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horizontal_line(x1, cx16.r1L, abs(dx) as uword +1, color)
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return
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}
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word @zp d = 0
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bool positive_ix = true
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if dx < 0 {
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dx = -dx
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positive_ix = false
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}
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word @zp dx2 = dx*2
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word @zp dy2 = dy*2
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cx16.r0 = x1 ; ensure zeropage
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cx16.r2 = x2 ; ensure zeropage
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cx16.VERA_CTRL = 0
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if dx >= dy {
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if positive_ix {
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repeat {
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plot()
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if cx16.r0==cx16.r2
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return
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cx16.r0++
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d += dy2
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if d > dx {
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cx16.r1L++
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d -= dx2
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}
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}
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} else {
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repeat {
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plot()
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if cx16.r0==cx16.r2
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return
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cx16.r0--
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d += dy2
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if d > dx {
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cx16.r1L++
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d -= dx2
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}
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}
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}
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}
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else {
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if positive_ix {
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repeat {
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plot()
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if cx16.r1L == cx16.r3L
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return
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cx16.r1L++
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d += dx2
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if d > dy {
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cx16.r0++
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d -= dy2
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}
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}
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} else {
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repeat {
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plot()
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if cx16.r1L == cx16.r3L
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return
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cx16.r1L++
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d += dx2
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if d > dy {
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cx16.r0--
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d -= dy2
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}
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}
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}
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}
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asmsub plot() {
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; internal plot routine for the line algorithm: x in r0, y in r1, color in variable.
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%asm {{
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ldy cx16.r1L
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clc
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lda times320_lo,y
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adc cx16.r0L
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sta cx16.VERA_ADDR_L
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lda times320_mid,y
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adc cx16.r0H
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sta cx16.VERA_ADDR_M
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lda #0
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adc times320_hi,y
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sta cx16.VERA_ADDR_H
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lda p8v_color
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sta cx16.VERA_DATA0
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rts
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}}
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}
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}
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sub horizontal_line(uword xx, ubyte yy, uword length, ubyte color) {
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if length==0
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return
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plot(xx, yy, color) ; set starting position by reusing plot routine
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; set vera auto-increment to 1 pixel
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cx16.VERA_ADDR_H = cx16.VERA_ADDR_H & %00000111 | (1<<4)
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%asm {{
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lda p8v_color
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ldx p8v_length+1
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beq +
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ldy #0
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- sta cx16.VERA_DATA0
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iny
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bne -
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dex
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bne -
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+ ldy p8v_length ; remaining
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beq +
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- sta cx16.VERA_DATA0
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dey
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bne -
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+
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}}
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}
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sub vertical_line(uword xx, ubyte yy, ubyte lheight, ubyte color) {
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if lheight==0
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return
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plot(xx, yy, color) ; set starting position by reusing plot routine
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; set vera auto-increment to 320 pixel increment (=next line)
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cx16.VERA_ADDR_H = cx16.VERA_ADDR_H & %00000111 | (14<<4)
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%asm {{
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ldy p8v_lheight
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lda p8v_color
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- sta cx16.VERA_DATA0
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dey
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bne -
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}}
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}
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%asm {{
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; multiplication by 320 lookup table
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times320 := 320*range(240)
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times320_lo .byte <times320
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times320_mid .byte >times320
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times320_hi .byte `times320
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}}
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}
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