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https://github.com/irmen/prog8.git
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425 lines
18 KiB
Kotlin
425 lines
18 KiB
Kotlin
package prog8tests.codegeneration
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import io.kotest.core.spec.style.FunSpec
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import io.kotest.engine.spec.tempdir
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import prog8.code.target.Cx16Target
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import prog8tests.helpers.compileText
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import prog8tests.helpers.shouldContainInOrder
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import kotlin.io.path.readText
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class TestIfExpressionOptimizations : FunSpec({
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val outputDir = tempdir().toPath()
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test("if-expression operand swapping 1000 == w") {
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val text = """
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main {
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sub start() {
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uword @shared w = cx16.r0
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ubyte result = if 1000 == w then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// 1000 == w should be swapped to w == 1000
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// and generate optimized word comparison using AY registers:
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// lda p8v_w | cmp #<1000 | bne false | ldy p8v_w+1 | cpy #>1000 | bne false
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asm.shouldContainInOrder("ldy", "p8v_w+1", "lda", "p8v_w", "cmp", "#<1000", "bne", "ifexpr_false", "cpy", "#>1000", "bne", "ifexpr_false")
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}
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test("if-expression direct branching for byte") {
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val text = """
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main {
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sub start() {
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ubyte @shared b = cx16.r0L
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ubyte result = if b < 20 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// b < 20 should use lda b | cmp #20 | bcs false
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asm.shouldContainInOrder("lda", "p8v_b", "cmp", "#20", "bcs", "ifexpr_false")
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}
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test("if-expression bitwise AND optimization (BIT instruction)") {
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val text = """
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main {
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sub start() {
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ubyte @shared b = cx16.r0L
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ubyte result = if (b & 128) != 0 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// b & 128 should use bit p8v_b | bpl false
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asm.shouldContainInOrder("bit", "p8v_b", "bpl", "ifexpr_false")
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}
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test("if-expression pointer dereference condition") {
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val text = """
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main {
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sub start() {
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ubyte @shared x = 42
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^^ubyte p = &&x
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ubyte result = if p^^ == 0 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// p^^ should load indirect byte from pointer and branch on zero
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asm.shouldContainInOrder("lda", "(p8v_p)", "cmp", "#0")
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}
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test("if-expression for word equals number") {
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val text = """
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main {
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sub start() {
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long @shared l = 0
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l = l + 1
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ubyte result = if l != 0 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// long != 0 should use ora chain
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asm.shouldContainInOrder("lda", "p8v_l", "ora", "p8v_l+1", "ora", "p8v_l+2", "ora", "p8v_l+3", "beq", "ifexpr_false")
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}
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test("if-expression long comparison optimization") {
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val text = """
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main {
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sub start() {
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long @shared l = 0
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l = l + 1
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ubyte result = if l < 200000 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// 200000 = 0x030d40
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// Signed long comparison uses sbc with lowercase hex literals and signed branch sequence
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asm.shouldContainInOrder(
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"sec",
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"lda", "p8v_l", "sbc", $$"#$40",
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"lda", "p8v_l+1", "sbc", $$"#$0d",
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"lda", "p8v_l+2", "sbc", $$"#$03",
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"lda", "p8v_l+3", "sbc", $$"#$00",
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"bvc", "eor", "#128", "bpl", "ifexpr_false"
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)
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}
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test("if-expression long == 0 optimization") {
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val text = """
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main {
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sub start() {
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long @shared l = 0
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l = l + 1
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ubyte result = if l == 0 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// long == 0 should use ora chain + bne false
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asm.shouldContainInOrder("lda", "p8v_l", "ora", "p8v_l+1", "ora", "p8v_l+2", "ora", "p8v_l+3", "bne", "ifexpr_false")
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}
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test("if-expression long == constant optimization") {
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val text = """
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main {
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sub start() {
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long @shared l = 100000
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ubyte result = if l == 100000 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// 100000 = $0186a0 -> $a0, $86, $01, $00
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asm.shouldContainInOrder(
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"lda", "p8v_l", "cmp", $$"#$a0", "bne", "ifexpr_false",
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"lda", "p8v_l+1", "cmp", $$"#$86", "bne", "ifexpr_false",
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"lda", "p8v_l+2", "cmp", $$"#$01", "bne", "ifexpr_false",
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"lda", "p8v_l+3", "cmp", $$"#$00", "bne", "ifexpr_false"
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)
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}
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test("if-expression long < 0 optimization") {
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val text = """
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main {
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sub start() {
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long @shared l = -1
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ubyte result = if l < 0 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// long < 0 should use lda l+3 | bpl false
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asm.shouldContainInOrder("lda", "p8v_l+3", "bpl", "ifexpr_false")
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}
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test("if-expression long >= 0 optimization") {
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val text = """
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main {
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sub start() {
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long @shared l = 1
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ubyte result = if l >= 0 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// long >= 0 should use lda l+3 | bmi false
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asm.shouldContainInOrder("lda", "p8v_l+3", "bmi", "ifexpr_false")
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}
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test("if-expression long > 0 optimization") {
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val text = """
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main {
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sub start() {
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long @shared l = 1
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ubyte result = if l > 0 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// long > 0 should use lda l+3 | bmi false | ora l+2 | ora l+1 | ora l | beq false
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asm.shouldContainInOrder("lda", "p8v_l+3", "bmi", "ifexpr_false", "ora", "p8v_l+2", "ora", "p8v_l+1", "ora", "p8v_l", "beq", "ifexpr_false")
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}
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test("if-expression word indexed < 0 optimization") {
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val text = """
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main {
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word[10] @shared words
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sub start() {
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ubyte @shared i = 5
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ubyte @shared result = if words[i] < 0 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// words[i] < 0 should use lda words_msb,y | bpl false
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// it uses ldy p8v_i directly because it's a split array (no scaling needed)
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asm.shouldContainInOrder("ldy", "p8v_i", "lda", "p8v_words_msb,y", "bpl", "ifexpr_false")
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}
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test("if-expression long indexed > 0 optimization") {
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val text = """
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main {
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long[10] @shared longs
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sub start() {
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ubyte @shared i = 2
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ubyte @shared result = if longs[i] > 0 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// longs[i] > 0 should use direct indexed access:
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// lda longs+3,y | bmi false | ora longs+2,y | ora longs+1,y | ora longs,y | beq false
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asm.shouldContainInOrder("lda", "p8v_longs+3,y", "bmi", "ifexpr_false", "ora", "p8v_longs+2,y", "ora", "p8v_longs+1,y", "ora", "p8v_longs,y", "beq", "ifexpr_false")
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}
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test("if-expression long from function < 0 optimization") {
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val text = """
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main {
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sub getlong() -> long { return -1 }
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sub start() {
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ubyte result = if getlong() < 0 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// getlong() result will be in R14R15 for long return
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asm.shouldContainInOrder("jsr", "p8s_getlong", "lda", "cx16.r14+3", "bpl", "ifexpr_false")
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}
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test("if-expression word == word optimization") {
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val text = """
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main {
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sub start() {
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uword @shared w1 = cx16.r0
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uword @shared w2 = cx16.r1
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ubyte result = if w1 == w2 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// w1 == w2 should use optimized direct comparison using AY registers
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asm.shouldContainInOrder("cmp", "p8v_w2", "bne", "ifexpr_false", "cpy", "p8v_w2+1", "bne", "ifexpr_false")
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}
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test("if-expression word indexed == 0 optimization") {
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val text = """
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main {
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uword[10] @shared words
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sub start() {
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ubyte @shared i = 5
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ubyte @shared result = if words[i] == 0 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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asm.shouldContainInOrder("ldy", "p8v_i", "lda", "_lsb,y", "ora", "_msb,y", "bne", "ifexpr_false")
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}
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test("if-expression word split array indexed != 0 optimization") {
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val text = """
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main {
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word[10] @shared words
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sub start() {
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ubyte @shared i = 2
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ubyte @shared result = if words[i] != 0 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// word arrays are split by default
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asm.shouldContainInOrder("ldy", "p8v_i", "lda", "_lsb,y", "ora", "_msb,y", "beq", "ifexpr_false")
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}
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test("if-expression word indexed <= 0 optimization") {
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val text = """
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main {
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word[10] @shared words
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sub start() {
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ubyte i = 1
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ubyte result = if words[i] <= 0 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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asm.shouldContainInOrder("lda", "_msb,y", "bmi +", "ora", "_lsb,y", "bne", "ifexpr_false", "+")
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}
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test("if-expression word indexed > 0 optimization") {
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val text = """
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main {
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word[10] @shared words
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sub start() {
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ubyte i = 1
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ubyte result = if words[i] > 0 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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asm.shouldContainInOrder("lda", "_msb,y", "bmi", "ifexpr_false", "ora", "_lsb,y", "beq", "ifexpr_false")
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}
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test("if-expression addressOf == 0 optimization") {
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val text = """
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main {
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ubyte @shared x
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sub start() {
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ubyte result = if (&&x) == 0 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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asm.shouldContainInOrder("lda", "#<", "p8v_x", "ora", "#>", "p8v_x", "bne", "ifexpr_false")
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}
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test("if-expression word < word optimization") {
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val text = """
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main {
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sub start() {
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uword @shared w1 = cx16.r0
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uword @shared w2 = cx16.r1
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ubyte result = if w1 < w2 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// w1 < w2 should use cmp + bcs for unsigned or signed comparison
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asm.shouldContainInOrder("lda", "p8v_w1", "cmp", "p8v_w2", "bcs", "ifexpr_false")
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}
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test("if-expression word equals zero optimization") {
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val text = """
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main {
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sub start() {
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uword @shared w = cx16.r0
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ubyte result = if w == 0 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// w == 0 should use ora + bne for simple zero check
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asm.shouldContainInOrder("ora", "p8v_w+1", "bne", "ifexpr_false")
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}
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test("if-expression long == long optimization") {
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val text = """
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main {
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sub start() {
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long @shared l1 = 12345
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long @shared l2 = 67890
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ubyte result = if l1 == l2 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// l1 == l2 should use optimized variable comparison (branch to skip when differ)
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asm.shouldContainInOrder("cmp", "p8v_l2", "bne", "+", "cmp", "p8v_l2+1", "bne", "+", "cmp", "p8v_l2+2", "bne", "+", "cmp", "p8v_l2+3", "+")
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}
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test("if-expression long != long optimization") {
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val text = """
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main {
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sub start() {
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long @shared l1 = 12345
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long @shared l2 = 67890
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ubyte result = if l1 != l2 then 1 else 0
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cx16.r1L = result
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}
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}
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""".trimIndent()
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val result = compileText(Cx16Target(), false, text, outputDir, writeAssembly = true)!!
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val asm = result.compilationOptions.outputDir.resolve(result.compilerAst.name + ".asm").readText()
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// l1 != l2 should use optimized variable comparison with skip label pattern:
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// cmp p8v_l2, bne skip, ..., cmp p8v_l2+3, beq ifexpr_false, skip:
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asm.shouldContainInOrder("cmp p8v_l2", "bne +", "cmp p8v_l2+3", "beq", "ifexpr_false")
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}
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})
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