mirror of
https://github.com/marketideas/qasm.git
synced 2026-10-24 22:02:28 +00:00
Shawn Quick
dfcaae62dd
Move the assembler to src/qasm. qlink links OMF 1.0 and 2.0 from a script. makeBin flattens a load file, qomf dumps OMF, and qpro builds ProDOS volumes. APW and MPW assemble through the ORCA front end. Relocatable modules emit OMF objects. Listings stay off unless -l is set. make boot assembles the GS/OS 6.0.1 ProDOS 8 kernel and BASIC.SYSTEM into an 800K volume. BASIC.SYSTEM accepts ls and pfx, and its splash reports PRODOS BASIC 2.0, copyright 1983-2026. IIGS.601.SRC is the source and the BASIC.SYSTEM oracle that image is built from.
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23 KiB
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1 line
23 KiB
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eject
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; ;
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; equates part 1 ;
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; ;
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; by ;
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; fern bachman jr. ;
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; ;
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; Copyright Apple Computer, Inc. 1985-1993 ;
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; All Rights Reserved. ;
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; ;
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; ;
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; 08/13/87 RBM Change: DISKREG is now in bank $E1 ;
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; Added IWM equates ;
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; ;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;---------->> real zero page equates <<----------
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cswl equ $000036 ;character output hook
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cswh equ $000037
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kswl equ $000038 ;character input hook
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kswh equ $000039
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;---------->> screen hole equates <<----------
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mslot equ $0007f8 ;=$cn ;n=slot using $c800
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;---------->> bank 1 / page 1 permanent storage <<----------
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mnemstkptr equ $010100 ;main stack pointer
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alemstkptr equ $010101 ;alternate stack pointer
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;---------->> page 3 vectors <<----------
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oswmstrt equ $0003d0 ;quitmon jumps here
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brkv equ $0003f0 ;vectors here after break
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softev equ $0003f2 ;warm RESET vector
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pwredup equ $0003f4 ;this must = eor #$A5 of softev+1
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amperv equ $0003f5 ;Applesoft "&" vector
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usradr equ $0003f8 ;monitor Ctrl-Y vector
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nmi equ $0003fb ;NMI vector
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irqloc equ $0003fe ;maskable interrupt vector
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pro8mli equ $00bf00 ;address of prodos8 mli entry point
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;---------->> hardware equates <<----------
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ioadr equ $c000 ;all i/o is at $cxxx
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kbd equ $c000 ;bit 7=1 if keystroke
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clr80col equ $c000 ;disable 80 column store
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set80col equ $c001 ;enable 80 column store
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rdmainram equ $c002 ;read from main 48k ram
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rdcardram equ $c003 ;read from alt. 48k ram
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wrmainram equ $c004 ;write to main 48k ram
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wrcardram equ $c005 ;write to alt. 48k ram
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setslotcxrom equ $c006 ;use roms on cards
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setintcxrom equ $c007 ;use internal rom
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setstdzp equ $c008 ;use main zero page/stack
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setaltzp equ $c009 ;use alt. zero page/stack
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setintc3rom equ $c00a ;enable internal slot 3 rom
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setslotc3rom equ $c00b ;enable external slot 3 rom
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clr80vid equ $c00c ;disable 80 column hardware
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set80vid equ $c00d ;enable 80 column hardware
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clraltchar equ $c00e ;normal lc, flashing uc
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setaltchar equ $c00f ;normal inverse, lc; no flash
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kbdstrb equ $c010 ;turn off key pressed flag
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rdlcbnk2 equ $c011 ;bit 7=1 if LC bank 2 is in
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rdlcram equ $c012 ;bit 7=1 if LC ram read enabled
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rdramrd equ $c013 ;bit 7=1 if reading alt 48k
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rdramwrt equ $c014 ;bit 7=1 if writing alt 48k
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rdcxrom equ $c015 ;bit 7=1 if using int rom
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rdaltzp equ $c016 ;bit 7=1 if slot zp enabled
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rdc3rom equ $c017 ;bit 7=1 if slot c3 space enabled
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rd80col equ $c018 ;bit 7=1 if 80 column store
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rdvblbar equ $c019 ;bit 7=1 if not vbl
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rdtext equ $c01a ;bit 7=1 if text (not graphics)
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rdmix equ $c01b ;bit 7=1 if mixed mode on
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rdpage2 equ $c01c ;bit 7=1 if txtpage2 switched in
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rdhires equ $c01d ;bit 7=1 if hires is on
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altcharset equ $c01e ;bit 7=1 if alternate char set in use
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rd80vid equ $c01f ;bit 7=1 if 80 column hardware in
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; __7______6______5______4______3______2______1______0___
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;| | | | | | | | |
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;| vgc | 1sec | scan | ext | | 1sec | scan | ext |
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;| int | int | int | int |unused| int | int | int |
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;|active|active|active|active| |enable|enable|enable|
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;|______|______|______|______|______|______|______|______|
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; ^^^^^ vgcint status byte ^^^^^
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; vgcint bits defined as follows
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; bit 7= 1 if interrupt generated by vgc
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; bit 6= 1 if 1 second timer interrupt
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; bit 5= 1 if scan line interrupt
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; bit 4= 1 if external interrupt
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; bit 3= unused
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; bit 2= 1 second timer interrupt enable
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; bit 1= scan line interrupt enable
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; bit 0= external interrupt enable
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vgcint equ $c023 ;vgc interrupt register
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; __7______6______5______4______3______2______1______0___
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;| | |update| | | | | |
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;| open |closed| mod |keypad|repeat| caps | ctrl |shift |
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;| apple| apple|no key| key |active| lock | key | key |
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;| key | key | press|active| |active|active|active|
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;|______|______|______|______|______|______|______|______|
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; ^^^^^ keymodreg status byte ^^^^^
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; keymodreg bits defined as follows
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; bit 7= open apple key active
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; bit 6= closed apple key active
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; bit 5= updated modifier latch without keypress
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; bit 4= keypad key active
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; bit 3= repeat active
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; bit 2= caps lock active
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; bit 1= control key active
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; bit 0= shift key active
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keymodreg equ $c025 ;key modifier register
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; __7______6______5______4______3______2______1______0___
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;| | | | | | | | |
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;| |
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;| data to/from keyboard micro |
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;| |
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;|______|______|______|______|______|______|______|______|
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; ^^^^^ datareg byte ^^^^^
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; datareg bits defined as follows
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; bit 7,6,5,4,3,2,1,0 = data to/from keyboard micro
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;
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; data at interrupt time in this register is defined as
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; bit 7= response byte if set, otherwise status byte
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; bit 6= abort valid if set and all other bits reset
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; bit 5= desktop manager key sequence pressed
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; bit 4= flush buffer key sequence pressed
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; bit 3= srq valid if set
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; bit 2,1,0 if all bits clear then no fdb data valid,
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; else the bits indicate the number of valid
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; bytes received minus 1. (2-8 bytes total)
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datareg equ $c026 ;data register in keyglu chip
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; __7______6______5______4______3______2______1______0___
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;| | | | | | | | |
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;| mouse| mouse| data | data | key | key | mouse| cmd |
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;| reg | int | reg | int | data | int |x/yreg| reg |
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;| full |enable| full |enable| full |enable| data | full |
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;|______|______|______|______|______|______|______|______|
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; ^^^^^ kmstatus status byte ^^^^^
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; kmstatus bits defined as follows
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; bit 7= 1 if mouse register full
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; bit 6= mouse interrupt disable/enable
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; bit 5= 1 if data register full
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; bit 4= data interrupt enable
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; bit 3= 1 if key data full <<<<<------never use, won't work
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; bit 2= key data interrupt enable <<<<<------never use, won't work
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; bit 1= 0 = mouse 'x' register data available
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; 1 = mouse 'y' register data available
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; bit 0= command register full
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kmstatus equ $c027 ;keyboard/mouse status register
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; __7______6______5______4______3______2______1______0___
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;| | | | | | | | |
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;|slot7 |slot6 |slot5 |slot4 | |slot2 |slot1 | |
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;|intext|intext|intext|intext| 0 |intext|intext| 0 |
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;|enable|enable|enable|enable| |enable|enable| |
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;|______|______|______|______|______|______|______|______|
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; ^^^^^ sltromsel byte ^^^^^
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; sltromsel bits defined as follows
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; bit 7= 0 enables internal slot 7 -- 1 enables slot rom
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; bit 6= 0 enables internal slot 6 -- 1 enables slot rom
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; bit 5= 0 enables internal slot 5 -- 1 enables slot rom
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; bit 4= 0 enables internal slot 4 -- 1 enables slot rom
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; bit 3= must be 0
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; bit 2= 0 enables internal slot 2 -- 1 enables slot rom
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; bit 1= 0 enables internal slot 1 -- 1 enables slot rom
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; bit 0= must be 0
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sltromsel equ $c02d ;slot rom select
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spkr equ $c030 ;clicks the speaker
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; __7______6______5______4______3______2______1______0___
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;| | | | | | | | |
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;| 3.5" | 3.5" | | | | | | |
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;| head | drive| 0 | 0 | 0 | 0 | 0 | 0 |
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;|select|enable| | | | | | |
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;|______|______|______|______|______|______|______|______|
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; ^^^^^ diskreg status byte ^^^^^
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; diskreg bits defined as follows
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; bit 7= 1 to select head on 3.5" drive to use
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; bit 6= 1 to enable 3.5" drive
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; bit 5,4,3,2,1,0= unused
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diskreg equ $E1C031 ;used for 3.5" disk drives
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; __7______6______5______4______3______2______1______0___
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;| | | | | | | | |
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;| | stop | | stop | stop | stop | stop | stop |
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;| 0 |i/o/lc| 0 |auxh-r|suprhr|hires2|hires1|txt pg|
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;| |shadow| |shadow|shadow|shadow|shadow|shadow|
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;|______|______|______|______|______|______|______|______|
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; ^^^^^ shadow byte ^^^^^
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; shadow bits defined as follows
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; bit 7= must write 0
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; bit 6= 1 to inhibit i/o and language card operation
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; bit 5= must write 0
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; bit 4= 1 to inhibit shadowing aux hi-res page
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; bit 3= 1 to inhibit shadowing 32k video buffer
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; bit 2= 1 to inhibit shadowing hires page 2
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; bit 1= 1 to inhibit shadowing hires page 1
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; bit 0= 1 to inhibit shadowing text pages
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shadow equ $c035 ;shadow register
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; __7______6______5______4______3______2______1______0___
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;| | | | | | | | |
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;| slow/| | |shadow|slot 7|slot 6|slot 5|slot 4|
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;| fast | 0 | 0 |in all|motor |motor | motor| motor|
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;| speed| | | ram |detect|detect|detect|detect|
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;|______|______|______|______|______|______|______|______|
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; ^^^^^ cyareg byte ^^^^^
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; cyareg bits defined as follows
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; bit 7= 0=slow system speed -- 1=fast system speed
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; bit 6= must write 0
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; bit 5= must write 0
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; bit 4= shadow in all ram banks
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; bit 3= slot 7 disk motor on detect
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; bit 2= slot 6 disk motor on detect
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; bit 1= slot 5 disk motor on detect
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; bit 0= slot 4 disk motor on detect
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cyareg equ $c036 ;speed and motor on detect
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; __7______6______5______4______3______2______1______0___
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;| | | | | | | | |
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;| | | |enable|enable|enable|enable|enable|
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;| 0 | 0 | 0 |1/4sec| vbl |switch| move | mouse|
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;| | | | ints | ints | ints | ints | |
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;|______|______|______|______|______|______|______|______|
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; ^^^^^ inten byte ^^^^^
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; inten bits defined as follows
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; bit 7= must be 0
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; bit 6= must be 0
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; bit 5= must be 0
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; bit 4= 1 to enable 1/4 second interrupts
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; bit 3= 1 to enable vbl interrupts
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; bit 2= 1 to enable mega // mouse switch interrupts
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; bit 1= 1 to enable mega // mouse movement interrupts
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; bit 0= 1 to enable mega // mouse operation
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inten equ $c041 ;interrupt enable register
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; __7______6______5______4______3______2______1______0___
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;| | | | | | | | |
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;|mmouse|mmouse|status|status|status|status|status|status|
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;| now | last | an3 |1/4sec| vbl |switch| move |system|
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;|button|button| | int | int | int | int | irq |
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;|______|______|______|______|______|______|______|______|
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; ^^^^^ intflag byte ^^^^^
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; intflag bits defined as follows
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; bit 7= 1 if mouse button currently down
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; bit 6= 1 if mouse button was down on last read
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; bit 5= status of an3
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; bit 4= 1 if 1/4 second interrupted
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; bit 3= 1 if vbl interrupted
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; bit 2= 1 if mega // mouse switch interrupted
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; bit 1= 1 if mega // mouse movement interrupted
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; bit 0= 1 if system irq line is asserted
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intflag equ $c046 ;interrupt flag register
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clrvblint equ $c047 ;clear the vbl and 3.75hz interrupt flags
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txtclr equ $c050 ;switch in graphics (not text)
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txtset equ $c051 ;switch in text (not graphics)
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mixclr equ $c052 ;clear mixed-mode
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mixset equ $c053 ;set mixed-mode (4 lines text)
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txtpage1 equ $c054 ;switch in text page 1
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txtpage2 equ $c055 ;switch in text page 2
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lores equ $c056 ;low-resolution graphics
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hires equ $c057 ;high-resolution graphics
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setan0 equ $c058 ;clear annunciator 0
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clran0 equ $c059 ;set annunciator 0
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setan1 equ $c05a ;clear annunciator1
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clran1 equ $c05b ;set annunciator 1
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setan2 equ $c05c ;clear annunciator 2
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clran2 equ $c05d ;set annunciator 2
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setan3 equ $c05e ;clear annunciator 3
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clran3 equ $c05f ;set annunciator 3
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butn3 equ $c060 ;read switch 3
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butn0 equ $c061 ;open apple key
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butn1 equ $c062 ;closed apple key
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butn2 equ $c063 ;read switch 2
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; __7______6______5______4______3______2______1______0___
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;| | | | | | | | |
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;| alzp | page2| ramrd|ramwrt| rdrom|lcbnk2|rombnk| intcx|
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;|status|status|status|status|status|status|status|status|
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;| | | | | | | | |
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;|______|______|______|______|______|______|______|______|
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; ^^^^^ statereg status byte ^^^^^
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; statereg bits defined as follows
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; bit 7= alzp status
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; bit 6= page2 status
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; bit 5= ramrd status
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; bit 4= ramwrt status
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; bit 3= rdrom status (read only ram/rom (0/1))
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; important note:
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; do two reads to $c083 then change statereg
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; to change lcram/rom banks (0/1) and still
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; have the language card write enabled.
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; bit 2= lcbnk2 status 0=LC bank 0 - 1=LC bank 1
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; bit 1= rombank status
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; bit 0= intcxrom status
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statereg equ $c068 ;state register
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;---------->> language card soft switches <<----------
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romin equ $c081 ;enable rom read, 2 reads write enb LC ram
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lcbank2 equ $c083 ;sel LC ram bank2, 2 rds wrt enb LC ram
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lcbank1 equ $c08b ;sel LC ram bank1, 2 rds wrt enb LC ram
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clrrom equ $cfff ;switch out $c8 roms
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eject
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; ;
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; equates part 2 ;
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; ;
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; by ;
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; Fern Bachman ;
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; ;
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; Copyright Apple Computer, Inc. 1985-1987 ;
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; All Rights Reserved. ;
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; ;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;---------->> tool set numbers and call numbers <<----------
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mtn equ $03 ;miscellaneous tool number
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rthfn equ $0d ;read time hex function number
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wthfn equ $0e ;write time hex function number
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mmn equ $02 ;memory manager tool number
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initdismgr equ $fe0000 ;init dispatch handler (tool locator)
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;---------->> bank $e1 equates <<----------
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brambuffer equ $e102c0 ;image of batteryram
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osvariables equ brambuffer+$80+$01 ;32 bytes of operating system vari
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;---------->> important vectors the user may change
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;---------->> ram space from locations $e10000->$e102b7 are allocated
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;---------->> for monitor and ram vectors use.
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dispatch1 equ $e10000 ;jmp vector to tool locator1
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dispatch2 equ $e10004 ;jmp vector to tool locator2
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udispatch1 equ $e10008 ;jmp vector to user's tool locator1
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udispatch2 equ $e1000c ;jmp vector to user's tool locator2
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intmgrv equ $e10010 ;jmp vector to interrupt manager
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copmgrv equ $e10014 ;jmp vector to cop manager
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abortmgrv equ $e10018 ;jmp vector to abort manager
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sysdmgrv equ $e1001c ;jmp vector to system death manager
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;---------->> tool/internal interrupt vectors <<----------
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irq_aptlk equ $e10020 ;jmp vector to aptlk interrupt handler
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irq_serial equ $e10024 ;jmp vector to serial port int handler
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irq_scan equ $e10028 ;jmp vector to scan line interrupt handler
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irq_sound equ $e1002c ;jmp vector to sound interrupt handler
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irq_vbl equ $e10030 ;jmp vector to vbl interrupt handler
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irq_mouse equ $e10034 ;jmp vector to mouse interrupt handler
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irq_qtr equ $e10038 ;jmp vector to 1/4 sec interrupt handler
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irq_kbd equ $e1003c ;jmp vector to keyboard interrupt handler
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irq_response equ $e10040 ;jmp vctr to fdb response byte int handler
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irq_srq equ $e10044 ;jmp vector to srq int handler
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irq_dskacc equ $e10048 ;jmp vector to desk accessory int handler
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irq_flush equ $e1004c ;jmp vector to flush buffer int handler
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irq_micro equ $e10050 ;jmp vector to key micro int handler
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irq_1sec equ $e10054 ;jmp vector to 1 second interrupt handler
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irq_ext equ $e10058 ;jmp vector to ext vgc interrupt handler
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irq_other equ $e1005c ;jmp vector to other interrupt handler
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cupdate equ $e10060 ;jmp vector to cursor update handler
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incbusyflg equ $e10064 ;jmp vector to increment busyflag routine
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decbusyflg equ $e10068 ;jmp vector to decrement busyflag routine
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;---------->> end of user changable interrupt vectors <<----------
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;---------->> prodos bank $e1 vectors/data bytes <<----------
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pro16mli equ $e100a8 ;1st os vector is prodos16 mli entry poi
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os_switch equ $e100ac ;called before application launch
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stkpro16mli equ $e100b0 ;stack based entry to prodos16
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os_p8_switch equ $e100b4 ;called by GQuit when GQuit is about to remove P8
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os_public_flags equ $e100b8 ;2 bytes reserved for public GS/OS flags
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;currently, bit 15 is set if GLoader doesn't
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;load any INITs or DAs.
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zero_word equ $e100ba ;guaranteed 2 zeros
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os_kind equ $e100bc ;0/1-p8/p16 current os running
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os_boot equ $e100bd ;0/1-p8/p16 booted os
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os_flag equ $e100be ;word for prodos 16 flags
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warm_cold_flag equ $e101d0 ;word: 0=cold startup/shutdown, 1=warm startup/shutdown
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;----------->> System Service Calls Bank $E1 Vectors/Handles <<---------------
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e1_move equ $E10200 ; Move routine
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e1_set_speed equ $E10204 ; Set system speed routine
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e1_slot_arbiter equ $E10208 ; Request a slot
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*****************************************************************
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*
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* EQUATES for the IWM
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*
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*****************************************************************
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ph0off equ $E1C080 ; phase 0 off
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ph0on equ $E1C081 ; phase 0 on
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ph1off equ $E1C082 ; phase 1 off
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ph1on equ $E1C083 ; phase 1 on
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ph2off equ $E1C084 ; phase 2 off
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ph2on equ $E1C085 ; phase 2 on
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ph3off equ $E1C086 ; phase 3 off
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ph3on equ $E1C087 ; phase 3 on
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motor_off equ $E1C088 ; disk motor off
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motor_on equ $E1C089 ; disk motor on
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drive0 equ $E1C08A ; select drive 0
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drive1 equ $E1C08B ; select drive 1
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q6l equ $E1C08C ; Q6 low
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q6h equ $E1C08D ; Q6 high
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q7l equ $E1C08E ; Q7 low
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q7h equ $E1C08F ; Q7 high
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*
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* ____ ____ __________
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* | | | |
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* | Q7 | Q6 | MOTOR_ON |
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* |____|____|__________|
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*
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* 0 0 0 Read all ones
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* 0 0 1 Read data register
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* 0 1 X Read status register
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* 1 0 X Read write-handshake register
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* 1 1 0 Write mode register
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* 1 1 1 write data register
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*
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*
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* ___ ___ ___ ___ ___ ___ ___ ___
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* | | | | | | | | |
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* | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | IWM Mode Register (write only)
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* |___|___|___|___|___|___|___|___|
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* | | | | | | | |____ 1 = Latch mode
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* | | | | | | |________ 0 = sychronous, 1 = asynchronous
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* | | | | | |____________ 0 = timer enable, 1 = timer disable
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* | | | | |________________ 0 = slow mode, 1 = fast mode
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* | | | |____________________ 0 = 7mHz clock, 1 = 8 mHz clock
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* | | |________________________ 1 = test mode, 0 = normal mode
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* | |____________________________ 1 = mz reset (not used)
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* |________________________________ RESERVED
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*
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* ___ ___ ___ ___ ___ ___ ___ ___
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* | | | | | | | | |
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* | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | IWM Status Register (read only)
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* |___|___|___|___|___|___|___|___|
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* | | | | | | | |____ 1 = Latch mode
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* | | | | | | |________ 0 = sychronous, 1 = asynchronous
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* | | | | | |____________ 0 = timer enable, 1 = timer disable
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* | | | | |________________ 0 = slow mode, 1 = fast mode
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* | | | |____________________ 0 = 7mHz clock, 1 = 8 mHz clock
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* | | |________________________ 1 = enbl is active
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* | |____________________________ 1 = mz
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* |________________________________ 1 = sense high, 0 = sense low
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*
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* ___ ___ ___ ___ ___ ___ ___ ___
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* | | | | | | | | |
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* | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | IWM Handshake Register (read only)
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* |___|___|___|___|___|___|___|___|
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* | | |___|___|___|___|___|____ RESERVED (read as ones)
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* | |____________________________ 1 = write state, 0 = write underrun
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* |________________________________ 1 = write data buffer register ready
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*
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