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5X: optional percentage-based speed display for accelerator config
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.gitignore
vendored
2
.gitignore
vendored
@ -6,5 +6,7 @@
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*.o
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*.lst
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*.b
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*.po
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copyrom.sh
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rom5x/accel5x
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@ -14,9 +14,13 @@
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; into the ROM without moving the menu text and the speeds
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; table.
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TESTBLD = 0 ; set to 1 to enable test code that runs in random Apple II emulator at $2000
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.ifdef testaccel
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TESTBLD = 1
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.else
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TESTBLD = 0 ; set to 1 to enable test code that runs in random Apple II hw/emulator at $2000
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; this disables the bank switch and uses the main RAM at $0E00 to simulate the
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; MIG RAM.
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; MIG RAM. Will configure a Zip Chip as if it were the IIc+ Accelerator.
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.endif
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XTRACMD = 0 ; set to 1 to enable extra accelerator speed commands
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ACCMENU = 1 ; set to 1 to enable accelerator menu
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ADEBUG = 0 ; turn on debugging (copies registers to $300 whenever they are set)
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@ -24,6 +28,7 @@ ADEBUG = 0 ; turn on debugging (copies registers to $300 when
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.psc02
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.if TESTBLD
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; test build of accel code
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spdpct = 1
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.else
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.include "iic+.defs"
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.endif
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@ -446,15 +451,19 @@ dspd: lda ZIP5DSV ; Speed in 5D register
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dex ; otherwise, next entry
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dex
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bpl @sloop
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; fall through will say 0.00 MHz
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; fall through will say 0.00 MHz or 00%
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dspd1: tya
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stx COUNTER ; which speed option is selected
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.if ::TESTBLD
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stx $0e1f ; DEBUG
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.endif
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.if ::spdpct
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lda #$a0 ; space
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.else
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and #$03 ; MHz value
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ora #$b0 ; to digit
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sta $072b ; ones
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.endif
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sta $072b ; ones (MHz) or 100s (%)
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inx
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lda spdtab,x
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tay
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@ -463,11 +472,19 @@ dspd1: tya
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lsr
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lsr
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ora #$b0
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sta $072d ; 10ths
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.if ::spdpct
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sta $072c ; 10s (%)
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.else
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sta $072d ; 10ths (MHz)
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.endif
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tya
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and #$0f
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ora #$b0
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sta $072e ; 100ths
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.if ::spdpct
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sta $072d ; 1s (%)
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.else
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sta $072e ; 100ths (MHz)
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.endif
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aminp: ldy #$00
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lda #$60
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sta (UBFPTRL),y
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@ -16,6 +16,8 @@ task :clean do
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sh "rm -f *.o"
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sh "rm -f *.lst"
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sh "rm -f *.b"
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sh "rm -f accel5x"
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sh "rm -f POOF1 *.po"
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end
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desc "Assemble all source files"
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@ -62,3 +64,15 @@ task :sf512 => [:build_rom] do
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sh "cat #{dest_rom} #{dest_rom} > sf512_#{dest_rom}"
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end
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desc "Build accel5x test binary"
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task :accel5x do
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sh "ca65 -D testaccel -o accel5x.o -l accel5x.lst B1_FD00_accel5x.s"
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sh "ld65 -t none -o accel5x accel5x.o"
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end
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desc "Build accel5x test binary into accel5x.po disk image"
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task :"accel5x.po" => [:accel5x] do
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sh "to_pro -140 accel5x"
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sh "mv -f POOF1 accel5x.po"
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end
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@ -3,6 +3,10 @@ msg1: .byte $06,$a8,$81,"ccel: Off"
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.byte $06,$b3,$00
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msg2: .byte $06,$b0,"n "
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.byte $06,$bc,$93,"pk Dly: On"
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.if ::spdpct
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.byte $07,$28,$bc,$ad," 100% ",$ad,$be
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.else
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.byte $07,$28,$bc,$ad," 4.00 MHz ",$ad,$be
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.endif
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.byte $07,$3c,$90,"dl Dly: On"
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.byte $07,$4f,$00
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@ -1,5 +1,7 @@
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; options
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newbeep = 0 ; 1 = use IIc+ beep
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spdpct = 1 ; 1 = use percent speeds in accel config
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; hardware
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;set80col = $c001
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@ -1,8 +1,29 @@
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; speed table for 4 MHz IIc Plus
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; this was confirmed by measuring a delay loop
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; for each speed. The delay loop was timed
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; timed to 1/100 sec accuracy using the Ram
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; Express II+ dclock.
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.if ::spdpct
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; percent speed table for any IIc Plus/Zip Chip
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.byte %00000001,$00
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.byte %00100000,$83
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.byte %00010000,$80
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.byte %00001000,$75
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.byte %00000100,$67
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.byte %01000000,$50
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.byte %01100000,$42
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.byte %01010000,$40
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.byte %01001000,$38
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.byte %11000000,$33
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.byte %11100000,$28
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.byte %11010000,$27
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.byte %11001000,$25
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.byte %11000100,$22
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.byte %10100000,$21
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.byte %10010000,$20
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.byte %10001000,$19
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.byte %10000100,$17
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.else
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; MHz speed table for 4 MHz IIc Plus
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.byte %00000000,$00 ; 4.0000
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.byte %00100011,$33 ; 3.3333
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.byte %00010011,$20 ; 3.2000
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@ -21,4 +42,4 @@
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.byte %10010000,$80 ; 0.8000
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.byte %10001000,$75 ; 0.7500
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.byte %10000100,$67 ; 0.6667
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.endif
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