5X: optional percentage-based speed display for accelerator config

.gitignore

@@ -6,5 +6,7 @@
 *.o
 *.lst
 *.b
+*.po
 copyrom.sh
+rom5x/accel5x
 

rom5x/B1_FD00_accel5x.s

@@ -14,9 +14,13 @@
 ; into the ROM without moving the menu text and the speeds
 ; table.
 
-TESTBLD = 0                   ; set to 1 to enable test code that runs in random Apple II emulator at $2000
+.ifdef testaccel
+TESTBLD = 1
+.else
+TESTBLD = 0                   ; set to 1 to enable test code that runs in random Apple II hw/emulator at $2000
                               ; this disables the bank switch and uses the main RAM at $0E00 to simulate the
-                              ; MIG RAM.
+                              ; MIG RAM.  Will configure a Zip Chip as if it were the IIc+ Accelerator.
+.endif
 XTRACMD = 0                   ; set to 1 to enable extra accelerator speed commands
 ACCMENU = 1                   ; set to 1 to enable accelerator menu
 ADEBUG  = 0                   ; turn on debugging (copies registers to $300 whenever they are set)
@@ -24,6 +28,7 @@ ADEBUG  = 0                   ; turn on debugging (copies registers to $300 when
         .psc02
 .if TESTBLD
   ; test build of accel code
+  spdpct = 1
 .else
   .include "iic+.defs"
 .endif
@@ -446,15 +451,19 @@ dspd:   lda   ZIP5DSV       ; Speed in 5D register
         dex                 ; otherwise, next entry
         dex
         bpl   @sloop
-        ; fall through will say 0.00 MHz
+        ; fall through will say 0.00 MHz or 00%
 dspd1:  tya
         stx   COUNTER       ; which speed option is selected
 .if ::TESTBLD
         stx   $0e1f         ; DEBUG
 .endif
+.if ::spdpct
+        lda   #$a0          ; space
+.else
         and   #$03          ; MHz value
         ora   #$b0          ; to digit
-        sta   $072b         ; ones
+.endif
+        sta   $072b         ; ones (MHz) or 100s (%)
         inx
         lda   spdtab,x
         tay
@@ -463,11 +472,19 @@ dspd1:  tya
         lsr
         lsr
         ora   #$b0
-        sta   $072d         ; 10ths
+.if ::spdpct
+        sta   $072c         ; 10s (%)
+.else
+        sta   $072d         ; 10ths (MHz)
+.endif
         tya
         and   #$0f
         ora   #$b0
-        sta   $072e         ; 100ths
+.if ::spdpct
+        sta   $072d         ; 1s (%)
+.else
+        sta   $072e         ; 100ths (MHz)
+.endif
 aminp:  ldy   #$00
         lda   #$60
         sta   (UBFPTRL),y

rom5x/Rakefile

@@ -16,6 +16,8 @@ task :clean do
   sh "rm -f *.o"
   sh "rm -f *.lst"
   sh "rm -f *.b"
+  sh "rm -f accel5x"
+  sh "rm -f POOF1 *.po"
 end
 
 desc "Assemble all source files"
@@ -62,3 +64,15 @@ task :sf512 => [:build_rom] do
   sh "cat #{dest_rom} #{dest_rom} > sf512_#{dest_rom}"
 end
 
+desc "Build accel5x test binary"
+task :accel5x do
+  sh "ca65 -D testaccel -o accel5x.o -l accel5x.lst B1_FD00_accel5x.s"
+  sh "ld65 -t none -o accel5x accel5x.o"
+end
+
+desc "Build accel5x test binary into accel5x.po disk image"
+task :"accel5x.po" => [:accel5x] do
+  sh "to_pro -140 accel5x"
+  sh "mv -f POOF1 accel5x.po"
+end
+

rom5x/accelmenu.h

@@ -3,6 +3,10 @@ msg1:   .byte $06,$a8,$81,"ccel: Off"
         .byte $06,$b3,$00
 msg2:   .byte $06,$b0,"n "
         .byte $06,$bc,$93,"pk Dly: On"
+.if ::spdpct
+        .byte $07,$28,$bc,$ad," 100% ",$ad,$be
+.else
         .byte $07,$28,$bc,$ad," 4.00 MHz ",$ad,$be
+.endif
         .byte $07,$3c,$90,"dl Dly: On"
         .byte $07,$4f,$00

rom5x/iic+.defs

@@ -1,5 +1,7 @@
 ; options
 newbeep = 0		; 1 = use IIc+ beep
+spdpct  = 1		; 1 = use percent speeds in accel config
+
 
 ; hardware
 ;set80col = $c001

rom5x/spdtab.h

@@ -1,8 +1,29 @@
-; speed table for 4 MHz IIc Plus
 ; this was confirmed by measuring a delay loop
 ; for each speed.  The delay loop was timed
 ; timed to 1/100 sec accuracy using the Ram
 ; Express II+ dclock.
+.if ::spdpct
+; percent speed table for any IIc Plus/Zip Chip
+        .byte %00000001,$00
+        .byte %00100000,$83
+        .byte %00010000,$80
+        .byte %00001000,$75
+        .byte %00000100,$67
+        .byte %01000000,$50
+        .byte %01100000,$42
+        .byte %01010000,$40
+        .byte %01001000,$38
+        .byte %11000000,$33
+        .byte %11100000,$28
+        .byte %11010000,$27
+        .byte %11001000,$25
+        .byte %11000100,$22
+        .byte %10100000,$21
+        .byte %10010000,$20
+        .byte %10001000,$19
+        .byte %10000100,$17
+.else
+; MHz speed table for 4 MHz IIc Plus
         .byte %00000000,$00 ; 4.0000
         .byte %00100011,$33 ; 3.3333
         .byte %00010011,$20 ; 3.2000
@@ -21,4 +42,4 @@
         .byte %10010000,$80 ; 0.8000
         .byte %10001000,$75 ; 0.7500
         .byte %10000100,$67 ; 0.6667
-
+.endif