Add prototype code to bigbang at the joystick port (#2)
* Add PB0 bitbanger and build process Signed-off-by: David Schmidt <1110325+david-schmidt@users.noreply.github.com> * Update target labels Signed-off-by: David Schmidt <1110325+david-schmidt@users.noreply.github.com> * Tune for 7-bit ASCII coming from a host Signed-off-by: David Schmidt <1110325+david-schmidt@users.noreply.github.com> * Update docs for bitbang joystick cable Signed-off-by: David Schmidt <1110325+david-schmidt@users.noreply.github.com> --------- Signed-off-by: David Schmidt <1110325+david-schmidt@users.noreply.github.com>
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@ -13,11 +13,13 @@ The problem is that I/O is pretty difficult. No one with one of these
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machines has come forward with the ability to get anything into or out of the
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existing serial port.
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The goal: get data of the TLC out of the machine. Hard to do without functional I/O.
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The goal: get data into and out of the TLC machine. Hard to do without functional I/O.
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### Audio to the rescue
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### Audio and Joystick to the rescue
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One thing the TLC _does_ have is sound. And a headphone jack. So we have... output.
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Looming on the horizon is bit-banged serial data via the joystick port. So we have...
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input.
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#### A long time ago...
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@ -0,0 +1,3 @@
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tlc.dsk
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*.lst
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*.bin
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@ -0,0 +1,18 @@
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AC_JAR ?= lib/AppleCommander/AppleCommander-1.3.5.13-ac.jar
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.PHONY:
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all:
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ca65 ../src/tapeout.asm --listing tapeout.lst
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ld65 ../src/tapeout.o -o tapeout.bin -C area_300.cfg
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ca65 ../src/bitbangr.asm --listing bitbangr.lst
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ld65 ../src/bitbangr.o -o bitbangr.bin -C area_300.cfg
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@cp tlcBase.dsk tlc.dsk
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cat bitbangr.bin | java -jar ${AC_JAR} -p tlc.dsk BITB BIN 0x0300
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.PHONY:
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clean:
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-rm ../src/*.o
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-rm *.lst
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-rm bitbangr.bin
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-rm tapeout.bin
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@ -0,0 +1,22 @@
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BOM
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---
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2N4401 NPN transistor
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RS-232/TTL Level Shifter
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Male DE9 connector
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Connections
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-----------
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Switch is from collector to emitter, governed by base
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4401 Collector - DE9 pin 2 (+5v)
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4401 Emitter - DE9 pin 7 (PB0*)
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4401 Base - Level Shifter out
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Level Shifter GND - DE9 pin 3 (GND) and External Power ground
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Level Shifter out - 4401 Base
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Level Shifter Vcc - (External Power)
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DE9 pin 3 (GND) - Level Shifter GND
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DE9 pin 7 (PB0*) - 4402 Emitter
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DE9 pin 2 (+5v) - 4402 Collector
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* Consider using PB1 instead of PB0; PB0 held high is like holding down the open-apple key, turns ctrl-reset into ctrl-openapple-reset all the time
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@ -1,3 +1,3 @@
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/tapeout.o
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/tapeout.bin
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/tapeout.lst
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/*.o
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/*.bin
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/*.lst
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@ -1,4 +0,0 @@
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.PHONY:
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all:
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ca65 tapeout.asm --listing tapeout.lst
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ld65 tapeout.o -o tapeout.bin -C tapeout.cfg
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@ -0,0 +1,108 @@
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;
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; Bitbang RS-232 (using a pushbutton input in our case)
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;
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;
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; CPU cycle counting must be done to meet bit-time requirements on the wire.
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; Bit time is defined as (1 / baud) seconds, or (1000000 / baud) microseconds.
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; So at 9600 baud, we get a bit time 0.000104166 seconds, or 104.166 microseconds.
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; With a 6502 CPU running at about 1MHz, each CPU clock cycle is about 1.023
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; microseconds long.
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;
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.org $300 ; For now
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; Some system constants
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WAIT = $FCA8
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CROUT = $FD8E
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PRBYTE = $FDDA
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PRHEX = $FDE3
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COUT = $FDED
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PRERR = $FF2D
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PB0 = $C061 ; Paddle 0 PushButton: HIGH/ON if > 127, LOW/OFF if < 128.
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start:
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lda #$09 ; We'll be watching for 8 bits plus one stop bit
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sta bits
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clc
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jsr pb0_recv ; Pull a byte from PB0
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bcs printit ; Carry set means we got a '1' stop bit, so we're good
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jsr CROUT
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jsr PRERR ; Else we got a framing error
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printit:
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ora #$80
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jsr COUT ; PRBYTE
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lda $25
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cmp #$17
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bne start
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lda #$00
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sta $25
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beq start
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done: rts
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pb0_recv:
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; State is unknown
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poll_for_1:
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; sample state
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lda PB0
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bpl poll_for_1 ; if not negative, branch to wait_for_1
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; State is now 1
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poll_for_0:
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; sample state
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lda PB0
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bmi poll_for_0 ; if negative, branch to wait_for_0
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; State just became 0 (start bit)
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; Wait 1.5 bit times (104.2 + 52.1 = 156.3us at 9600 baud) to get into the middle of the first bit
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; Approximately 152.8 ($99) CPU cycles
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; When falling through to here, the above branch was not taken - consuming 2 cycles to get here
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ldx #$14 ; 2 loop count
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: nop ; 2 \
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dex ; 2 |-- 7 * loop count
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bne :- ; 3 / final exit of the loop adds 2, branch not taken
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; $90 cycles to get here; need to burn 7 more
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beq :+ ; 3
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: nop ; 2
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nop ; 2
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; $97 cycles to get here; save 2 for upcoming clc
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pull_byte:
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; We now have one bit time (104.2us at 9600 baud) to process this bit
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; Approximately 106.6 ($6B) CPU cycles
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clc ; 2
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lda PB0 ; 4
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bmi :+ ; 2 if positive, 3 if negative
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jmp push_bit ; 3
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: sec ; 2 bit was low/negative
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push_bit: ; We now have a bit in the carry
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dec bits ; 6
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beq byte_complete ; Have we read all 8 bits? Then this bit is the stop bit; leave with carry set
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; 2 (in the case we care about, i.e. more bits to read)
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lda ring ; 4
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ror ; 2
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sta ring ; 4
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; $1C/$1D cycles to get here (since center of bit time)
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; We are now done with processing that bit; we need to cool our heels for the rest ($6B - $1C = $4F) of the
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; bit time in order to get into the middle of the next bit
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ldx #$0A ; 2 loop count
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: nop ; 2 \
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dex ; 2 |-- 7 * loop count
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bne :- ; 3 / final exit of the loop adds 2, branch not taken
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; $48 cycles to get here
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nop ; 2
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nop ; 2
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jmp pull_byte ; 3 Loop around for another bit - we burned $4F cycles
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; $6B
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byte_complete:
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; Carry now holds stop bit (clear/0 indicates framing error, because we end with set/1)
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lda ring ; Exit with the assembled byte in A
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rts
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pb_state: .byte $00
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ring: .byte $55
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bits: .byte $00
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