105 lines
3.7 KiB
NASM
105 lines
3.7 KiB
NASM
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; Tiger Learning Computer Joystick serial bitbanger (using a pushbutton input in our case)
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;
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; Custom serial-to-joystick cable is required. RS-232 settings are 9600 bps,
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; no parity, 8 data bits, 1 stop bit; 1ms pacing seems to be required.
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;
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; CPU cycle counting must be done to meet bit-time requirements on the wire.
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; Bit time is defined as (1 / baud) seconds, or (1000000 / baud) microseconds.
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; So at 9600 baud, we get a bit time 0.000104166 seconds, or 104.166 microseconds.
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; With a 6502 CPU running at about 1MHz, each CPU clock cycle is about 1.023
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; microseconds long.
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;
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.org $300
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; Some system constants
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WAIT = $FCA8
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CROUT = $FD8E
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PRBYTE = $FDDA
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PRHEX = $FDE3
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COUT = $FDED
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PRERR = $FF2D
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PB0 = $C061 ; Paddle 0 PushButton: HIGH/ON if > 127, LOW/OFF if < 128.
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start:
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jsr pb0_recv ; Pull a byte from PB0
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bcs printit ; Carry set means we got a '1' stop bit, so we're good
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jsr CROUT
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jsr PRERR ; Else we got a framing error
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jsr CROUT
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jmp start
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printit:
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ora #$80
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jsr COUT
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lda $25
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cmp #$17
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bne start
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lda #$00
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sta $25
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beq start
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done: rts
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pb0_recv:
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; State is currently unknown
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lda #$09 ; We'll be watching for 8 bits plus one stop bit
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sta bits
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clc
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poll_for_1:
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; Sample PB0's state
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lda PB0
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bpl poll_for_1 ; if not negative, branch to poll_for_1
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; State is now 1
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poll_for_0:
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; Sample PB0's state
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lda PB0
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bmi poll_for_0 ; if negative, branch to poll_for_0
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; State just became 0 (start bit) sometime in the last 4 or so clock cycles
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; Wait 1.5 bit times (104.2 + 52.1 = 156.3us at 9600 bps) to get into the middle of the first bit
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; Approximately 152.8 ($99) CPU cycles
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; When falling through to here, the above branch was not taken - consuming 2 cycles to get here
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ldx #$1D ; 2 loop count
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: dex ; 2 \ = 5 * loop count - 1
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bne :- ; 3 / final exit of the loop only adds 2, branch not taken
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; $94 cycles to get here
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bit $00 ; 3 don't care about results
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; $97 cycles to get here; final 2 will be consumed by clc below
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pull_byte:
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; We now have one bit time (104.2us at 9600 bps) to process this bit
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; Approximately 101.8 ($66) CPU cycles
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clc ; 2
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lda PB0 ; 4
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bmi :+ ; 2 if positive, 3 if negative
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jmp push_bit ; 3
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: sec ; 2 bit was low/negative
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push_bit: ; We now have a bit in the carry
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dec bits ; 6
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beq byte_complete ; Have we read all 8 bits? Then this bit is the stop bit; leave with carry set
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; 2 (in the case we care about, i.e. more bits to read)
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lda ring ; 4
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ror ; 2
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sta ring ; 4
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; $1D cycles to get here (since center of bit time)
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; We are now done with processing that bit; we need to cool our heels for the rest ($66 - $1D = $49) of the
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; bit time in order to get into the middle of the next bit
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ldx #$0E ; 2 loop count
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: dex ; 2 \ = 5 * loop count - 1
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bne :- ; 3 / final exit of the loop only adds 2, branch not taken
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; $47 cycles to get here
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jmp pull_byte ; 3 Loop around for another bit - we actually burn $4A cycles
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; $67
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byte_complete:
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; Carry now holds stop bit (clear/0 indicates framing error, because we end with set/1)
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lda ring ; Exit with the assembled byte in A
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rts
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ring: .byte $55
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bits: .byte $00
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