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enable IIc VBL
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@ -22,6 +22,9 @@ WaitForVBL
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+LDADDR WaitForVBL_iie
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bne +
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@iic
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sta $C07F ; enable access to VBL register
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sta $C05B ; enable VBL polling
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sta $C07E ; disable access to VBL register
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+LDADDR WaitForVBL_iic
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bne +
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@nop
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@ -50,5 +53,7 @@ WaitForVBL_iie ; IIe/IIgs have a relatively sane VBL
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rts
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WaitForVBL_iic ; IIc is special
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; TODO
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- bit $c019
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bpl -
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bit $c070 ;$c019 bit 7 is sticky, reset it
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rts
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