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shave 61381 cycles from all precomputed 2-bit HGR transitions (~4% faster)
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9bb4524402
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@ -1,20 +1,9 @@
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;license:MIT
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;license:MIT
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;(c) 2019 by 4am
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;(c) 2019-2020 by 4am
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;
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;
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mirror_src1 = $E8 ; word
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mirror_dest1 = $EA ; word
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mirror_src2 = $EC ; word
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mirror_dest2 = $EE ; word
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src1 = $F0 ; word
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dest1 = $F2 ; word
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src2 = $F4 ; word
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dest2 = $F6 ; word
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reverse_input = $FC ; word
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input = $FE ; word
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copymasks = $0200 ; $100 bytes but sparse, index is 0..4 but in high 3 bits, so $00, $20, $40, $60, $80
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copymasks = $0200 ; $100 bytes but sparse, index is 0..4 but in high 3 bits, so $00, $20, $40, $60, $80
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mirror_copymasks = $0201
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mirror_copymasks = $0201
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hgrlo = $0300 ; $C0 bytes
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hgrlo = $0301 ; $C0 bytes
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hgrlomirror = $BD40 ; $C0 bytes
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hgrlomirror = $BD40 ; $C0 bytes
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mirror_cols = $BE00 ; $28 bytes
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mirror_cols = $BE00 ; $28 bytes
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hgr1hi = $BE40 ; $C0 bytes
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hgr1hi = $BE40 ; $C0 bytes
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@ -71,19 +60,19 @@ hgr1himirror = $BF40 ; $C0 bytes
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!macro ROW_X_TO_2BIT_BASE_ADDRESSES {
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!macro ROW_X_TO_2BIT_BASE_ADDRESSES {
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; X = $01..$C0, mapping to row 0..191
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; X = $01..$C0, mapping to row 0..191
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lda hgrlo-1, x
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lda hgrlo-1, x
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sta dest1
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sta <dest1
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sta src1
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sta <src1
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lda hgr1hi-1, x
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lda hgr1hi-1, x
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sta dest1+1
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sta <dest1+1
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eor #$60
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eor #$60
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sta src1+1
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sta <src1+1
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lda hgrlo, x
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lda hgrlo, x
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sta dest2
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sta <dest2
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sta src2
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sta <src2
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lda hgr1hi, x
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lda hgr1hi, x
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sta dest2+1
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sta <dest2+1
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eor #$60
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eor #$60
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sta src2+1
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sta <src2+1
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}
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}
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!macro HIGH_3_LOW_5 .input {
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!macro HIGH_3_LOW_5 .input {
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@ -93,39 +82,51 @@ hgr1himirror = $BF40 ; $C0 bytes
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tay
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tay
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}
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}
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!macro INC_INPUT_AND_LOOP .loop {
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inc input
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beq +
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jmp .loop
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+ bit $c000
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bmi +
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inc input+1
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jmp .loop
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+ rts
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}
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!macro FX_PRECOMPUTED_2BIT .coords {
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!macro FX_PRECOMPUTED_2BIT .coords {
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+BUILD_HGR_LOOKUP_TABLES hgrlo, hgr1hi
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+BUILD_HGR_LOOKUP_TABLES hgrlo, hgr1hi
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+BUILD_MIRROR_COLS mirror_cols
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+BUILD_MIRROR_COLS mirror_cols
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+BUILD_SPARSE_BITMASKS_2BIT copymasks, mirror_copymasks
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+BUILD_SPARSE_BITMASKS_2BIT copymasks, mirror_copymasks
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ldx #(end-start) ; copy InputLoop code to zero page
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- lda start-1, x
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sta $FF, x
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dex
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bne -
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+LDADDR .coords
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+LDADDR .coords
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+ST16 input
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sta <input
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jmp InputLoop
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sty <input+1
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lda #0
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pha
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pha
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start
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!pseudopc 0 {
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Exit2Bit rts
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Exit2Bit rts
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InputLoop
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InputLoop
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ldy #0
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ldy #0
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lda (input),y ; first value: HGR row + 1
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input=*+1
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lda $FDFD, y ; first value: HGR row + 1
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beq Exit2Bit ; if 0 then we're done
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beq Exit2Bit ; if 0 then we're done
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tax
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tax
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+ROW_X_TO_2BIT_BASE_ADDRESSES
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+ROW_X_TO_2BIT_BASE_ADDRESSES
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inc input
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inc <input
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lda (input),y
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lda (<input), y
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+HIGH_3_LOW_5 input
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+HIGH_3_LOW_5 input
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; main 2x2 block in left half
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; main 2x2 block in left half
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+COPY_BIT src1, dest1, copymasks
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src1=*+1
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+COPY_BIT src2, dest2, copymasks
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lda $FDFD, y
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eor (<dest1), y
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and copymasks, x
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eor (<dest1), y
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dest1=*+1
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sta $FDFD, y
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src2=*+1
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lda $FDFD, y
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eor (<dest2), y
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and copymasks, x
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eor (<dest2), y
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dest2=*+1
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sta $FDFD, y
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; corresponding 2x2 block in right half (same row, opposite column)
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; corresponding 2x2 block in right half (same row, opposite column)
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lda mirror_cols, y
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lda mirror_cols, y
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@ -133,8 +134,14 @@ InputLoop
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+COPY_BIT src1, dest1, mirror_copymasks
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+COPY_BIT src1, dest1, mirror_copymasks
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+COPY_BIT src2, dest2, mirror_copymasks
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+COPY_BIT src2, dest2, mirror_copymasks
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+INC_INPUT_AND_LOOP InputLoop
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inc <input
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rts
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bne InputLoop
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bit $c000
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bmi Exit2Bit
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inc <input+1
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bne InputLoop ; always branches
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}
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end
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!if * and 1 {
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!if * and 1 {
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!byte 0 ;align 2 but avoids the fake allocation bug if it was aligned already
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!byte 0 ;align 2 but avoids the fake allocation bug if it was aligned already
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}
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}
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