commit 1ee0b6e2dc20eb2575411a221516c7f6cc705bb5 Author: sorgelig Date: Sat Nov 4 21:21:27 2017 +0800 Initial port. diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..93fd271 --- /dev/null +++ b/.gitignore @@ -0,0 +1,37 @@ +db +greybox_tmp +incremental_db +output_files +simulation +hc_output +scaler +hps_isw_handoff +vip +*_sim +.qsys_edit +PLLJ_PLLSPE_INFO.txt +*.bak +*.orig +*.rej +*.qdf +*.rpt +*.smsg +*.summary +*.done +*.jdi +*.pin +*.sof +*.qws +*.ppf +*.ddb +build_id.v +c5_pin_model_dump.txt +*.sopcinfo +*.csv +*.f +*.cmp +*.sip +*.spd +*.bsf +*~ +*.xml diff --git a/Apple-II-lite.qsf b/Apple-II-lite.qsf new file mode 100644 index 0000000..7399446 --- /dev/null +++ b/Apple-II-lite.qsf @@ -0,0 +1,378 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition +# Date created = 01:53:32 April 20, 2017 +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name VERILOG_MACRO "LITE=1" + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEBA6U23I7 +set_global_assignment -name TOP_LEVEL_ENTITY sys_top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION "17.0.1 Standard Edition" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 + +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "FAST FIT" +set_global_assignment -name OPTIMIZATION_MODE BALANCED +set_global_assignment -name SEED 1 + +#============================================================ +# ADC +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO +set_location_assignment PIN_U9 -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCK +set_location_assignment PIN_AC4 -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO + +#============================================================ +# ARDUINO +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_location_assignment PIN_AG9 -to ARDUINO_IO[3] +set_location_assignment PIN_U14 -to ARDUINO_IO[4] +set_location_assignment PIN_U13 -to ARDUINO_IO[5] +set_location_assignment PIN_AG8 -to ARDUINO_IO[6] +set_location_assignment PIN_AH8 -to ARDUINO_IO[7] +set_location_assignment PIN_AF17 -to ARDUINO_IO[8] +set_location_assignment PIN_AE15 -to ARDUINO_IO[9] +set_location_assignment PIN_AF15 -to ARDUINO_IO[10] +set_location_assignment PIN_AG16 -to ARDUINO_IO[11] +set_location_assignment PIN_AH11 -to ARDUINO_IO[12] +set_location_assignment PIN_AH12 -to ARDUINO_IO[13] +set_location_assignment PIN_AH9 -to ARDUINO_IO[14] +set_location_assignment PIN_AG11 -to ARDUINO_IO[15] + +#============================================================ +# SDIO +#============================================================ +set_location_assignment PIN_AF25 -to SDIO_DAT[0] +set_location_assignment PIN_AF23 -to SDIO_DAT[1] +set_location_assignment PIN_AD26 -to SDIO_DAT[2] +set_location_assignment PIN_AF28 -to SDIO_DAT[3] +set_location_assignment PIN_AF27 -to SDIO_CMD +set_location_assignment PIN_AH26 -to SDIO_CLK +set_location_assignment PIN_AH7 -to SDIO_CD + +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_* + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_* +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD + +#============================================================ +# VGA +#============================================================ +set_location_assignment PIN_AE17 -to VGA_R[0] +set_location_assignment PIN_AE20 -to VGA_R[1] +set_location_assignment PIN_AF20 -to VGA_R[2] +set_location_assignment PIN_AH18 -to VGA_R[3] +set_location_assignment PIN_AH19 -to VGA_R[4] +set_location_assignment PIN_AF21 -to VGA_R[5] + +set_location_assignment PIN_AE19 -to VGA_G[0] +set_location_assignment PIN_AG15 -to VGA_G[1] +set_location_assignment PIN_AF18 -to VGA_G[2] +set_location_assignment PIN_AG18 -to VGA_G[3] +set_location_assignment PIN_AG19 -to VGA_G[4] +set_location_assignment PIN_AG20 -to VGA_G[5] + +set_location_assignment PIN_AG21 -to VGA_B[0] +set_location_assignment PIN_AA20 -to VGA_B[1] +set_location_assignment PIN_AE22 -to VGA_B[2] +set_location_assignment PIN_AF22 -to VGA_B[3] +set_location_assignment PIN_AH23 -to VGA_B[4] +set_location_assignment PIN_AH21 -to VGA_B[5] + +set_location_assignment PIN_AH22 -to VGA_HS +set_location_assignment PIN_AG24 -to VGA_VS + +set_location_assignment PIN_AH27 -to VGA_EN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_* + +#============================================================ +# AUDIO +#============================================================ +set_location_assignment PIN_AC24 -to AUDIO_L +set_location_assignment PIN_AE25 -to AUDIO_R +set_location_assignment PIN_AG26 -to AUDIO_SPDIF +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_* +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_* + +#============================================================ +# SDRAM +#============================================================ +set_location_assignment PIN_Y11 -to SDRAM_A[0] +set_location_assignment PIN_AA26 -to SDRAM_A[1] +set_location_assignment PIN_AA13 -to SDRAM_A[2] +set_location_assignment PIN_AA11 -to SDRAM_A[3] +set_location_assignment PIN_W11 -to SDRAM_A[4] +set_location_assignment PIN_Y19 -to SDRAM_A[5] +set_location_assignment PIN_AB23 -to SDRAM_A[6] +set_location_assignment PIN_AC23 -to SDRAM_A[7] +set_location_assignment PIN_AC22 -to SDRAM_A[8] +set_location_assignment PIN_C12 -to SDRAM_A[9] +set_location_assignment PIN_AB26 -to SDRAM_A[10] +set_location_assignment PIN_AD17 -to SDRAM_A[11] +set_location_assignment PIN_D12 -to SDRAM_A[12] +set_location_assignment PIN_Y17 -to SDRAM_BA[0] +set_location_assignment PIN_AB25 -to SDRAM_BA[1] + +set_location_assignment PIN_E8 -to SDRAM_DQ[0] +set_location_assignment PIN_V12 -to SDRAM_DQ[1] +set_location_assignment PIN_D11 -to SDRAM_DQ[2] +set_location_assignment PIN_W12 -to SDRAM_DQ[3] +set_location_assignment PIN_AH13 -to SDRAM_DQ[4] +set_location_assignment PIN_D8 -to SDRAM_DQ[5] +set_location_assignment PIN_AH14 -to SDRAM_DQ[6] +set_location_assignment PIN_AF7 -to SDRAM_DQ[7] +set_location_assignment PIN_AE24 -to SDRAM_DQ[8] +set_location_assignment PIN_AD23 -to SDRAM_DQ[9] +set_location_assignment PIN_AE6 -to SDRAM_DQ[10] +set_location_assignment PIN_AE23 -to SDRAM_DQ[11] +set_location_assignment PIN_AG14 -to SDRAM_DQ[12] +set_location_assignment PIN_AD5 -to SDRAM_DQ[13] +set_location_assignment PIN_AF4 -to SDRAM_DQ[14] +set_location_assignment PIN_AH3 -to SDRAM_DQ[15] +set_location_assignment PIN_AG13 -to SDRAM_DQML +set_location_assignment PIN_AF13 -to SDRAM_DQMH + +set_location_assignment PIN_AD20 -to SDRAM_CLK +set_location_assignment PIN_AG10 -to SDRAM_CKE + +set_location_assignment PIN_AA19 -to SDRAM_nWE +set_location_assignment PIN_AA18 -to SDRAM_nCAS +set_location_assignment PIN_Y18 -to SDRAM_nCS +set_location_assignment PIN_W14 -to SDRAM_nRAS + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_* +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n* +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_* + +#============================================================ +# I/O +#============================================================ +set_location_assignment PIN_Y15 -to LED_USER +set_location_assignment PIN_AA15 -to LED_HDD +set_location_assignment PIN_AG28 -to LED_POWER + +set_location_assignment PIN_AH24 -to BTN_USER +set_location_assignment PIN_AG25 -to BTN_OSD +set_location_assignment PIN_AG23 -to BTN_RESET + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_* +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_* + +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 +set_location_assignment PIN_V11 -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 + +#============================================================ +# HDMI +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS +set_location_assignment PIN_U10 -to HDMI_I2C_SCL +set_location_assignment PIN_AA4 -to HDMI_I2C_SDA +set_location_assignment PIN_T13 -to HDMI_I2S +set_location_assignment PIN_T11 -to HDMI_LRCLK +set_location_assignment PIN_U11 -to HDMI_MCLK +set_location_assignment PIN_T12 -to HDMI_SCLK +set_location_assignment PIN_AG5 -to HDMI_TX_CLK +set_location_assignment PIN_AD19 -to HDMI_TX_DE +set_location_assignment PIN_AD12 -to HDMI_TX_D[0] +set_location_assignment PIN_AE12 -to HDMI_TX_D[1] +set_location_assignment PIN_W8 -to HDMI_TX_D[2] +set_location_assignment PIN_Y8 -to HDMI_TX_D[3] +set_location_assignment PIN_AD11 -to HDMI_TX_D[4] +set_location_assignment PIN_AD10 -to HDMI_TX_D[5] +set_location_assignment PIN_AE11 -to HDMI_TX_D[6] +set_location_assignment PIN_Y5 -to HDMI_TX_D[7] +set_location_assignment PIN_AF10 -to HDMI_TX_D[8] +set_location_assignment PIN_Y4 -to HDMI_TX_D[9] +set_location_assignment PIN_AE9 -to HDMI_TX_D[10] +set_location_assignment PIN_AB4 -to HDMI_TX_D[11] +set_location_assignment PIN_AE7 -to HDMI_TX_D[12] +set_location_assignment PIN_AF6 -to HDMI_TX_D[13] +set_location_assignment PIN_AF8 -to HDMI_TX_D[14] +set_location_assignment PIN_AF5 -to HDMI_TX_D[15] +set_location_assignment PIN_AE4 -to HDMI_TX_D[16] +set_location_assignment PIN_AH2 -to HDMI_TX_D[17] +set_location_assignment PIN_AH4 -to HDMI_TX_D[18] +set_location_assignment PIN_AH5 -to HDMI_TX_D[19] +set_location_assignment PIN_AH6 -to HDMI_TX_D[20] +set_location_assignment PIN_AG6 -to HDMI_TX_D[21] +set_location_assignment PIN_AF9 -to HDMI_TX_D[22] +set_location_assignment PIN_AE8 -to HDMI_TX_D[23] +set_location_assignment PIN_T8 -to HDMI_TX_HS +set_location_assignment PIN_AF11 -to HDMI_TX_INT +set_location_assignment PIN_V13 -to HDMI_TX_VS + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_location_assignment PIN_AH17 -to KEY[0] +set_location_assignment PIN_AH16 -to KEY[1] + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_AA23 -to LED[7] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_location_assignment PIN_Y24 -to SW[0] +set_location_assignment PIN_W24 -to SW[1] +set_location_assignment PIN_W21 -to SW[2] +set_location_assignment PIN_W20 -to SW[3] + +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" + +set_global_assignment -name CDF_FILE jtag_lite.cdf +set_global_assignment -name QIP_FILE sys/sys.qip +set_global_assignment -name QIP_FILE sys/sysmem.qip +set_global_assignment -name VHDL_FILE mockingboard/YM2149_volmix.vhd +set_global_assignment -name VHDL_FILE mockingboard/vol_table_array.vhd +set_global_assignment -name VHDL_FILE mockingboard/mockingboard.vhd +set_global_assignment -name VHDL_FILE mockingboard/m6522.vhd +set_global_assignment -name VERILOG_FILE ramcard.v +set_global_assignment -name VHDL_FILE spram.vhd +set_global_assignment -name VHDL_FILE keyboard.vhd +set_global_assignment -name VHDL_FILE timing_generator.vhd +set_global_assignment -name VHDL_FILE character_rom.vhd +set_global_assignment -name VHDL_FILE video_generator.vhd +set_global_assignment -name VHDL_FILE cpu6502.vhd +set_global_assignment -name VHDL_FILE apple2.vhd +set_global_assignment -name VHDL_FILE disk_ii.vhd +set_global_assignment -name VHDL_FILE disk_ii_rom.vhd +set_global_assignment -name VHDL_FILE vga_controller.vhd +set_global_assignment -name VHDL_FILE PS2_Ctrl.vhd +set_global_assignment -name VHDL_FILE roms.vhd +set_global_assignment -name VHDL_FILE apple2_top.vhd +set_global_assignment -name SYSTEMVERILOG_FILE Apple-II.sv +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Apple-II-lite.srf b/Apple-II-lite.srf new file mode 100644 index 0000000..fc3d1e3 --- /dev/null +++ b/Apple-II-lite.srf @@ -0,0 +1,17 @@ +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Synthesized away node \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|outclk_wire\[2\]\"" { } { } 0 14320 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[1\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Ignored locations or region assignments to the following nodes" { } { } 0 15705 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[2\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." { } { } 0 0 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(129): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(134): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21074 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "sysmem_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Apple-II.qpf b/Apple-II.qpf new file mode 100644 index 0000000..dc40831 --- /dev/null +++ b/Apple-II.qpf @@ -0,0 +1,32 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition +# Date created = 04:04:47 October 16, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "17.0" +DATE = "04:04:47 October 16, 2017" + +# Revisions + +PROJECT_REVISION = "Apple-II" +PROJECT_REVISION = "Apple-II-lite" diff --git a/Apple-II.qsf b/Apple-II.qsf new file mode 100644 index 0000000..b5be6af --- /dev/null +++ b/Apple-II.qsf @@ -0,0 +1,376 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Intel and sold by Intel or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition +# Date created = 01:53:32 April 20, 2017 +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CSEBA6U23I7 +set_global_assignment -name TOP_LEVEL_ENTITY sys_top +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2 +set_global_assignment -name LAST_QUARTUS_VERSION "17.0.1 Standard Edition" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017" +set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 + +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name OPTIMIZATION_MODE BALANCED +set_global_assignment -name SEED 1 + +#============================================================ +# ADC +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CONVST +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SDO +set_location_assignment PIN_U9 -to ADC_CONVST +set_location_assignment PIN_V10 -to ADC_SCK +set_location_assignment PIN_AC4 -to ADC_SDI +set_location_assignment PIN_AD4 -to ADC_SDO + +#============================================================ +# ARDUINO +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_location_assignment PIN_AG9 -to ARDUINO_IO[3] +set_location_assignment PIN_U14 -to ARDUINO_IO[4] +set_location_assignment PIN_U13 -to ARDUINO_IO[5] +set_location_assignment PIN_AG8 -to ARDUINO_IO[6] +set_location_assignment PIN_AH8 -to ARDUINO_IO[7] +set_location_assignment PIN_AF17 -to ARDUINO_IO[8] +set_location_assignment PIN_AE15 -to ARDUINO_IO[9] +set_location_assignment PIN_AF15 -to ARDUINO_IO[10] +set_location_assignment PIN_AG16 -to ARDUINO_IO[11] +set_location_assignment PIN_AH11 -to ARDUINO_IO[12] +set_location_assignment PIN_AH12 -to ARDUINO_IO[13] +set_location_assignment PIN_AH9 -to ARDUINO_IO[14] +set_location_assignment PIN_AG11 -to ARDUINO_IO[15] + +#============================================================ +# SDIO +#============================================================ +set_location_assignment PIN_AF25 -to SDIO_DAT[0] +set_location_assignment PIN_AF23 -to SDIO_DAT[1] +set_location_assignment PIN_AD26 -to SDIO_DAT[2] +set_location_assignment PIN_AF28 -to SDIO_DAT[3] +set_location_assignment PIN_AF27 -to SDIO_CMD +set_location_assignment PIN_AH26 -to SDIO_CLK +set_location_assignment PIN_AH7 -to SDIO_CD + +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDIO_* + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDIO_* +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_DAT[*] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CMD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SDIO_CD + +#============================================================ +# VGA +#============================================================ +set_location_assignment PIN_AE17 -to VGA_R[0] +set_location_assignment PIN_AE20 -to VGA_R[1] +set_location_assignment PIN_AF20 -to VGA_R[2] +set_location_assignment PIN_AH18 -to VGA_R[3] +set_location_assignment PIN_AH19 -to VGA_R[4] +set_location_assignment PIN_AF21 -to VGA_R[5] + +set_location_assignment PIN_AE19 -to VGA_G[0] +set_location_assignment PIN_AG15 -to VGA_G[1] +set_location_assignment PIN_AF18 -to VGA_G[2] +set_location_assignment PIN_AG18 -to VGA_G[3] +set_location_assignment PIN_AG19 -to VGA_G[4] +set_location_assignment PIN_AG20 -to VGA_G[5] + +set_location_assignment PIN_AG21 -to VGA_B[0] +set_location_assignment PIN_AA20 -to VGA_B[1] +set_location_assignment PIN_AE22 -to VGA_B[2] +set_location_assignment PIN_AF22 -to VGA_B[3] +set_location_assignment PIN_AH23 -to VGA_B[4] +set_location_assignment PIN_AH21 -to VGA_B[5] + +set_location_assignment PIN_AH22 -to VGA_HS +set_location_assignment PIN_AG24 -to VGA_VS + +set_location_assignment PIN_AH27 -to VGA_EN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to VGA_EN + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_* +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_* + +#============================================================ +# AUDIO +#============================================================ +set_location_assignment PIN_AC24 -to AUDIO_L +set_location_assignment PIN_AE25 -to AUDIO_R +set_location_assignment PIN_AG26 -to AUDIO_SPDIF +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_* +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_* + +#============================================================ +# SDRAM +#============================================================ +set_location_assignment PIN_Y11 -to SDRAM_A[0] +set_location_assignment PIN_AA26 -to SDRAM_A[1] +set_location_assignment PIN_AA13 -to SDRAM_A[2] +set_location_assignment PIN_AA11 -to SDRAM_A[3] +set_location_assignment PIN_W11 -to SDRAM_A[4] +set_location_assignment PIN_Y19 -to SDRAM_A[5] +set_location_assignment PIN_AB23 -to SDRAM_A[6] +set_location_assignment PIN_AC23 -to SDRAM_A[7] +set_location_assignment PIN_AC22 -to SDRAM_A[8] +set_location_assignment PIN_C12 -to SDRAM_A[9] +set_location_assignment PIN_AB26 -to SDRAM_A[10] +set_location_assignment PIN_AD17 -to SDRAM_A[11] +set_location_assignment PIN_D12 -to SDRAM_A[12] +set_location_assignment PIN_Y17 -to SDRAM_BA[0] +set_location_assignment PIN_AB25 -to SDRAM_BA[1] + +set_location_assignment PIN_E8 -to SDRAM_DQ[0] +set_location_assignment PIN_V12 -to SDRAM_DQ[1] +set_location_assignment PIN_D11 -to SDRAM_DQ[2] +set_location_assignment PIN_W12 -to SDRAM_DQ[3] +set_location_assignment PIN_AH13 -to SDRAM_DQ[4] +set_location_assignment PIN_D8 -to SDRAM_DQ[5] +set_location_assignment PIN_AH14 -to SDRAM_DQ[6] +set_location_assignment PIN_AF7 -to SDRAM_DQ[7] +set_location_assignment PIN_AE24 -to SDRAM_DQ[8] +set_location_assignment PIN_AD23 -to SDRAM_DQ[9] +set_location_assignment PIN_AE6 -to SDRAM_DQ[10] +set_location_assignment PIN_AE23 -to SDRAM_DQ[11] +set_location_assignment PIN_AG14 -to SDRAM_DQ[12] +set_location_assignment PIN_AD5 -to SDRAM_DQ[13] +set_location_assignment PIN_AF4 -to SDRAM_DQ[14] +set_location_assignment PIN_AH3 -to SDRAM_DQ[15] +set_location_assignment PIN_AG13 -to SDRAM_DQML +set_location_assignment PIN_AF13 -to SDRAM_DQMH + +set_location_assignment PIN_AD20 -to SDRAM_CLK +set_location_assignment PIN_AG10 -to SDRAM_CKE + +set_location_assignment PIN_AA19 -to SDRAM_nWE +set_location_assignment PIN_AA18 -to SDRAM_nCAS +set_location_assignment PIN_Y18 -to SDRAM_nCS +set_location_assignment PIN_W14 -to SDRAM_nRAS + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_* +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQM* +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_n* +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*] +set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF -to *|SDRAM_* + +#============================================================ +# I/O +#============================================================ +set_location_assignment PIN_Y15 -to LED_USER +set_location_assignment PIN_AA15 -to LED_HDD +set_location_assignment PIN_AG28 -to LED_POWER + +set_location_assignment PIN_AH24 -to BTN_USER +set_location_assignment PIN_AG25 -to BTN_OSD +set_location_assignment PIN_AG23 -to BTN_RESET + +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED_* +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to BTN_* +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to BTN_* + +#============================================================ +# CLOCK +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50 +set_location_assignment PIN_V11 -to FPGA_CLK1_50 +set_location_assignment PIN_Y13 -to FPGA_CLK2_50 +set_location_assignment PIN_E11 -to FPGA_CLK3_50 + +#============================================================ +# HDMI +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SCL +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2C_SDA +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_I2S +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_LRCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_MCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_DE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_D[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HDMI_TX_VS +set_location_assignment PIN_U10 -to HDMI_I2C_SCL +set_location_assignment PIN_AA4 -to HDMI_I2C_SDA +set_location_assignment PIN_T13 -to HDMI_I2S +set_location_assignment PIN_T11 -to HDMI_LRCLK +set_location_assignment PIN_U11 -to HDMI_MCLK +set_location_assignment PIN_T12 -to HDMI_SCLK +set_location_assignment PIN_AG5 -to HDMI_TX_CLK +set_location_assignment PIN_AD19 -to HDMI_TX_DE +set_location_assignment PIN_AD12 -to HDMI_TX_D[0] +set_location_assignment PIN_AE12 -to HDMI_TX_D[1] +set_location_assignment PIN_W8 -to HDMI_TX_D[2] +set_location_assignment PIN_Y8 -to HDMI_TX_D[3] +set_location_assignment PIN_AD11 -to HDMI_TX_D[4] +set_location_assignment PIN_AD10 -to HDMI_TX_D[5] +set_location_assignment PIN_AE11 -to HDMI_TX_D[6] +set_location_assignment PIN_Y5 -to HDMI_TX_D[7] +set_location_assignment PIN_AF10 -to HDMI_TX_D[8] +set_location_assignment PIN_Y4 -to HDMI_TX_D[9] +set_location_assignment PIN_AE9 -to HDMI_TX_D[10] +set_location_assignment PIN_AB4 -to HDMI_TX_D[11] +set_location_assignment PIN_AE7 -to HDMI_TX_D[12] +set_location_assignment PIN_AF6 -to HDMI_TX_D[13] +set_location_assignment PIN_AF8 -to HDMI_TX_D[14] +set_location_assignment PIN_AF5 -to HDMI_TX_D[15] +set_location_assignment PIN_AE4 -to HDMI_TX_D[16] +set_location_assignment PIN_AH2 -to HDMI_TX_D[17] +set_location_assignment PIN_AH4 -to HDMI_TX_D[18] +set_location_assignment PIN_AH5 -to HDMI_TX_D[19] +set_location_assignment PIN_AH6 -to HDMI_TX_D[20] +set_location_assignment PIN_AG6 -to HDMI_TX_D[21] +set_location_assignment PIN_AF9 -to HDMI_TX_D[22] +set_location_assignment PIN_AE8 -to HDMI_TX_D[23] +set_location_assignment PIN_T8 -to HDMI_TX_HS +set_location_assignment PIN_AF11 -to HDMI_TX_INT +set_location_assignment PIN_V13 -to HDMI_TX_VS + +#============================================================ +# KEY +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_location_assignment PIN_AH17 -to KEY[0] +set_location_assignment PIN_AH16 -to KEY[1] + +#============================================================ +# LED +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] +set_location_assignment PIN_W15 -to LED[0] +set_location_assignment PIN_AA24 -to LED[1] +set_location_assignment PIN_V16 -to LED[2] +set_location_assignment PIN_V15 -to LED[3] +set_location_assignment PIN_AF26 -to LED[4] +set_location_assignment PIN_AE26 -to LED[5] +set_location_assignment PIN_Y16 -to LED[6] +set_location_assignment PIN_AA23 -to LED[7] + +#============================================================ +# SW +#============================================================ +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_location_assignment PIN_Y24 -to SW[0] +set_location_assignment PIN_W24 -to SW[1] +set_location_assignment PIN_W21 -to SW[2] +set_location_assignment PIN_W20 -to SW[3] + +set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl" + +set_global_assignment -name CDF_FILE jtag.cdf +set_global_assignment -name QIP_FILE sys/sys.qip +set_global_assignment -name QIP_FILE sys/vip.qip +set_global_assignment -name VHDL_FILE mockingboard/YM2149_volmix.vhd +set_global_assignment -name VHDL_FILE mockingboard/vol_table_array.vhd +set_global_assignment -name VHDL_FILE mockingboard/mockingboard.vhd +set_global_assignment -name VHDL_FILE mockingboard/m6522.vhd +set_global_assignment -name VERILOG_FILE ramcard.v +set_global_assignment -name VHDL_FILE spram.vhd +set_global_assignment -name VHDL_FILE keyboard.vhd +set_global_assignment -name VHDL_FILE timing_generator.vhd +set_global_assignment -name VHDL_FILE character_rom.vhd +set_global_assignment -name VHDL_FILE video_generator.vhd +set_global_assignment -name VHDL_FILE cpu6502.vhd +set_global_assignment -name VHDL_FILE apple2.vhd +set_global_assignment -name VHDL_FILE disk_ii.vhd +set_global_assignment -name VHDL_FILE disk_ii_rom.vhd +set_global_assignment -name VHDL_FILE vga_controller.vhd +set_global_assignment -name VHDL_FILE PS2_Ctrl.vhd +set_global_assignment -name VHDL_FILE roms.vhd +set_global_assignment -name VHDL_FILE apple2_top.vhd +set_global_assignment -name SYSTEMVERILOG_FILE "Apple-II.sv" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Apple-II.srf b/Apple-II.srf new file mode 100644 index 0000000..04c03cc --- /dev/null +++ b/Apple-II.srf @@ -0,0 +1,51 @@ +{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} +{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""} diff --git a/Apple-II.sv b/Apple-II.sv new file mode 100644 index 0000000..35f43a6 --- /dev/null +++ b/Apple-II.sv @@ -0,0 +1,307 @@ +//============================================================================ +// Apple II+ +// +// Port to MiSTer +// Copyright (C) 2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +//============================================================================ + +module emu +( + //Master input clock + input CLK_50M, + + //Async reset from top-level module. + //Can be used as initial reset. + input RESET, + + //Must be passed to hps_io module + inout [43:0] HPS_BUS, + + //Base video clock. Usually equals to CLK_SYS. + output CLK_VIDEO, + + //Multiple resolutions are supported using different CE_PIXEL rates. + //Must be based on CLK_VIDEO + output CE_PIXEL, + + //Video aspect ratio for HDMI. Most retro systems have ratio 4:3. + output [7:0] VIDEO_ARX, + output [7:0] VIDEO_ARY, + + output [7:0] VGA_R, + output [7:0] VGA_G, + output [7:0] VGA_B, + output VGA_HS, + output VGA_VS, + output VGA_DE, // = ~(VBlank | HBlank) + + output LED_USER, // 1 - ON, 0 - OFF. + + // b[1]: 0 - LED status is system status ORed with b[0] + // 1 - LED status is controled solely by b[0] + // hint: supply 2'b00 to let the system control the LED. + output [1:0] LED_POWER, + output [1:0] LED_DISK, + + output [15:0] AUDIO_L, + output [15:0] AUDIO_R, + output AUDIO_S, // 1 - signed audio samples, 0 - unsigned + input TAPE_IN, + + // SD-SPI + output SD_SCK, + output SD_MOSI, + input SD_MISO, + output SD_CS, + + //High latency DDR3 RAM interface + //Use for non-critical time purposes + output DDRAM_CLK, + input DDRAM_BUSY, + output [7:0] DDRAM_BURSTCNT, + output [28:0] DDRAM_ADDR, + input [63:0] DDRAM_DOUT, + input DDRAM_DOUT_READY, + output DDRAM_RD, + output [63:0] DDRAM_DIN, + output [7:0] DDRAM_BE, + output DDRAM_WE, + + //SDRAM interface with lower latency + output SDRAM_CLK, + output SDRAM_CKE, + output [12:0] SDRAM_A, + output [1:0] SDRAM_BA, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nCS, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nWE +); + +assign {SD_SCK, SD_MOSI, SD_CS} = 'Z; +assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z; +assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0; + +assign LED_USER = led; +assign LED_DISK = 0; +assign LED_POWER = 0; + +assign VIDEO_ARX = status[1] ? 8'd16 : 8'd4; +assign VIDEO_ARY = status[1] ? 8'd9 : 8'd3; + +`include "build_id.v" +parameter CONF_STR = { + "Apple-II;;", + "-;", + "S,NIB;", + "-;", + "O1,Aspect ratio,4:3,16:9;", + "O23,Display,Color,B&W,Green,Amber;", + "-;", + "O4,Mocking board,Yes,No;", + "-;", + "T6,Reset;", + "J,Fire 1,Fire 2;", + "V,v1.01.",`BUILD_DATE +}; + +///////////////// CLOCKS //////////////////////// + +wire clk_ram, clk_sys, clk_fdd, clk_vid; +wire pll_locked; + +pll pll +( + .refclk(CLK_50M), + .rst(0), + .outclk_0(clk_vid), + .outclk_1(clk_sys), + .locked(pll_locked) +); + +///////////////// HPS /////////////////////////// + +wire [31:0] status; +wire [1:0] buttons; + +wire [15:0] joystick_0, joystick_1; +wire [15:0] joystick_a0, joystick_a1; + +wire [5:0] joy = (joystick_0[5:0] | joystick_1[5:0]) & {2'b11, {4{~joya_en}}}; +wire [15:0] joya = joystick_a0 ? joystick_a0 : joystick_a1; +wire joya_en = |joya; + + +wire ps2_kbd_clk_out; +wire ps2_kbd_data_out; + +reg [31:0] sd_lba; +reg sd_rd; +wire sd_ack; +wire [8:0] sd_buff_addr; +wire [7:0] sd_buff_dout; +wire sd_buff_wr; +wire img_mounted; +wire [63:0] img_size; + +hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io +( + .clk_sys(clk_sys), + .HPS_BUS(HPS_BUS), + + .conf_str(CONF_STR), + + .buttons(buttons), + .status(status), + + .sd_lba(sd_lba), + .sd_rd(sd_rd), + .sd_wr(0), + .sd_ack(sd_ack), + .sd_buff_addr(sd_buff_addr), + .sd_buff_dout(sd_buff_dout), + .sd_buff_din(0), + .sd_buff_wr(sd_buff_wr), + .img_mounted(img_mounted), + .img_size(img_size), + + .ioctl_wait(0), + + .ps2_kbd_clk_out(ps2_kbd_clk_out), + .ps2_kbd_data_out(ps2_kbd_data_out), + + .joystick_0(joystick_0), + .joystick_1(joystick_1), + .joystick_analog_0(joystick_a0), + .joystick_analog_1(joystick_a1) +); + +///////////////// RESET ///////////////////////// + +wire reset = RESET | status[0] | buttons[1] | status[6]; + +/////////////////////////////////////////////////// + +wire [7:0] audio_l, audio_r; +wire speaker; + +assign AUDIO_L = {1'b0, audio_l, 7'd0} + {2'b0, speaker, 13'd0}; +assign AUDIO_R = {1'b0, audio_r, 7'd0} + {2'b0, speaker, 13'd0}; +assign AUDIO_S = 0; + +assign CLK_VIDEO = clk_vid; +assign CE_PIXEL = 1; + +wire led; +apple2_top apple2_top +( + .CLK_28M(clk_vid), + .CLK_14M(clk_sys), + .CPU_WAIT(cpu_wait), + + .reset_in(reset), + + .VGA_DE(VGA_DE), + .VGA_HS(VGA_HS), + .VGA_VS(VGA_VS), + .VGA_R(VGA_R), + .VGA_G(VGA_G), + .VGA_B(VGA_B), + .SCREEN_MODE(status[3:2]), + + .AUDIO_L(audio_l), + .AUDIO_R(audio_r), + .SPEAKER(speaker), + + .ps2Clk(ps2_kbd_clk_out), + .ps2Data(ps2_kbd_data_out), + + .joy(joy), + .joy_an(joya), + + .mb_enabled(~status[4]), + + + .TRACK(track), + .TRACK_RAM_ADDR({track_sec, sd_buff_addr}), + .TRACK_RAM_DI(sd_buff_dout), + .TRACK_RAM_WE(sd_buff_wr), + + .ram_addr(ram_addr), + .ram_dout(ram_dout), + .ram_din(ram_din), + .ram_we(ram_we), + + .LED(led) +); + +wire [17:0] ram_addr; +reg [7:0] ram_dout; +wire [7:0] ram_din; +wire ram_we; + +reg [7:0] ram[262144]; //om-nom-nom :) +always @(posedge clk_sys) begin + if(ram_we) begin + ram[ram_addr] <= ram_din; + ram_dout <= ram_din; + end else begin + ram_dout <= ram[ram_addr]; + end +end + +wire [5:0] track; +reg [3:0] track_sec; +reg cpu_wait = 0; + +always @(posedge clk_sys) begin + reg [2:0] state = 0; + reg [5:0] cur_track; + reg mounted = 0; + reg old_ack = 0; + + old_ack <= sd_ack; + mounted <= mounted | img_mounted; + + case(state) + 0: if((cur_track != track) || (mounted && ~img_mounted)) begin + cur_track <= track; + mounted <= 0; + if(img_size) begin + track_sec <= 0; + sd_lba <= 13 * track; + state <= 1; + sd_rd <= 1; + cpu_wait <= 1; + end + end + + 1: if(~old_ack & sd_ack) begin + if(track_sec >= 12) sd_rd <= 0; + sd_lba <= sd_lba + 1'd1; + end else if(old_ack & ~sd_ack) begin + track_sec <= track_sec + 1'd1; + if(~sd_rd) state <= 0; + cpu_wait <= 0; + end + endcase +end + +endmodule diff --git a/PS2_Ctrl.vhd b/PS2_Ctrl.vhd new file mode 100644 index 0000000..6421c75 --- /dev/null +++ b/PS2_Ctrl.vhd @@ -0,0 +1,147 @@ +-- PS2_Ctrl.vhd +-- ------------------------------------------------ +-- Simplified PS/2 Controller (kbd, mouse...) +-- ------------------------------------------------ +-- Only the Receive function is implemented ! +-- (c) ALSE. http://www.alse-fr.com + +library IEEE; +use IEEE.Std_Logic_1164.all; +use IEEE.Numeric_Std.all; + +-- -------------------------------------- + Entity PS2_Ctrl is +-- -------------------------------------- + generic (FilterSize : positive := 8); + port( Clk : in std_logic; -- System Clock + Reset : in std_logic; -- System Reset + PS2_Clk : in std_logic; -- Keyboard Clock Line + PS2_Data : in std_logic; -- Keyboard Data Line + DoRead : in std_logic; -- From outside when reading the scan code + Scan_Err : out std_logic; -- To outside : Parity or Overflow error + Scan_DAV : out std_logic; -- To outside when a scan code has arrived + Scan_Code : out unsigned(7 downto 0) -- Eight bits Data Out + ); +end PS2_Ctrl; + +-- -------------------------------------- + Architecture ALSE_RTL of PS2_Ctrl is +-- -------------------------------------- +-- (c) ALSE. http://www.alse-fr.com +-- Author : Bert Cuzeau. +-- Fully synchronous solution, same Filter on PS2_Clk. +-- Still as compact as "Plain_wrong"... +-- Possible improvement : add TIMEOUT on PS2_Clk while shifting +-- Note: PS2_Data is resynchronized though this should not be +-- necessary (qualified by Fall_Clk and does not change at that time). +-- Note the tricks to correctly interpret 'H' as '1' in RTL simulation. + + signal PS2_Datr : std_logic; + + subtype Filter_t is std_logic_vector(FilterSize-1 downto 0); + signal Filter : Filter_t; + signal Fall_Clk : std_logic; + signal Bit_Cnt : unsigned(3 downto 0); + signal Parity : std_logic; + signal Scan_DAVi : std_logic; + + signal S_Reg : unsigned(8 downto 0); + + signal PS2_Clk_f : std_logic; + + Type State_t is (Idle, Shifting); + signal State : State_t; + +begin + +Scan_DAV <= Scan_DAVi; + +-- This filters digitally the raw clock signal coming from the keyboard : +-- * Eight consecutive PS2_Clk=1 makes the filtered_clock go high +-- * Eight consecutive PS2_Clk=0 makes the filtered_clock go low +-- Implies a (FilterSize+1) x Tsys_clock delay on Fall_Clk wrt Data +-- Also in charge of the re-synchronization of PS2_Data + +process (Clk,Reset) +begin + if Reset='1' then + PS2_Datr <= '0'; + PS2_Clk_f <= '0'; + Filter <= (others=>'0'); + Fall_Clk <= '0'; + elsif rising_edge (Clk) then + PS2_Datr <= PS2_Data and PS2_Data; -- also turns 'H' into '1' + Fall_Clk <= '0'; + Filter <= (PS2_Clk and PS2_CLK) & Filter(Filter'high downto 1); + if Filter = Filter_t'(others=>'1') then + PS2_Clk_f <= '1'; + elsif Filter = Filter_t'(others=>'0') then + PS2_Clk_f <= '0'; + if PS2_Clk_f = '1' then + Fall_Clk <= '1'; + end if; + end if; + end if; +end process; + + +-- This simple State Machine reads in the Serial Data +-- coming from the PS/2 peripheral. + +process(Clk,Reset) +begin + + if Reset='1' then + State <= Idle; + Bit_Cnt <= (others => '0'); + S_Reg <= (others => '0'); + Scan_Code <= (others => '0'); + Parity <= '0'; + Scan_Davi <= '0'; + Scan_Err <= '0'; + + elsif rising_edge (Clk) then + + if DoRead='1' then + Scan_Davi <= '0'; -- note: this assgnmnt can be overriden + end if; + + case State is + + when Idle => + Parity <= '0'; + Bit_Cnt <= (others => '0'); + -- note that we dont need to clear the Shift Register + if Fall_Clk='1' and PS2_Datr='0' then -- Start bit + Scan_Err <= '0'; + State <= Shifting; + end if; + + when Shifting => + if Bit_Cnt >= 9 then + if Fall_Clk='1' then -- Stop Bit + -- Error is (wrong Parity) or (Stop='0') or Overflow + Scan_Err <= (not Parity) or (not PS2_Datr) or Scan_DAVi; + Scan_Davi <= '1'; + Scan_Code <= S_Reg(7 downto 0); + State <= Idle; + end if; + elsif Fall_Clk='1' then + Bit_Cnt <= Bit_Cnt + 1; + S_Reg <= PS2_Datr & S_Reg (S_Reg'high downto 1); -- Shift right + Parity <= Parity xor PS2_Datr; + end if; + + when others => -- never reached + State <= Idle; + + end case; + + --Scan_Err <= '0'; -- to create an on-purpose error on Scan_Err ! + + end if; + +end process; + +end ALSE_RTL; + diff --git a/README.txt b/README.txt new file mode 100644 index 0000000..d034398 --- /dev/null +++ b/README.txt @@ -0,0 +1,178 @@ +This is MiSTer port of Apple II+ from MiST. + +Bellow is readme from MiST. Functionality is identical. + +--------------------------------------------------------------------------- + +This the MiST port of a reconstruction of an 1980s-era Apple ][+ implemented in VHDL for FPGAs. +Original for the DE2: http://www1.cs.columbia.edu/~sedwards/apple2fpga/ +Port for the MiST: http://ws0.org/tag/apple2/ + +Features: +- disk loading via osd (no write support yet) +- joystick support +- scanlines +- color, amber, green and black&white monitor +- language card in slot 0 +- Saturn 128k RAM expansion in slot 5 (get the utility disks from here: http://apple2online.com/index.php?p=1_28) +- Mockingboard model A (two AY-3-8913 chips for six audio channels) in slot 4 + +On the "Apple ][" boot screen open the OSD with F12 and choose a nibblelized disk. It will boot +the disk automatically. Use dsk2nib to convert AppleII disk images to .nib images. +The disk emulation is read only. + +If you press reset (the right button on the MiST) you'll enter Applesoft with the ] prompt. +From here you have some limited commands. See: http://www.landsnail.com/a2ref.htm +If you want to boot another disk choose a .nib image via the osd and type the following: + +]PR#6 + +or + +]CALL -151 +*C600G + +The call command will enter the Monitor. Type the call a second time if the * prompt won't +show the first time. +At the Monitor you can also type 6 and then Ctrl-P followed by return. +See http://vectronicsappleworld.com/appleii/dos.html#bootdos + + +--------------------------------------------------------------------------- + Pre-MiST ReadMe for historical purpose. +--------------------------------------------------------------------------- + +This is a reconstruction of an 1980s-era Apple ][+ implemented in VHDL for +FPGAs. + +Stephen A. Edwards, sedwards@cs.columbia.edu +http://www1.cs.columbia.edu/~sedwards +------------------------------ +The current implementation uses the Altera DE2 board and takes advantage +of its off-chip SRAM, VGA DAC, SD card, audio CODEC, and PS/2 keyboard +interface. + +It was designed to be fairly easy to port: the apple2.vhd file should +be implementation-agnostic: it only assumes the external availability +of 48K of RAM and a keyboard. + +It contains a simple read-only Disk II emulator that expects +"nibblized" disk images written raw onto an SD or MMC card (i.e., it +does not use a FAT or any other type of filesystem). + +The VGA controller (not part of an original Apple) doubles each line +and interprets the Apple's NTSC-compatible color signals to produce a color +640 X 480 VGA display with non-standard dot timing. +------------------------------ +To compile under Altera's Quartus software, open the apple2fpga.qpf +project file and compile. +------------------------------ +VHDL files, in order of elaboration: + +timing_generator.vhd Timing signal generation, video counters +character_rom.vhd The beautiful 5 X 8 uppercase-only text font +video_generator.vhd Text, lores, and hires mode shift registers +main_roms.vhd D000-FFFF ROMs: Applesoft and the Monitor +cpu6502.vhd The 6502 CPU core +apple2.vhd Top-level of the Apple: mostly address decode +disk_ii_rom.vhd C600-C6FF ROM: Disk II bootstrap ROM +disk_ii.vhd Read-only Disk II emulator +vga_controller.vhd NTSC-to-VGA color interpolation, line doubler +PS2_Ctrl.vhd Low-level PS/2 keyboard interface +keyboard.vhd PS/2 keyboard-to-Apple interface +spi_controller.vhd SD/MMC card controller: reads raw tracks +i2c_controller.vhd Simple I2C bus driver; initializes the codec +wm8731_audio.vhd Controller for the Wolfson WM8731 audio codec +DE2_TOP.vhd Top-level entity for the Altera DE2 board +CLK28MPLL.vhd Altera-specific configuration for 28 MHz PLL + +Other files: + +dsk2nib.c Converts a 140K .dsk image file to the raw 228K + .nib format used by the Disk II emulator + +makenibs A shell (e.g., bash) script that assembles + collections of .dsk files into a file suitable + for directly writing onto an SD card + +rom2vhdl Script to convert raw ROM files into + synthesizable VHDL code. Used to produce main_roms.vhd + +apple2fpga.qpf Project file for Altera's Quartus +DE2_TOP.qsf Mostly pin assignments for Altera's Quartus +DE2_TOP.sof A compiled bitstream for the DE2 board: the + result of compiling all the VHDL files in + Quartus; suitable for programming if you have a + DE2 board. + +dos33master.nib Bootable disk image: Apple DOS 3.3 system master + +bios.a65 6502 assembly source for a "fake" BIOS +bios.rom Binary data for the "fake" BIOS + +Makefile Rules for creating the .zip, .vhd files, etc. +------------------------------ +Disk images + +The system expects a sequence of "nibblized" (227K) disk images on the +SD card starting at block 0. Switches on the DE2 board selects which +image appears to be in the drive; the image number is displayed in hex +on two of the seven-segment displays. + +Most Apple II disk images are in 140K .dsk files, which stores only +the disk's logical data, i.e., is not encoded. dsk2nib.c is a small C +program that expands .dsk files to .nib files. + +I used the "makenibs" script to find all the .dsk files in a tree of +directories, assemble them into an image suitable for downloading to +the SD card, and print an image number/file name cross-listing. + +To write .nib images to an SD/MMC card under Linux, I use + +dd if=dos33master.nib of=/dev/sdd + +Of course, your card may appear as something other than /dev/sdd. +------------------------------ +ROMs + +This archive does NOT include a copy of the Apple ][+'s ROMs, which +are copyright Apple Computer. Instead, it includes a very trivial +BIOS that beeps, displays a text screen, then cycles through some +lores and hires graphics patterns when keys are pressed. This should +be enough to verify the graphics, sound, and keyboard are working (but +not the disk emulator). Source for this BIOS is in the bios.a65 file, +which I assembled using the xa65 cross-assembler. + +The system requires two ROM images: a 12K image of the system roms +(memory from 0xD000 - 0xFFFF) and a 256-byte image of the Disk II +controller bootstrap ROM (memory from 0xc600 - 0xc6ff if the card is +in the usual slot 6). + +Once you obtain them, run the "rom2vhdl" script to convert the binary +files into .vhd files that hold the data. The Makefile contains rules +for doing this. +------------------------------ +Credits: + +Peter Wendrich supplied the 6502 core: + +-- cpu65xx_fast.vhdl, part of FPGA-64, is made available strictly for personal +-- educational purposes. Distributed with apple2fgpa with permission. +-- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com). +-- All rights reserved. +-- http://www.syntiac.com/fpga64.html + +The low-level PS/2 keyboard controller is from ALSE: + +-- PS2_Ctrl.vhd +-- ------------------------------------------------ +-- Simplified PS/2 Controller (kbd, mouse...) +-- ------------------------------------------------ +-- Only the Receive function is implemented ! +-- (c) ALSE. http://www.alse-fr.com + +I adapted the Apple ][ keyboard emulation from Alex Freed's FPGApple: +http://mirrow.com/FPGApple/ + + \ No newline at end of file diff --git a/apple2.vhd b/apple2.vhd new file mode 100644 index 0000000..416c7cb --- /dev/null +++ b/apple2.vhd @@ -0,0 +1,358 @@ +------------------------------------------------------------------------------- +-- +-- Top level of an Apple ][+ +-- +-- Stephen A. Edwards, sedwards@cs.columbia.edu +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity apple2 is + port ( + CLK_14M : in std_logic; -- 14.31818 MHz master clock + CLK_2M : out std_logic; + CPU_WAIT : in std_logic; + PRE_PHASE_ZERO : out std_logic; + FLASH_CLK : in std_logic; -- approx. 2 Hz flashing char clock + reset : in std_logic; + ADDR : out unsigned(15 downto 0); -- CPU address + ram_addr : out unsigned(17 downto 0); -- RAM address + D : out unsigned(7 downto 0); -- Data to RAM + ram_do : in unsigned(7 downto 0); -- Data from RAM + PD : in unsigned(7 downto 0); -- Data to CPU from peripherals + ram_we : out std_logic; -- RAM write enable + VIDEO : out std_logic; + COLOR_LINE : out std_logic; + HBL : out std_logic; + VBL : out std_logic; + LD194 : out std_logic; + K : in unsigned(7 downto 0); -- Keyboard data + READ_KEY : out std_logic; -- Processor has read key + AN : out std_logic_vector(3 downto 0); -- Annunciator outputs + -- GAMEPORT input bits: + -- 7 6 5 4 3 2 1 0 + -- pdl3 pdl2 pdl1 pdl0 pb3 pb2 pb1 casette + GAMEPORT : in std_logic_vector(7 downto 0); + PDL_STROBE : out std_logic; -- Pulses high when C07x read + STB : out std_logic; -- Pulses high when C04x read + IO_SELECT : out std_logic_vector(7 downto 0); + DEVICE_SELECT : out std_logic_vector(7 downto 0); + pcDebugOut : out unsigned(15 downto 0); + opcodeDebugOut : out unsigned(7 downto 0); + laudio : out std_logic_vector(7 downto 0); + raudio : out std_logic_vector(7 downto 0); + mb_enabled : in std_logic; + speaker : out std_logic -- One-bit speaker output + ); +end apple2; + +architecture rtl of apple2 is + + component ramcard is + port ( mclk28: in std_logic; + reset_in: in std_logic; + addr: in std_logic_vector(15 downto 0); + ram_addr: out std_logic_vector(17 downto 0); + we: in std_logic; + card_ram_we: out std_logic; + card_ram_rd: out std_logic; + bank1: out std_logic + ); + end component; + + -- Clocks + signal CLK_7M : std_logic; + signal Q3, RAS_N, CAS_N, AX : std_logic; + signal PHASE_ZERO, PRE_PHASE_ZERO_sig : std_logic; + signal COLOR_REF : std_logic; + + -- From the timing generator + signal VIDEO_ADDRESS : unsigned(15 downto 0); + signal LDPS_N : std_logic; + signal H0, VA, VB, VC, V2, V4 : std_logic; + signal BLANK, LD194_I : std_logic; + + signal HIRES : std_logic; -- from video generator B11 p6 + + -- Soft switches + signal soft_switches : std_logic_vector(7 downto 0) := "00000000"; + signal TEXT_MODE : std_logic; + signal MIXED_MODE : std_logic; + signal PAGE2 : std_logic; + signal HIRES_MODE : std_logic; + + -- CPU signals + signal D_IN : unsigned(7 downto 0); + signal D_OUT: unsigned(7 downto 0); + signal A : unsigned(15 downto 0); + signal we : std_logic; + + -- Main ROM signals + signal rom_out : unsigned(7 downto 0); + signal rom_addr : unsigned(13 downto 0); + + -- Address decoder signals + signal RAM_SELECT : std_logic := '1'; + signal KEYBOARD_SELECT : std_logic := '0'; + signal SPEAKER_SELECT : std_logic; + signal SOFTSWITCH_SELECT : std_logic; + signal ROM_SELECT : std_logic; + signal GAMEPORT_SELECT : std_logic; + signal IO_STROBE : std_logic; + + -- Speaker signal + signal speaker_sig : std_logic := '0'; + + signal DL : unsigned(7 downto 0); -- Latched RAM data + + -- ramcard + signal card_addr : unsigned(17 downto 0); + signal card_ram_rd : std_logic; + signal card_ram_we : std_logic; + signal ram_card_read : std_logic; + signal ram_card_write : std_logic; + + signal psg_irq_n : std_logic; + signal psg_do : unsigned(7 downto 0); + + signal ioselect : std_logic_vector(7 downto 0); + signal devselect : std_logic_vector(7 downto 0); + + signal R_W_n : std_logic; + +begin + + CLK_2M <= Q3; + PRE_PHASE_ZERO <= PRE_PHASE_ZERO_sig; + + ram_addr <= card_addr when PHASE_ZERO = '1' else "00" & VIDEO_ADDRESS; + ram_we <= ((we and RAM_SELECT) or (we and ram_card_write)) when PHASE_ZERO = '1' else '0'; + + -- Latch RAM data on the rising edge of RAS + RAM_data_latch : process (CLK_14M) + begin + if rising_edge(CLK_14M) then + if AX = '1' and CAS_N = '0' and RAS_N = '0' then + DL <= ram_do; + end if; + end if; + end process; + + ADDR <= A; + D <= D_OUT; + + IO_SELECT <= ioselect; + DEVICE_SELECT <= devselect; + + -- Address decoding + rom_addr <= (A(13) and A(12)) & (not A(12)) & A(11 downto 0); + + address_decoder: process (A) + begin + ROM_SELECT <= '0'; + RAM_SELECT <= '0'; + KEYBOARD_SELECT <= '0'; + READ_KEY <= '0'; + SPEAKER_SELECT <= '0'; + SOFTSWITCH_SELECT <= '0'; + GAMEPORT_SELECT <= '0'; + PDL_STROBE <= '0'; + STB <= '0'; + ioselect <= (others => '0'); + devselect <= (others => '0'); + IO_STROBE <= '0'; + case A(15 downto 14) is + when "00" | "01" | "10" => -- 0000 - BFFF + RAM_SELECT <= '1'; + when "11" => -- C000 - FFFF + case A(13 downto 12) is + when "00" => -- C000 - CFFF + case A(11 downto 8) is + when x"0" => -- C000 - C0FF + case A(7 downto 4) is + when x"0" => -- C000 - C00F + KEYBOARD_SELECT <= '1'; + when x"1" => -- C010 - C01F + READ_KEY <= '1'; + when x"3" => -- C030 - C03F + SPEAKER_SELECT <= '1'; + when x"4" => + STB <= '1'; + when x"5" => -- C050 - C05F + SOFTSWITCH_SELECT <= '1'; + when x"6" => -- C060 - C06F + GAMEPORT_SELECT <= '1'; + when x"7" => -- C070 - C07F + PDL_STROBE <= '1'; + when x"8" | x"9" | x"A" | -- C080 - C0FF + x"B" | x"C" | x"D" | x"E" | x"F" => + devselect(TO_INTEGER(A(6 downto 4))) <= '1'; + when others => null; + end case; + when x"1" | x"2" | x"3" | -- C100 - C7FF + x"4" | x"5" | x"6" | x"7" => + ioselect(TO_INTEGER(A(10 downto 8))) <= '1'; + when x"8" | x"9" | x"A" | -- C800 - CFFF + x"B" | x"C" | x"D" | x"E" | x"F" => + IO_STROBE <= '1'; + when others => null; + end case; + when "01" | "10" | "11" => -- D000 - FFFF + ROM_SELECT <= '1'; + when others => + null; + end case; + when others => null; + end case; + end process address_decoder; + + speaker_ctrl: process (Q3) + begin + if rising_edge(Q3) then + if PRE_PHASE_ZERO_sig = '1' and SPEAKER_SELECT = '1' then + speaker_sig <= not speaker_sig; + end if; + end if; + end process speaker_ctrl; + + softswitches: process (Q3) + begin + if rising_edge(Q3) then + if PRE_PHASE_ZERO_sig = '1' and SOFTSWITCH_SELECT = '1' then + soft_switches(TO_INTEGER(A(3 downto 1))) <= A(0); + end if; + end if; + end process softswitches; + + TEXT_MODE <= soft_switches(0); + MIXED_MODE <= soft_switches(1); + PAGE2 <= soft_switches(2); + HIRES_MODE <= soft_switches(3); + AN <= soft_switches(7 downto 4); + + speaker <= speaker_sig; + + D_IN <= DL when RAM_SELECT = '1' or ram_card_read = '1' else -- RAM + K when KEYBOARD_SELECT = '1' else -- Keyboard + GAMEPORT(TO_INTEGER(A(2 downto 0))) & "0000000" -- Gameport + when GAMEPORT_SELECT = '1' else + rom_out when ROM_SELECT = '1' else -- ROMs + psg_do when (devselect(4) = '1' or ioselect(4) = '1') and mb_enabled = '1' else + PD; -- Peripherals + + LD194 <= LD194_I; + + timing : entity work.timing_generator port map ( + CLK_14M => CLK_14M, + CLK_7M => CLK_7M, + CAS_N => CAS_N, + RAS_N => RAS_N, + Q3 => Q3, + AX => AX, + PHI0 => PHASE_ZERO, + PRE_PHI0 => PRE_PHASE_ZERO_sig, + COLOR_REF => COLOR_REF, + TEXT_MODE => TEXT_MODE, + PAGE2 => PAGE2, + HIRES => HIRES, + VIDEO_ADDRESS => VIDEO_ADDRESS, + H0 => H0, + VA => VA, + VB => VB, + VC => VC, + V2 => V2, + V4 => V4, + VBL => VBL, + HBL => HBL, + BLANK => BLANK, + LDPS_N => LDPS_N, + LD194 => LD194_I); + + video_display : entity work.video_generator port map ( + CLK_14M => CLK_14M, + CLK_7M => CLK_7M, + AX => AX, + CAS_N => CAS_N, + TEXT_MODE => TEXT_MODE, + PAGE2 => PAGE2, + HIRES_MODE => HIRES_MODE, + MIXED_MODE => MIXED_MODE, + H0 => H0, + VA => VA, + VB => VB, + VC => VC, + V2 => V2, + V4 => V4, + BLANK => BLANK, + DL => DL, + LDPS_N => LDPS_N, + LD194 => LD194_I, + FLASH_CLK => FLASH_CLK, + HIRES => HIRES, + VIDEO => VIDEO, + COLOR_LINE => COLOR_LINE); + + cpu : entity work.cpu65xx + generic map ( + pipelineOpcode => false, + pipelineAluMux => false, + pipelineAluOut => false) + port map ( + clk => Q3, + enable => (not PRE_PHASE_ZERO_sig) and (not CPU_WAIT), + reset => reset, + nmi_n => '1', + irq_n => psg_irq_n, + di => D_IN, + do => D_OUT, + addr => A, + we => we, + debugPc => pcDebugOut, + debugOpcode => opcodeDebugOut + ); + + -- Original Apple had asynchronous ROMs. We use a synchronous ROM + -- that needs its address earlier, hence the odd clock. + roms : entity work.roms port map ( + address => std_logic_vector(rom_addr), + clock => CLK_14M, + unsigned(q) => rom_out); + + -- ramcard + ram_card_D: component ramcard + port map + ( + mclk28 => CLK_14M, + reset_in => reset, + addr => std_logic_vector(A), + unsigned(ram_addr) => card_addr, + we => we, + card_ram_we => card_ram_we, + card_ram_rd => card_ram_rd, + bank1 => open + ); + + ram_card_read <= ROM_SELECT and card_ram_rd; + ram_card_write <= ROM_SELECT and card_ram_we; + + mb : work.mockingboard + port map ( + CLK_VIA => not Q3, + CLK_PSG => not PHASE_ZERO, + I_P2_H => not PHASE_ZERO, + I_RESET_L => not reset, + I_ENA_H => mb_enabled, + + I_ADDR => std_logic_vector(A)(7 downto 0), + I_DATA => std_logic_vector(D_OUT), + unsigned(O_DATA) => psg_do, + I_RW_L => not we, + I_IOSEL_L => not ioselect(4), + O_IRQ_L => psg_irq_n, + O_AUDIO_L => laudio, + O_AUDIO_R => raudio + ); + +end rtl; diff --git a/apple2_top.vhd b/apple2_top.vhd new file mode 100644 index 0000000..9e7072d --- /dev/null +++ b/apple2_top.vhd @@ -0,0 +1,252 @@ +-- +-- +-- Apple II+ toplevel for the MiST board +-- https://github.com/wsoltys/mist_apple2 +-- +-- Copyright (c) 2014 W. Soltys +-- +-- This source file is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published +-- by the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This source file is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see . +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity apple2_top is port +( + -- Clocks + CLK_28M : in std_logic; + CLK_14M : in std_logic; + CPU_WAIT : in std_logic; + + reset_in : in std_logic; + + -- VGA output + VGA_DE : out std_logic; + VGA_CLK : out std_logic; + VGA_HS : out std_logic; + VGA_VS : out std_logic; + VGA_R : out std_logic_vector(7 downto 0); + VGA_G : out std_logic_vector(7 downto 0); + VGA_B : out std_logic_vector(7 downto 0); + SCREEN_MODE : in std_logic_vector(1 downto 0); -- 00: Color, 01: B&W, 10:Green, 11: Amber + + -- Audio + AUDIO_L : out std_logic_vector(7 downto 0); + AUDIO_R : out std_logic_vector(7 downto 0); + SPEAKER : out std_logic; + + ps2Clk : in std_logic; + ps2Data : in std_logic; + + joy : in std_logic_vector(5 downto 0); + joy_an : in std_logic_vector(15 downto 0); + + -- mocking board + mb_enabled : in std_logic; + + -- disk control + TRACK : out unsigned(5 downto 0); + TRACK_RAM_ADDR : in unsigned(12 downto 0); + TRACK_RAM_DI : in unsigned(7 downto 0); + TRACK_RAM_WE : in std_logic; + + -- main RAM + ram_addr : out std_logic_vector(17 downto 0); + ram_dout : in std_logic_vector(7 downto 0); + ram_din : out std_logic_vector(7 downto 0); + ram_we : out std_logic; + + -- LEDG + LED : out std_logic +); + +end apple2_top; + +architecture datapath of apple2_top is + + signal CLK_2M, PRE_PHASE_ZERO: std_logic; + signal IO_SELECT, DEVICE_SELECT : std_logic_vector(7 downto 0); + signal ADDR : unsigned(15 downto 0); + signal D, PD: unsigned(7 downto 0); + + signal we_ram : std_logic; + signal VIDEO, HBL, VBL, LD194 : std_logic; + signal COLOR_LINE : std_logic; + signal COLOR_LINE_CONTROL : std_logic; + signal GAMEPORT : std_logic_vector(7 downto 0); + signal cpu_pc : unsigned(15 downto 0); + + signal K : unsigned(7 downto 0); + signal read_key : std_logic; + + signal flash_clk : unsigned(22 downto 0) := (others => '0'); + signal power_on_reset : std_logic := '1'; + signal reset : std_logic; + + signal a_ram: unsigned(17 downto 0); + + signal joyx : std_logic; + signal joyy : std_logic; + signal pdl_strobe : std_logic; + +begin + + reset <= power_on_reset; + + power_on : process(CLK_14M, reset_in) + begin + if reset_in = '1' then + power_on_reset <= '1'; + elsif rising_edge(CLK_14M) then + if flash_clk(22) = '1' then + power_on_reset <= '0'; + end if; + end if; + end process; + + -- In the Apple ][, this was a 555 timer + flash_clkgen : process (CLK_14M, reset_in) + begin + if reset_in = '1' then + flash_clk <= (others=>'0'); + elsif rising_edge(CLK_14M) then + flash_clk <= flash_clk + 1; + end if; + end process; + + -- Paddle buttons + -- GAMEPORT input bits: + -- 7 6 5 4 3 2 1 0 + -- pdl3 pdl2 pdl1 pdl0 pb3 pb2 pb1 casette + GAMEPORT <= "00" & joyy & joyx & "0" & joy(5) & joy(4) & "0"; + + process(CLK_2M, pdl_strobe) + variable cx, cy : integer range -100 to 5800 := 0; + begin + if rising_edge(CLK_2M) then + if cx > 0 then + cx := cx -1; + joyx <= '1'; + else + joyx <= '0'; + end if; + if cy > 0 then + cy := cy -1; + joyy <= '1'; + else + joyy <= '0'; + end if; + if pdl_strobe = '1' then + cx := 2800+(22*to_integer(signed(joy_an(7 downto 0)))); + cy := 2800+(22*to_integer(signed(joy_an(15 downto 8)))); -- max 5650 + if cx < 0 then + cx := 0; + elsif cx >= 5590 then + cx := 5650; + end if; + if cy < 0 then + cy := 0; + elsif cy >= 5590 then + cy := 5650; + end if; + end if; + end if; + end process; + + COLOR_LINE_CONTROL <= COLOR_LINE and not (SCREEN_MODE(0) or SCREEN_MODE(1)); -- Color or B&W mode + + -- Simulate power up on cold reset to go to the disk boot routine + ram_we <= we_ram; -- when reset_in = '0' else '1'; + ram_addr <= std_logic_vector(a_ram); -- when reset_in = '0' else std_logic_vector(to_unsigned(1012,ram_addr'length)); -- $3F4 + ram_din <= std_logic_vector(D); -- when reset_in = '0' else "00000000"; + + core : entity work.apple2 port map ( + CLK_14M => CLK_14M, + CLK_2M => CLK_2M, + CPU_WAIT => CPU_WAIT, + PRE_PHASE_ZERO => PRE_PHASE_ZERO, + FLASH_CLK => flash_clk(22), + reset => reset, + ADDR => ADDR, + ram_addr => a_ram, + D => D, + ram_do => unsigned(ram_dout), + PD => PD, + ram_we => we_ram, + VIDEO => VIDEO, + COLOR_LINE => COLOR_LINE, + HBL => HBL, + VBL => VBL, + LD194 => LD194, + K => K, + read_key => read_key, + AN => open, + GAMEPORT => GAMEPORT, + PDL_strobe => pdl_strobe, + IO_SELECT => IO_SELECT, + DEVICE_SELECT => DEVICE_SELECT, + pcDebugOut => cpu_pc, + speaker => SPEAKER, + laudio => AUDIO_L, + raudio => AUDIO_R, + mb_enabled => mb_enabled + ); + + vga : entity work.vga_controller port map ( + CLK_28M => CLK_28M, + VIDEO => VIDEO, + COLOR_LINE => COLOR_LINE_CONTROL, + SCREEN_MODE => SCREEN_MODE, + HBL => HBL, + VBL => VBL, + LD194 => LD194, + VGA_CLK => VGA_CLK, + VGA_HS => VGA_HS, + VGA_VS => VGA_VS, + VGA_DE => VGA_DE, + std_logic_vector(VGA_R) => VGA_R, + std_logic_vector(VGA_G) => VGA_G, + std_logic_vector(VGA_B) => VGA_B + ); + + keyboard : entity work.keyboard port map ( + PS2_Clk => ps2Clk, + PS2_Data => ps2Data, + CLK_14M => CLK_14M, + reset => reset, + reads => read_key, + K => K + ); + + disk : entity work.disk_ii port map ( + CLK_14M => CLK_14M, + CLK_2M => CLK_2M, + PRE_PHASE_ZERO => PRE_PHASE_ZERO, + IO_SELECT => IO_SELECT(6), + DEVICE_SELECT => DEVICE_SELECT(6), + RESET => reset, + A => ADDR, + D_IN => D, + D_OUT => PD, + TRACK => TRACK, + TRACK_ADDR => open, + D1_ACTIVE => LED, + D2_ACTIVE => open, + ram_write_addr => TRACK_RAM_ADDR, + ram_di => TRACK_RAM_DI, + ram_we => TRACK_RAM_WE + ); + +end datapath; \ No newline at end of file diff --git a/character_rom.vhd b/character_rom.vhd new file mode 100644 index 0000000..33c5072 --- /dev/null +++ b/character_rom.vhd @@ -0,0 +1,539 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity character_rom is + + port ( + addr : in unsigned(8 downto 0); + clk : in std_logic; + dout : out unsigned(4 downto 0)); +end character_rom; + +architecture rtl of character_rom is + type rom_array is array (0 to 511) of unsigned(4 downto 0); + + constant ROM : rom_array := ( + "01110", + "10001", + "10101", + "11101", + "01101", + "00001", + "11110", + "00000", + "00100", + "01010", + "10001", + "10001", + "11111", + "10001", + "10001", + "00000", + "01111", + "10001", + "10001", + "01111", + "10001", + "10001", + "01111", + "00000", + "01110", + "10001", + "00001", + "00001", + "00001", + "10001", + "01110", + "00000", + "01111", + "10001", + "10001", + "10001", + "10001", + "10001", + "01111", + "00000", + "11111", + "00001", + "00001", + "01111", + "00001", + "00001", + "11111", + "00000", + "11111", + "00001", + "00001", + "01111", + "00001", + "00001", + "00001", + "00000", + "11110", + "00001", + "00001", + "00001", + "11001", + "10001", + "11110", + "00000", + "10001", + "10001", + "10001", + "11111", + "10001", + "10001", + "10001", + "00000", + "01110", + "00100", + "00100", + "00100", + "00100", + "00100", + "01110", + "00000", + "10000", + "10000", + "10000", + "10000", + "10000", + "10001", + "01110", + "00000", + "10001", + "01001", + "00101", + "00011", + "00101", + "01001", + "10001", + "00000", + "00001", + "00001", + "00001", + "00001", + "00001", + "00001", + "11111", + "00000", + "10001", + "11011", + "10101", + "10101", + "10001", + "10001", + "10001", + "00000", + "10001", + "10001", + "10011", + "10101", + "11001", + "10001", + "10001", + "00000", + "01110", + "10001", + "10001", + "10001", + "10001", + "10001", + "01110", + "00000", + "01111", + "10001", + "10001", + "01111", + "00001", + "00001", + "00001", + "00000", + "01110", + "10001", + "10001", + "10001", + "10101", + "01001", + "10110", + "00000", + "01111", + "10001", + "10001", + "01111", + "00101", + "01001", + "10001", + "00000", + "01110", + "10001", + "00001", + "01110", + "10000", + "10001", + "01110", + "00000", + "11111", + "00100", + "00100", + "00100", + "00100", + "00100", + "00100", + "00000", + "10001", + "10001", + "10001", + "10001", + "10001", + "10001", + "01110", + "00000", + "10001", + "10001", + "10001", + "10001", + "10001", + "01010", + "00100", + "00000", + "10001", + "10001", + "10001", + "10101", + "10101", + "11011", + "10001", + "00000", + "10001", + "10001", + "01010", + "00100", + "01010", + "10001", + "10001", + "00000", + "10001", + "10001", + "01010", + "00100", + "00100", + "00100", + "00100", + "00000", + "11111", + "10000", + "01000", + "00100", + "00010", + "00001", + "11111", + "00000", + "11111", + "00011", + "00011", + "00011", + "00011", + "00011", + "11111", + "00000", + "00000", + "00001", + "00010", + "00100", + "01000", + "10000", + "00000", + "00000", + "11111", + "11000", + "11000", + "11000", + "11000", + "11000", + "11111", + "00000", + "00000", + "00000", + "00100", + "01010", + "10001", + "00000", + "00000", + "00000", + "00000", + "00000", + "00000", + "00000", + "00000", + "00000", + "11111", + "00000", + "00000", + "00000", + "00000", + "00000", + "00000", + "00000", + "00000", + "00000", + "00100", + "00100", + "00100", + "00100", + "00100", + "00000", + "00100", + "00000", + "01010", + "01010", + "01010", + "00000", + "00000", + "00000", + "00000", + "00000", + "01010", + "01010", + "11111", + "01010", + "11111", + "01010", + "01010", + "00000", + "00100", + "11110", + "00101", + "01110", + "10100", + "01111", + "00100", + "00000", + "00011", + "10011", + "01000", + "00100", + "00010", + "11001", + "11000", + "00000", + "00010", + "00101", + "00101", + "00010", + "10101", + "01001", + "10110", + "00000", + "00100", + "00100", + "00100", + "00000", + "00000", + "00000", + "00000", + "00000", + "00100", + "00010", + "00001", + "00001", + "00001", + "00010", + "00100", + "00000", + "00100", + "01000", + "10000", + "10000", + "10000", + "01000", + "00100", + "00000", + "00100", + "10101", + "01110", + "00100", + "01110", + "10101", + "00100", + "00000", + "00000", + "00100", + "00100", + "11111", + "00100", + "00100", + "00000", + "00000", + "00000", + "00000", + "00000", + "00000", + "00100", + "00100", + "00010", + "00000", + "00000", + "00000", + "00000", + "11111", + "00000", + "00000", + "00000", + "00000", + "00000", + "00000", + "00000", + "00000", + "00000", + "00000", + "00100", + "00000", + "00000", + "10000", + "01000", + "00100", + "00010", + "00001", + "00000", + "00000", + "01110", + "10001", + "11001", + "10101", + "10011", + "10001", + "01110", + "00000", + "00100", + "00110", + "00100", + "00100", + "00100", + "00100", + "01110", + "00000", + "01110", + "10001", + "10000", + "01100", + "00010", + "00001", + "11111", + "00000", + "11111", + "10000", + "01000", + "01100", + "10000", + "10001", + "01110", + "00000", + "01000", + "01100", + "01010", + "01001", + "11111", + "01000", + "01000", + "00000", + "11111", + "00001", + "01111", + "10000", + "10000", + "10001", + "01110", + "00000", + "11100", + "00010", + "00001", + "01111", + "10001", + "10001", + "01110", + "00000", + "11111", + "10000", + "01000", + "00100", + "00010", + "00010", + "00010", + "00000", + "01110", + "10001", + "10001", + "01110", + "10001", + "10001", + "01110", + "00000", + "01110", + "10001", + "10001", + "11110", + "10000", + "01000", + "00111", + "00000", + "00000", + "00000", + "00100", + "00000", + "00100", + "00000", + "00000", + "00000", + "00000", + "00000", + "00100", + "00000", + "00100", + "00100", + "00010", + "00000", + "01000", + "00100", + "00010", + "00001", + "00010", + "00100", + "01000", + "00000", + "00000", + "00000", + "11111", + "00000", + "11111", + "00000", + "00000", + "00000", + "00010", + "00100", + "01000", + "10000", + "01000", + "00100", + "00010", + "00000", + "01110", + "10001", + "01000", + "00100", + "00100", + "00000", + "00100", + "00000"); + +begin + + process (clk) + begin + if rising_edge(clk) then + dout <= ROM(TO_INTEGER(addr)); + end if; + end process; + +end rtl; diff --git a/clean.bat b/clean.bat new file mode 100644 index 0000000..3c54b34 --- /dev/null +++ b/clean.bat @@ -0,0 +1,39 @@ +@echo off +del /s *.bak +del /s *.orig +del /s *.rej +del /s *~ +rmdir /s /q db +rmdir /s /q incremental_db +rmdir /s /q output_files +rmdir /s /q simulation +rmdir /s /q greybox_tmp +rmdir /s /q hc_output +rmdir /s /q .qsys_edit +rmdir /s /q hps_isw_handoff +rmdir /s /q sys\.qsys_edit +rmdir /s /q sys\vip +rmdir /s /q diskemu\.qsys_edit +rmdir /s /q diskemu\diskemu +cd sys +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +cd .. +for /d %%i in (*_sim) do rmdir /s /q "%%~nxi" +del build_id.v +del c5_pin_model_dump.txt +del PLLJ_PLLSPE_INFO.txt +del /s *.qws +del /s *.ppf +del /s *.ddb +del /s *.csv +del /s *.cmp +del /s *.sip +del /s *.spd +del /s *.bsf +del /s *.f +del /s *.sopcinfo +del /s *.xml +del /s new_rtl_netlist +del /s old_rtl_netlist + +pause diff --git a/cpu6502.vhd b/cpu6502.vhd new file mode 100644 index 0000000..1c521ff --- /dev/null +++ b/cpu6502.vhd @@ -0,0 +1,1598 @@ +-- ----------------------------------------------------------------------- +-- +-- FPGA 64 +-- +-- A fully functional commodore 64 implementation in a single FPGA +-- +-- ----------------------------------------------------------------------- +-- +-- Table driven, cycle exact 6502/6510 core +-- +-- ----------------------------------------------------------------------- +-- +-- cpu65xx_fast.vhdl, part of FPGA-64, is made available strictly for personal +-- educational purposes. Distributed with apple2fgpa with permission. +-- +-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com). +-- All rights reserved. +-- http://www.syntiac.com/fpga64.html +-- +-- ----------------------------------------------------------------------- + +library IEEE; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; + +entity cpu65xx is + generic ( + pipelineOpcode : boolean; + pipelineAluMux : boolean; + pipelineAluOut : boolean + ); + port ( + clk : in std_logic; + enable : in std_logic; + reset : in std_logic; + nmi_n : in std_logic; + irq_n : in std_logic; + so_n : in std_logic := '1'; + + di : in unsigned(7 downto 0); + do : out unsigned(7 downto 0); + addr : out unsigned(15 downto 0); + we : out std_logic; + + debugOpcode : out unsigned(7 downto 0); + debugPc : out unsigned(15 downto 0); + debugA : out unsigned(7 downto 0); + debugX : out unsigned(7 downto 0); + debugY : out unsigned(7 downto 0); + debugS : out unsigned(7 downto 0) + ); +end cpu65xx; + +-- ----------------------------------------------------------------------- + +-- Store Zp (3) => fetch, cycle2, cycleEnd +-- Store Zp,x (4) => fetch, cycle2, preWrite, cycleEnd +-- Read Zp,x (4) => fetch, cycle2, cycleRead, cycleRead2 +-- Rmw Zp,x (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd +-- Store Abs (4) => fetch, cycle2, cycle3, cycleEnd +-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd +-- Rts (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd +-- Rti (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump +-- Jsr (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump +-- Jmp abs (-) => fetch, cycle2, .., cycleJump +-- Jmp (ind) (-) => fetch, cycle2, .., cycleJump +-- Brk / irq (6) => fetch, cycle2, stack2, stack3, stack4 +-- ----------------------------------------------------------------------- + +architecture fast of cpu65xx is +-- Statemachine + type cpuCycles is ( + opcodeFetch, -- New opcode is read and registers updated + cycle2, + cycle3, + cyclePreIndirect, + cycleIndirect, + cycleBranchTaken, + cycleBranchPage, + cyclePreRead, -- Cycle before read while doing zeropage indexed addressing. + cycleRead, -- Read cycle + cycleRead2, -- Second read cycle after page-boundary crossing. + cycleRmw, -- Calculate ALU output for read-modify-write instr. + cyclePreWrite, -- Cycle before write when doing indexed addressing. + cycleWrite, -- Write cycle for zeropage or absolute addressing. + cycleStack1, + cycleStack2, + cycleStack3, + cycleStack4, + cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr. + cycleEnd + ); + signal theCpuCycle : cpuCycles; + signal nextCpuCycle : cpuCycles; + signal updateRegisters : boolean; + signal processIrq : std_logic; + signal nmiReg: std_logic; + signal nmiEdge: std_logic; + signal irqReg : std_logic; -- Delay IRQ input with one clock cycle. + signal soReg : std_logic; -- SO pin edge detection + +-- Opcode decoding + constant opcUpdateA : integer := 0; + constant opcUpdateX : integer := 1; + constant opcUpdateY : integer := 2; + constant opcUpdateS : integer := 3; + constant opcUpdateN : integer := 4; + constant opcUpdateV : integer := 5; + constant opcUpdateD : integer := 6; + constant opcUpdateI : integer := 7; + constant opcUpdateZ : integer := 8; + constant opcUpdateC : integer := 9; + + constant opcSecondByte : integer := 10; + constant opcAbsolute : integer := 11; + constant opcZeroPage : integer := 12; + constant opcIndirect : integer := 13; + constant opcStackAddr : integer := 14; -- Push/Pop address + constant opcStackData : integer := 15; -- Push/Pop status/data + constant opcJump : integer := 16; + constant opcBranch : integer := 17; + constant indexX : integer := 18; + constant indexY : integer := 19; + constant opcStackUp : integer := 20; + constant opcWrite : integer := 21; + constant opcRmw : integer := 22; + constant opcIncrAfter : integer := 23; -- Insert extra cycle to increment PC (RTS) + constant opcRti : integer := 24; + constant opcIRQ : integer := 25; + + constant opcInA : integer := 26; + constant opcInE : integer := 27; + constant opcInX : integer := 28; + constant opcInY : integer := 29; + constant opcInS : integer := 30; + constant opcInT : integer := 31; + constant opcInH : integer := 32; + constant opcInClear : integer := 33; + constant aluMode1From : integer := 34; + -- + constant aluMode1To : integer := 37; + constant aluMode2From : integer := 38; + -- + constant aluMode2To : integer := 40; + -- + constant opcInCmp : integer := 41; + constant opcInCpx : integer := 42; + constant opcInCpy : integer := 43; + + + subtype addrDef is unsigned(0 to 15); + -- + -- is Interrupt -----------------+ + -- instruction is RTI ----------------+| + -- PC++ on last cycle (RTS) ---------------+|| + -- RMW --------------+||| + -- Write -------------+|||| + -- Pop/Stack up -------------+||||| + -- Branch ---------+ |||||| + -- Jump ----------+| |||||| + -- Push or Pop data -------+|| |||||| + -- Push or Pop addr ------+||| |||||| + -- Indirect -----+|||| |||||| + -- ZeroPage ----+||||| |||||| + -- Absolute ---+|||||| |||||| + -- PC++ on cycle2 --+||||||| |||||| + -- |AZI||JBXY|WM||| + constant immediate : addrDef := "1000000000000000"; + constant implied : addrDef := "0000000000000000"; + -- Zero page + constant readZp : addrDef := "1010000000000000"; + constant writeZp : addrDef := "1010000000010000"; + constant rmwZp : addrDef := "1010000000001000"; + -- Zero page indexed + constant readZpX : addrDef := "1010000010000000"; + constant writeZpX : addrDef := "1010000010010000"; + constant rmwZpX : addrDef := "1010000010001000"; + constant readZpY : addrDef := "1010000001000000"; + constant writeZpY : addrDef := "1010000001010000"; + constant rmwZpY : addrDef := "1010000001001000"; + -- Zero page indirect + constant readIndX : addrDef := "1001000010000000"; + constant writeIndX : addrDef := "1001000010010000"; + constant rmwIndX : addrDef := "1001000010001000"; + constant readIndY : addrDef := "1001000001000000"; + constant writeIndY : addrDef := "1001000001010000"; + constant rmwIndY : addrDef := "1001000001001000"; + -- |AZI||JBXY|WM|| + -- Absolute + constant readAbs : addrDef := "1100000000000000"; + constant writeAbs : addrDef := "1100000000010000"; + constant rmwAbs : addrDef := "1100000000001000"; + constant readAbsX : addrDef := "1100000010000000"; + constant writeAbsX : addrDef := "1100000010010000"; + constant rmwAbsX : addrDef := "1100000010001000"; + constant readAbsY : addrDef := "1100000001000000"; + constant writeAbsY : addrDef := "1100000001010000"; + constant rmwAbsY : addrDef := "1100000001001000"; + -- PHA PHP + constant push : addrDef := "0000010000000000"; + -- PLA PLP + constant pop : addrDef := "0000010000100000"; + -- Jumps + constant jsr : addrDef := "1000101000000000"; + constant jumpAbs : addrDef := "1000001000000000"; + constant jumpInd : addrDef := "1100001000000000"; + constant relative : addrDef := "1000000100000000"; + -- Specials + constant rts : addrDef := "0000101000100100"; + constant rti : addrDef := "0000111000100010"; + constant brk : addrDef := "1000111000000001"; +-- constant : unsigned(0 to 0) := "0"; + constant xxxxxxxx : addrDef := "----------0---00"; + + -- A = accu + -- E = Accu | 0xEE (for ANE, LXA) + -- X = index X + -- Y = index Y + -- S = Stack pointer + -- H = indexH + -- + -- AEXYSTHc + constant aluInA : unsigned(0 to 7) := "10000000"; + constant aluInE : unsigned(0 to 7) := "01000000"; + constant aluInEXT : unsigned(0 to 7) := "01100100"; + constant aluInET : unsigned(0 to 7) := "01000100"; + constant aluInX : unsigned(0 to 7) := "00100000"; + constant aluInXH : unsigned(0 to 7) := "00100010"; + constant aluInY : unsigned(0 to 7) := "00010000"; + constant aluInYH : unsigned(0 to 7) := "00010010"; + constant aluInS : unsigned(0 to 7) := "00001000"; + constant aluInT : unsigned(0 to 7) := "00000100"; + constant aluInAX : unsigned(0 to 7) := "10100000"; + constant aluInAXH : unsigned(0 to 7) := "10100010"; + constant aluInAT : unsigned(0 to 7) := "10000100"; + constant aluInXT : unsigned(0 to 7) := "00100100"; + constant aluInST : unsigned(0 to 7) := "00001100"; + constant aluInSet : unsigned(0 to 7) := "00000000"; + constant aluInClr : unsigned(0 to 7) := "00000001"; + constant aluInXXX : unsigned(0 to 7) := "--------"; + + -- Most of the aluModes are just like the opcodes. + -- aluModeInp -> input is output. calculate N and Z + -- aluModeCmp -> Compare for CMP, CPX, CPY + -- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV + -- aluModeInc -> for INC but also INX, INY + -- aluModeDec -> for DEC but also DEX, DEY + + subtype aluMode1 is unsigned(0 to 3); + subtype aluMode2 is unsigned(0 to 2); + subtype aluMode is unsigned(0 to 9); + + -- Logic/Shift ALU + constant aluModeInp : aluMode1 := "0000"; + constant aluModeP : aluMode1 := "0001"; + constant aluModeInc : aluMode1 := "0010"; + constant aluModeDec : aluMode1 := "0011"; + constant aluModeFlg : aluMode1 := "0100"; + constant aluModeBit : aluMode1 := "0101"; + -- 0110 + -- 0111 + constant aluModeLsr : aluMode1 := "1000"; + constant aluModeRor : aluMode1 := "1001"; + constant aluModeAsl : aluMode1 := "1010"; + constant aluModeRol : aluMode1 := "1011"; + -- 1100 + -- 1101 + -- 1110 + constant aluModeAnc : aluMode1 := "1111"; + + -- Arithmetic ALU + constant aluModePss : aluMode2 := "000"; + constant aluModeCmp : aluMode2 := "001"; + constant aluModeAdc : aluMode2 := "010"; + constant aluModeSbc : aluMode2 := "011"; + constant aluModeAnd : aluMode2 := "100"; + constant aluModeOra : aluMode2 := "101"; + constant aluModeEor : aluMode2 := "110"; + constant aluModeArr : aluMode2 := "111"; + + + constant aluInp : aluMode := aluModeInp & aluModePss & "---"; + constant aluP : aluMode := aluModeP & aluModePss & "---"; + constant aluInc : aluMode := aluModeInc & aluModePss & "---"; + constant aluDec : aluMode := aluModeDec & aluModePss & "---"; + constant aluFlg : aluMode := aluModeFlg & aluModePss & "---"; + constant aluBit : aluMode := aluModeBit & aluModeAnd & "---"; + constant aluRor : aluMode := aluModeRor & aluModePss & "---"; + constant aluLsr : aluMode := aluModeLsr & aluModePss & "---"; + constant aluRol : aluMode := aluModeRol & aluModePss & "---"; + constant aluAsl : aluMode := aluModeAsl & aluModePss & "---"; + + constant aluCmp : aluMode := aluModeInp & aluModeCmp & "100"; + constant aluCpx : aluMode := aluModeInp & aluModeCmp & "010"; + constant aluCpy : aluMode := aluModeInp & aluModeCmp & "001"; + constant aluAdc : aluMode := aluModeInp & aluModeAdc & "---"; + constant aluSbc : aluMode := aluModeInp & aluModeSbc & "---"; + constant aluAnd : aluMode := aluModeInp & aluModeAnd & "---"; + constant aluOra : aluMode := aluModeInp & aluModeOra & "---"; + constant aluEor : aluMode := aluModeInp & aluModeEor & "---"; + + constant aluSlo : aluMode := aluModeAsl & aluModeOra & "---"; + constant aluSre : aluMode := aluModeLsr & aluModeEor & "---"; + constant aluRra : aluMode := aluModeRor & aluModeAdc & "---"; + constant aluRla : aluMode := aluModeRol & aluModeAnd & "---"; + constant aluDcp : aluMode := aluModeDec & aluModeCmp & "100"; + constant aluIsc : aluMode := aluModeInc & aluModeSbc & "---"; + constant aluAnc : aluMode := aluModeAnc & aluModeAnd & "---"; + constant aluArr : aluMode := aluModeRor & aluModeArr & "---"; + constant aluSbx : aluMode := aluModeInp & aluModeCmp & "110"; + + constant aluXXX : aluMode := (others => '-'); + + + -- Stack operations. Push/Pop/None + constant stackInc : unsigned(0 to 0) := "0"; + constant stackDec : unsigned(0 to 0) := "1"; + constant stackXXX : unsigned(0 to 0) := "-"; + + subtype decodedBitsDef is unsigned(0 to 43); + type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef; + constant opcodeInfoTable : opcodeInfoTableDef := ( + -- +------- Update register A + -- |+------ Update register X + -- ||+----- Update register Y + -- |||+---- Update register S + -- |||| +-- Update Flags + -- |||| | + -- |||| _|__ + -- |||| / \ + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "000100" & brk & aluInXXX & aluP, -- 00 BRK + "1000" & "100010" & readIndX & aluInT & aluOra, -- 01 ORA (zp,x) + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 02 *** JAM *** + "1000" & "100011" & rmwIndX & aluInT & aluSlo, -- 03 iSLO (zp,x) + "0000" & "000000" & readZp & aluInXXX & aluXXX, -- 04 iNOP zp + "1000" & "100010" & readZp & aluInT & aluOra, -- 05 ORA zp + "0000" & "100011" & rmwZp & aluInT & aluAsl, -- 06 ASL zp + "1000" & "100011" & rmwZp & aluInT & aluSlo, -- 07 iSLO zp + "0000" & "000000" & push & aluInXXX & aluP, -- 08 PHP + "1000" & "100010" & immediate & aluInT & aluOra, -- 09 ORA imm + "1000" & "100011" & implied & aluInA & aluAsl, -- 0A ASL accu + "1000" & "100011" & immediate & aluInT & aluAnc, -- 0B iANC imm + "0000" & "000000" & readAbs & aluInXXX & aluXXX, -- 0C iNOP abs + "1000" & "100010" & readAbs & aluInT & aluOra, -- 0D ORA abs + "0000" & "100011" & rmwAbs & aluInT & aluAsl, -- 0E ASL abs + "1000" & "100011" & rmwAbs & aluInT & aluSlo, -- 0F iSLO abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 10 BPL + "1000" & "100010" & readIndY & aluInT & aluOra, -- 11 ORA (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 12 *** JAM *** + "1000" & "100011" & rmwIndY & aluInT & aluSlo, -- 13 iSLO (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 14 iNOP zp,x + "1000" & "100010" & readZpX & aluInT & aluOra, -- 15 ORA zp,x + "0000" & "100011" & rmwZpX & aluInT & aluAsl, -- 16 ASL zp,x + "1000" & "100011" & rmwZpX & aluInT & aluSlo, -- 17 iSLO zp,x + "0000" & "000001" & implied & aluInClr & aluFlg, -- 18 CLC + "1000" & "100010" & readAbsY & aluInT & aluOra, -- 19 ORA abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- 1A iNOP implied + "1000" & "100011" & rmwAbsY & aluInT & aluSlo, -- 1B iSLO abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 1C iNOP abs,x + "1000" & "100010" & readAbsX & aluInT & aluOra, -- 1D ORA abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluAsl, -- 1E ASL abs,x + "1000" & "100011" & rmwAbsX & aluInT & aluSlo, -- 1F iSLO abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "000000" & jsr & aluInXXX & aluXXX, -- 20 JSR + "1000" & "100010" & readIndX & aluInT & aluAnd, -- 21 AND (zp,x) + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 22 *** JAM *** + "1000" & "100011" & rmwIndX & aluInT & aluRla, -- 23 iRLA (zp,x) + "0000" & "110010" & readZp & aluInT & aluBit, -- 24 BIT zp + "1000" & "100010" & readZp & aluInT & aluAnd, -- 25 AND zp + "0000" & "100011" & rmwZp & aluInT & aluRol, -- 26 ROL zp + "1000" & "100011" & rmwZp & aluInT & aluRla, -- 27 iRLA zp + "0000" & "111111" & pop & aluInT & aluFlg, -- 28 PLP + "1000" & "100010" & immediate & aluInT & aluAnd, -- 29 AND imm + "1000" & "100011" & implied & aluInA & aluRol, -- 2A ROL accu + "1000" & "100011" & immediate & aluInT & aluAnc, -- 2B iANC imm + "0000" & "110010" & readAbs & aluInT & aluBit, -- 2C BIT abs + "1000" & "100010" & readAbs & aluInT & aluAnd, -- 2D AND abs + "0000" & "100011" & rmwAbs & aluInT & aluRol, -- 2E ROL abs + "1000" & "100011" & rmwAbs & aluInT & aluRla, -- 2F iRLA abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 30 BMI + "1000" & "100010" & readIndY & aluInT & aluAnd, -- 31 AND (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 32 *** JAM *** + "1000" & "100011" & rmwIndY & aluInT & aluRla, -- 33 iRLA (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 34 iNOP zp,x + "1000" & "100010" & readZpX & aluInT & aluAnd, -- 35 AND zp,x + "0000" & "100011" & rmwZpX & aluInT & aluRol, -- 36 ROL zp,x + "1000" & "100011" & rmwZpX & aluInT & aluRla, -- 37 iRLA zp,x + "0000" & "000001" & implied & aluInSet & aluFlg, -- 38 SEC + "1000" & "100010" & readAbsY & aluInT & aluAnd, -- 39 AND abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- 3A iNOP implied + "1000" & "100011" & rmwAbsY & aluInT & aluRla, -- 3B iRLA abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 3C iNOP abs,x + "1000" & "100010" & readAbsX & aluInT & aluAnd, -- 3D AND abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluRol, -- 3E ROL abs,x + "1000" & "100011" & rmwAbsX & aluInT & aluRla, -- 3F iRLA abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "111111" & rti & aluInT & aluFlg, -- 40 RTI + "1000" & "100010" & readIndX & aluInT & aluEor, -- 41 EOR (zp,x) + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 42 *** JAM *** + "1000" & "100011" & rmwIndX & aluInT & aluSre, -- 43 iSRE (zp,x) + "0000" & "000000" & readZp & aluInXXX & aluXXX, -- 44 iNOP zp + "1000" & "100010" & readZp & aluInT & aluEor, -- 45 EOR zp + "0000" & "100011" & rmwZp & aluInT & aluLsr, -- 46 LSR zp + "1000" & "100011" & rmwZp & aluInT & aluSre, -- 47 iSRE zp + "0000" & "000000" & push & aluInA & aluInp, -- 48 PHA + "1000" & "100010" & immediate & aluInT & aluEor, -- 49 EOR imm + "1000" & "100011" & implied & aluInA & aluLsr, -- 4A LSR accu + "1000" & "100011" & immediate & aluInAT & aluLsr, -- 4B iALR imm + "0000" & "000000" & jumpAbs & aluInXXX & aluXXX, -- 4C JMP abs + "1000" & "100010" & readAbs & aluInT & aluEor, -- 4D EOR abs + "0000" & "100011" & rmwAbs & aluInT & aluLsr, -- 4E LSR abs + "1000" & "100011" & rmwAbs & aluInT & aluSre, -- 4F iSRE abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 50 BVC + "1000" & "100010" & readIndY & aluInT & aluEor, -- 51 EOR (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 52 *** JAM *** + "1000" & "100011" & rmwIndY & aluInT & aluSre, -- 53 iSRE (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 54 iNOP zp,x + "1000" & "100010" & readZpX & aluInT & aluEor, -- 55 EOR zp,x + "0000" & "100011" & rmwZpX & aluInT & aluLsr, -- 56 LSR zp,x + "1000" & "100011" & rmwZpX & aluInT & aluSre, -- 57 SRE zp,x + "0000" & "000100" & implied & aluInClr & aluXXX, -- 58 CLI + "1000" & "100010" & readAbsY & aluInT & aluEor, -- 59 EOR abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- 5A iNOP implied + "1000" & "100011" & rmwAbsY & aluInT & aluSre, -- 5B iSRE abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 5C iNOP abs,x + "1000" & "100010" & readAbsX & aluInT & aluEor, -- 5D EOR abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluLsr, -- 5E LSR abs,x + "1000" & "100011" & rmwAbsX & aluInT & aluSre, -- 5F SRE abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "000000" & rts & aluInXXX & aluXXX, -- 60 RTS + "1000" & "110011" & readIndX & aluInT & aluAdc, -- 61 ADC (zp,x) + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 62 *** JAM *** + "1000" & "110011" & rmwIndX & aluInT & aluRra, -- 63 iRRA (zp,x) + "0000" & "000000" & readZp & aluInXXX & aluXXX, -- 64 iNOP zp + "1000" & "110011" & readZp & aluInT & aluAdc, -- 65 ADC zp + "0000" & "100011" & rmwZp & aluInT & aluRor, -- 66 ROR zp + "1000" & "110011" & rmwZp & aluInT & aluRra, -- 67 iRRA zp + "1000" & "100010" & pop & aluInT & aluInp, -- 68 PLA + "1000" & "110011" & immediate & aluInT & aluAdc, -- 69 ADC imm + "1000" & "100011" & implied & aluInA & aluRor, -- 6A ROR accu + "1000" & "110011" & immediate & aluInAT & aluArr, -- 6B iARR imm + "0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect + "1000" & "110011" & readAbs & aluInT & aluAdc, -- 6D ADC abs + "0000" & "100011" & rmwAbs & aluInT & aluRor, -- 6E ROR abs + "1000" & "110011" & rmwAbs & aluInT & aluRra, -- 6F iRRA abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 70 BVS + "1000" & "110011" & readIndY & aluInT & aluAdc, -- 71 ADC (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 72 *** JAM *** + "1000" & "110011" & rmwIndY & aluInT & aluRra, -- 73 iRRA (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- 74 iNOP zp,x + "1000" & "110011" & readZpX & aluInT & aluAdc, -- 75 ADC zp,x + "0000" & "100011" & rmwZpX & aluInT & aluRor, -- 76 ROR zp,x + "1000" & "110011" & rmwZpX & aluInT & aluRra, -- 77 iRRA zp,x + "0000" & "000100" & implied & aluInSet & aluXXX, -- 78 SEI + "1000" & "110011" & readAbsY & aluInT & aluAdc, -- 79 ADC abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- 7A iNOP implied + "1000" & "110011" & rmwAbsY & aluInT & aluRra, -- 7B iRRA abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- 7C iNOP abs,x + "1000" & "110011" & readAbsX & aluInT & aluAdc, -- 7D ADC abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluRor, -- 7E ROR abs,x + "1000" & "110011" & rmwAbsX & aluInT & aluRra, -- 7F iRRA abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 80 iNOP imm + "0000" & "000000" & writeIndX & aluInA & aluInp, -- 81 STA (zp,x) + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 iNOP imm + "0000" & "000000" & writeIndX & aluInAX & aluInp, -- 83 iSAX (zp,x) + "0000" & "000000" & writeZp & aluInY & aluInp, -- 84 STY zp + "0000" & "000000" & writeZp & aluInA & aluInp, -- 85 STA zp + "0000" & "000000" & writeZp & aluInX & aluInp, -- 86 STX zp + "0000" & "000000" & writeZp & aluInAX & aluInp, -- 87 iSAX zp + "0010" & "100010" & implied & aluInY & aluDec, -- 88 DEY + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 84 iNOP imm + "1000" & "100010" & implied & aluInX & aluInp, -- 8A TXA + "1000" & "100010" & immediate & aluInEXT & aluInp, -- 8B iANE imm + "0000" & "000000" & writeAbs & aluInY & aluInp, -- 8C STY abs + "0000" & "000000" & writeAbs & aluInA & aluInp, -- 8D STA abs + "0000" & "000000" & writeAbs & aluInX & aluInp, -- 8E STX abs + "0000" & "000000" & writeAbs & aluInAX & aluInp, -- 8F iSAX abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- 90 BCC + "0000" & "000000" & writeIndY & aluInA & aluInp, -- 91 STA (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- 92 *** JAM *** + "0000" & "000000" & writeIndY & aluInAXH & aluInp, -- 93 iAHX (zp),y + "0000" & "000000" & writeZpX & aluInY & aluInp, -- 94 STY zp,x + "0000" & "000000" & writeZpX & aluInA & aluInp, -- 95 STA zp,x + "0000" & "000000" & writeZpY & aluInX & aluInp, -- 96 STX zp,y + "0000" & "000000" & writeZpY & aluInAX & aluInp, -- 97 iSAX zp,y + "1000" & "100010" & implied & aluInY & aluInp, -- 98 TYA + "0000" & "000000" & writeAbsY & aluInA & aluInp, -- 99 STA abs,y + "0001" & "000000" & implied & aluInX & aluInp, -- 9A TXS + "0001" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9B iSHS abs,y + "0000" & "000000" & writeAbsX & aluInYH & aluInp, -- 9C iSHY abs,x + "0000" & "000000" & writeAbsX & aluInA & aluInp, -- 9D STA abs,x + "0000" & "000000" & writeAbsY & aluInXH & aluInp, -- 9E iSHX abs,y + "0000" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9F iAHX abs,y + -- AXYS NVDIZC addressing aluInput aluMode + "0010" & "100010" & immediate & aluInT & aluInp, -- A0 LDY imm + "1000" & "100010" & readIndX & aluInT & aluInp, -- A1 LDA (zp,x) + "0100" & "100010" & immediate & aluInT & aluInp, -- A2 LDX imm + "1100" & "100010" & readIndX & aluInT & aluInp, -- A3 LAX (zp,x) + "0010" & "100010" & readZp & aluInT & aluInp, -- A4 LDY zp + "1000" & "100010" & readZp & aluInT & aluInp, -- A5 LDA zp + "0100" & "100010" & readZp & aluInT & aluInp, -- A6 LDX zp + "1100" & "100010" & readZp & aluInT & aluInp, -- A7 iLAX zp + "0010" & "100010" & implied & aluInA & aluInp, -- A8 TAY + "1000" & "100010" & immediate & aluInT & aluInp, -- A9 LDA imm + "0100" & "100010" & implied & aluInA & aluInp, -- AA TAX + "1100" & "100010" & immediate & aluInET & aluInp, -- AB iLXA imm + "0010" & "100010" & readAbs & aluInT & aluInp, -- AC LDY abs + "1000" & "100010" & readAbs & aluInT & aluInp, -- AD LDA abs + "0100" & "100010" & readAbs & aluInT & aluInp, -- AE LDX abs + "1100" & "100010" & readAbs & aluInT & aluInp, -- AF iLAX abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- B0 BCS + "1000" & "100010" & readIndY & aluInT & aluInp, -- B1 LDA (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- B2 *** JAM *** + "1100" & "100010" & readIndY & aluInT & aluInp, -- B3 iLAX (zp),y + "0010" & "100010" & readZpX & aluInT & aluInp, -- B4 LDY zp,x + "1000" & "100010" & readZpX & aluInT & aluInp, -- B5 LDA zp,x + "0100" & "100010" & readZpY & aluInT & aluInp, -- B6 LDX zp,y + "1100" & "100010" & readZpY & aluInT & aluInp, -- B7 iLAX zp,y + "0000" & "010000" & implied & aluInClr & aluFlg, -- B8 CLV + "1000" & "100010" & readAbsY & aluInT & aluInp, -- B9 LDA abs,y + "0100" & "100010" & implied & aluInS & aluInp, -- BA TSX + "1101" & "100010" & readAbsY & aluInST & aluInp, -- BB iLAS abs,y + "0010" & "100010" & readAbsX & aluInT & aluInp, -- BC LDY abs,x + "1000" & "100010" & readAbsX & aluInT & aluInp, -- BD LDA abs,x + "0100" & "100010" & readAbsY & aluInT & aluInp, -- BE LDX abs,y + "1100" & "100010" & readAbsY & aluInT & aluInp, -- BF iLAX abs,y + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "100011" & immediate & aluInT & aluCpy, -- C0 CPY imm + "0000" & "100011" & readIndX & aluInT & aluCmp, -- C1 CMP (zp,x) + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 iNOP imm + "0000" & "100011" & rmwIndX & aluInT & aluDcp, -- C3 iDCP (zp,x) + "0000" & "100011" & readZp & aluInT & aluCpy, -- C4 CPY zp + "0000" & "100011" & readZp & aluInT & aluCmp, -- C5 CMP zp + "0000" & "100010" & rmwZp & aluInT & aluDec, -- C6 DEC zp + "0000" & "100011" & rmwZp & aluInT & aluDcp, -- C7 iDCP zp + "0010" & "100010" & implied & aluInY & aluInc, -- C8 INY + "0000" & "100011" & immediate & aluInT & aluCmp, -- C9 CMP imm + "0100" & "100010" & implied & aluInX & aluDec, -- CA DEX + "0100" & "100011" & immediate & aluInT & aluSbx, -- CB SBX imm + "0000" & "100011" & readAbs & aluInT & aluCpy, -- CC CPY abs + "0000" & "100011" & readAbs & aluInT & aluCmp, -- CD CMP abs + "0000" & "100010" & rmwAbs & aluInT & aluDec, -- CE DEC abs + "0000" & "100011" & rmwAbs & aluInT & aluDcp, -- CF iDCP abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- D0 BNE + "0000" & "100011" & readIndY & aluInT & aluCmp, -- D1 CMP (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- D2 *** JAM *** + "0000" & "100011" & rmwIndY & aluInT & aluDcp, -- D3 iDCP (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- D4 iNOP zp,x + "0000" & "100011" & readZpX & aluInT & aluCmp, -- D5 CMP zp,x + "0000" & "100010" & rmwZpX & aluInT & aluDec, -- D6 DEC zp,x + "0000" & "100011" & rmwZpX & aluInT & aluDcp, -- D7 iDCP zp,x + "0000" & "001000" & implied & aluInClr & aluXXX, -- D8 CLD + "0000" & "100011" & readAbsY & aluInT & aluCmp, -- D9 CMP abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- DA iNOP implied + "0000" & "100011" & rmwAbsY & aluInT & aluDcp, -- DB iDCP abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- DC iNOP abs,x + "0000" & "100011" & readAbsX & aluInT & aluCmp, -- DD CMP abs,x + "0000" & "100010" & rmwAbsX & aluInT & aluDec, -- DE DEC abs,x + "0000" & "100011" & rmwAbsX & aluInT & aluDcp, -- DF iDCP abs,x + -- AXYS NVDIZC addressing aluInput aluMode + "0000" & "100011" & immediate & aluInT & aluCpx, -- E0 CPX imm + "1000" & "110011" & readIndX & aluInT & aluSbc, -- E1 SBC (zp,x) + "0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 iNOP imm + "1000" & "110011" & rmwIndX & aluInT & aluIsc, -- E3 iISC (zp,x) + "0000" & "100011" & readZp & aluInT & aluCpx, -- E4 CPX zp + "1000" & "110011" & readZp & aluInT & aluSbc, -- E5 SBC zp + "0000" & "100010" & rmwZp & aluInT & aluInc, -- E6 INC zp + "1000" & "110011" & rmwZp & aluInT & aluIsc, -- E7 iISC zp + "0100" & "100010" & implied & aluInX & aluInc, -- E8 INX + "1000" & "110011" & immediate & aluInT & aluSbc, -- E9 SBC imm + "0000" & "000000" & implied & aluInXXX & aluXXX, -- EA NOP + "1000" & "110011" & immediate & aluInT & aluSbc, -- EB SBC imm (illegal opc) + "0000" & "100011" & readAbs & aluInT & aluCpx, -- EC CPX abs + "1000" & "110011" & readAbs & aluInT & aluSbc, -- ED SBC abs + "0000" & "100010" & rmwAbs & aluInT & aluInc, -- EE INC abs + "1000" & "110011" & rmwAbs & aluInT & aluIsc, -- EF iISC abs + "0000" & "000000" & relative & aluInXXX & aluXXX, -- F0 BEQ + "1000" & "110011" & readIndY & aluInT & aluSbc, -- F1 SBC (zp),y + "----" & "------" & xxxxxxxx & aluInXXX & aluXXX, -- F2 *** JAM *** + "1000" & "110011" & rmwIndY & aluInT & aluIsc, -- F3 iISC (zp),y + "0000" & "000000" & readZpX & aluInXXX & aluXXX, -- F4 iNOP zp,x + "1000" & "110011" & readZpX & aluInT & aluSbc, -- F5 SBC zp,x + "0000" & "100010" & rmwZpX & aluInT & aluInc, -- F6 INC zp,x + "1000" & "110011" & rmwZpX & aluInT & aluIsc, -- F7 iISC zp,x + "0000" & "001000" & implied & aluInSet & aluXXX, -- F8 SED + "1000" & "110011" & readAbsY & aluInT & aluSbc, -- F9 SBC abs,y + "0000" & "000000" & implied & aluInXXX & aluXXX, -- FA iNOP implied + "1000" & "110011" & rmwAbsY & aluInT & aluIsc, -- FB iISC abs,y + "0000" & "000000" & readAbsX & aluInXXX & aluXXX, -- FC iNOP abs,x + "1000" & "110011" & readAbsX & aluInT & aluSbc, -- FD SBC abs,x + "0000" & "100010" & rmwAbsX & aluInT & aluInc, -- FE INC abs,x + "1000" & "110011" & rmwAbsX & aluInT & aluIsc -- FF iISC abs,x + ); + signal opcInfo : decodedBitsDef; + signal nextOpcInfo : decodedBitsDef; -- Next opcode (decoded) + signal nextOpcInfoReg : decodedBitsDef; -- Next opcode (decoded) pipelined + signal theOpcode : unsigned(7 downto 0); + signal nextOpcode : unsigned(7 downto 0); + +-- Program counter + signal PC : unsigned(15 downto 0); -- Program counter + +-- Address generation + type nextAddrDef is ( + nextAddrHold, + nextAddrIncr, + nextAddrIncrL, -- Increment low bits only (zeropage accesses) + nextAddrIncrH, -- Increment high bits only (page-boundary) + nextAddrDecrH, -- Decrement high bits (branch backwards) + nextAddrPc, + nextAddrIrq, + nextAddrReset, + nextAddrAbs, + nextAddrAbsIndexed, + nextAddrZeroPage, + nextAddrZPIndexed, + nextAddrStack, + nextAddrRelative + ); + signal nextAddr : nextAddrDef; + signal myAddr : unsigned(15 downto 0); + signal myAddrIncr : unsigned(15 downto 0); + signal myAddrIncrH : unsigned(7 downto 0); + signal myAddrDecrH : unsigned(7 downto 0); + signal theWe : std_logic; + + signal irqActive : std_logic; + +-- Output register + signal doReg : unsigned(7 downto 0); + +-- Buffer register + signal T : unsigned(7 downto 0); + +-- General registers + signal A: unsigned(7 downto 0); -- Accumulator + signal X: unsigned(7 downto 0); -- Index X + signal Y: unsigned(7 downto 0); -- Index Y + signal S: unsigned(7 downto 0); -- stack pointer + +-- Status register + signal C: std_logic; -- Carry + signal Z: std_logic; -- Zero flag + signal I: std_logic; -- Interrupt flag + signal D: std_logic; -- Decimal mode + signal V: std_logic; -- Overflow + signal N: std_logic; -- Negative + +-- ALU + -- ALU input + signal aluInput : unsigned(7 downto 0); + signal aluCmpInput : unsigned(7 downto 0); + -- ALU output + signal aluRegisterOut : unsigned(7 downto 0); + signal aluRmwOut : unsigned(7 downto 0); + signal aluC : std_logic; + signal aluZ : std_logic; + signal aluV : std_logic; + signal aluN : std_logic; + -- Pipeline registers + signal aluInputReg : unsigned(7 downto 0); + signal aluCmpInputReg : unsigned(7 downto 0); + signal aluRmwReg : unsigned(7 downto 0); + signal aluNineReg : unsigned(7 downto 0); + signal aluCReg : std_logic; + signal aluZReg : std_logic; + signal aluVReg : std_logic; + signal aluNReg : std_logic; + +-- Indexing + signal indexOut : unsigned(8 downto 0); + +begin +processAluInput: process(clk, opcInfo, A, X, Y, T, S) + variable temp : unsigned(7 downto 0); + begin + temp := (others => '1'); + if opcInfo(opcInA) = '1' then + temp := temp and A; + end if; + if opcInfo(opcInE) = '1' then + temp := temp and (A or X"EE"); + end if; + if opcInfo(opcInX) = '1' then + temp := temp and X; + end if; + if opcInfo(opcInY) = '1' then + temp := temp and Y; + end if; + if opcInfo(opcInS) = '1' then + temp := temp and S; + end if; + if opcInfo(opcInT) = '1' then + temp := temp and T; + end if; + if opcInfo(opcInClear) = '1' then + temp := (others => '0'); + end if; + if rising_edge(clk) then + aluInputReg <= temp; + end if; + + aluInput <= temp; + if pipelineAluMux then + aluInput <= aluInputReg; + end if; + end process; + +processCmpInput: process(clk, opcInfo, A, X, Y) + variable temp : unsigned(7 downto 0); + begin + temp := (others => '1'); + if opcInfo(opcInCmp) = '1' then + temp := temp and A; + end if; + if opcInfo(opcInCpx) = '1' then + temp := temp and X; + end if; + if opcInfo(opcInCpy) = '1' then + temp := temp and Y; + end if; + if rising_edge(clk) then + aluCmpInputReg <= temp; + end if; + + aluCmpInput <= temp; + if pipelineAluMux then + aluCmpInput <= aluCmpInputReg; + end if; + end process; + + -- ALU consists of two parts + -- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL + -- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA + -- Some instructions are both RMW and accumulator so for most + -- instructions the rmw results are routed through accu alu too. +processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, D, I, Z, C) + variable lowBits: unsigned(5 downto 0); + variable nineBits: unsigned(8 downto 0); + variable rmwBits: unsigned(8 downto 0); + + variable varC : std_logic; + variable varZ : std_logic; + variable varV : std_logic; + variable varN : std_logic; + begin + lowBits := (others => '-'); + nineBits := (others => '-'); + rmwBits := (others => '-'); + varV := aluInput(6); -- Default for BIT / PLP / RTI + + -- Shift unit + case opcInfo(aluMode1From to aluMode1To) is + when aluModeInp => + rmwBits := C & aluInput; + when aluModeP => + rmwBits := C & N & V & '1' & (not irqActive) & D & I & Z & C; + when aluModeInc => + rmwBits := C & (aluInput + 1); + when aluModeDec => + rmwBits := C & (aluInput - 1); + when aluModeAsl => + rmwBits := aluInput & "0"; + when aluModeFlg => + rmwBits := aluInput(0) & aluInput; + when aluModeLsr => + rmwBits := aluInput(0) & "0" & aluInput(7 downto 1); + when aluModeRol => + rmwBits := aluInput & C; + when aluModeRoR => + rmwBits := aluInput(0) & C & aluInput(7 downto 1); + when aluModeAnc => + rmwBits := (aluInput(7) and A(7)) & aluInput; + when others => + rmwBits := C & aluInput; + end case; + + -- ALU + case opcInfo(aluMode2From to aluMode2To) is + when aluModeAdc => + lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1"); + ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8)); + when aluModeSbc => + lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1"); + ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8)); + when aluModeCmp => + ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001"; + when aluModeAnd => + ninebits := rmwBits(8) & (A and rmwBits(7 downto 0)); + when aluModeEor => + ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0)); + when aluModeOra => + ninebits := rmwBits(8) & (A or rmwBits(7 downto 0)); + when others => + ninebits := rmwBits; + end case; + + if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then + varZ := rmwBits(1); + elsif ninebits(7 downto 0) = X"00" then + varZ := '1'; + else + varZ := '0'; + end if; + + case opcInfo(aluMode2From to aluMode2To) is + when aluModeAdc => + -- decimal mode low bits correction, is done after setting Z flag. + if D = '1' then + if lowBits(5 downto 1) > 9 then + ninebits(3 downto 0) := ninebits(3 downto 0) + 6; + if lowBits(5) = '0' then + ninebits(8 downto 4) := ninebits(8 downto 4) + 1; + end if; + end if; + end if; + when others => + null; + end case; + + if (opcInfo(aluMode1From to aluMode1To) = aluModeBit) + or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then + varN := rmwBits(7); + else + varN := nineBits(7); + end if; + varC := ninebits(8); + if opcInfo(aluMode2From to aluMode2To) = aluModeArr then + varC := aluInput(7); + varV := aluInput(7) xor aluInput(6); + end if; + + case opcInfo(aluMode2From to aluMode2To) is + when aluModeAdc => + -- decimal mode high bits correction, is done after setting Z and N flags + varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7)); + if D = '1' then + if ninebits(8 downto 4) > 9 then + ninebits(8 downto 4) := ninebits(8 downto 4) + 6; + varC := '1'; + end if; + end if; + when aluModeSbc => + varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7)); + if D = '1' then + -- Check for borrow (lower 4 bits) + if lowBits(5) = '0' then + ninebits(3 downto 0) := ninebits(3 downto 0) - 6; + end if; + -- Check for borrow (upper 4 bits) + if ninebits(8) = '0' then + ninebits(8 downto 4) := ninebits(8 downto 4) - 6; + end if; + end if; + when aluModeArr => + if D = '1' then + if (("0" & aluInput(3 downto 0)) + ("0000" & aluInput(0))) > 5 then + ninebits(3 downto 0) := ninebits(3 downto 0) + 6; + end if; + if (("0" & aluInput(7 downto 4)) + ("0000" & aluInput(4))) > 5 then + ninebits(8 downto 4) := ninebits(8 downto 4) + 6; + varC := '1'; + else + varC := '0'; + end if; + end if; + when others => + null; + end case; + + if rising_edge(clk) then + aluRmwReg <= rmwBits(7 downto 0); + aluNineReg <= ninebits(7 downto 0); + aluCReg <= varC; + aluZReg <= varZ; + aluVReg <= varV; + aluNReg <= varN; + end if; + + aluRmwOut <= rmwBits(7 downto 0); + aluRegisterOut <= ninebits(7 downto 0); + aluC <= varC; + aluZ <= varZ; + aluV <= varV; + aluN <= varN; + if pipelineAluOut then + aluRmwOut <= aluRmwReg; + aluRegisterOut <= aluNineReg; + aluC <= aluCReg; + aluZ <= aluZReg; + aluV <= aluVReg; + aluN <= aluNReg; + end if; + end process; + +calcInterrupt: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + if theCpuCycle = cycleStack4 + or reset = '1' then + nmiReg <= '1'; + end if; + + if nextCpuCycle /= cycleBranchTaken + and nextCpuCycle /= opcodeFetch then + irqReg <= irq_n; + nmiEdge <= nmi_n; + if (nmiEdge = '1') and (nmi_n = '0') then + nmiReg <= '0'; + end if; + end if; + -- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ. + -- Presumably this is done in the real 6502/6510 to prevent a double IRQ. + processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ)); + end if; + end if; + end process; + +calcNextOpcode: process(clk, di, reset, processIrq) + variable myNextOpcode : unsigned(7 downto 0); + begin + -- Next opcode is read from input unless a reset or IRQ is pending. + myNextOpcode := di; + if reset = '1' then + myNextOpcode := X"4C"; + elsif processIrq = '1' then + myNextOpcode := X"00"; + end if; + + nextOpcode <= myNextOpcode; + end process; + + nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode)); + process(clk) + begin + if rising_edge(clk) then + nextOpcInfoReg <= nextOpcInfo; + end if; + end process; + + -- Read bits and flags from opcodeInfoTable and store in opcInfo. + -- This info is used to control the execution of the opcode. +calcOpcInfo: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + if (reset = '1') or (theCpuCycle = opcodeFetch) then + opcInfo <= nextOpcInfo; + if pipelineOpcode then + opcInfo <= nextOpcInfoReg; + end if; + end if; + end if; + end if; + end process; + +calcTheOpcode: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + if theCpuCycle = opcodeFetch then + irqActive <= '0'; + if processIrq = '1' then + irqActive <= '1'; + end if; + -- Fetch opcode + theOpcode <= nextOpcode; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- State machine +-- ----------------------------------------------------------------------- + process(enable, theCpuCycle, opcInfo) + begin + updateRegisters <= false; + if enable = '1' then + if opcInfo(opcRti) = '1' then + if theCpuCycle = cycleRead then + updateRegisters <= true; + end if; + elsif theCpuCycle = opcodeFetch then + updateRegisters <= true; + end if; + end if; + end process; + + debugOpcode <= theOpcode; + process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + theCpuCycle <= nextCpuCycle; + end if; + if reset = '1' then + theCpuCycle <= cycle2; + end if; + end if; + end process; + + -- Determine the next cpu cycle. After the last cycle we always + -- go to opcodeFetch to get the next opcode. +calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, N, V, C, Z) + begin + nextCpuCycle <= opcodeFetch; + + case theCpuCycle is + when opcodeFetch => + nextCpuCycle <= cycle2; + when cycle2 => + if opcInfo(opcBranch) = '1' then + if (N = theOpcode(5) and theOpcode(7 downto 6) = "00") + or (V = theOpcode(5) and theOpcode(7 downto 6) = "01") + or (C = theOpcode(5) and theOpcode(7 downto 6) = "10") + or (Z = theOpcode(5) and theOpcode(7 downto 6) = "11") then + -- Branch condition is true + nextCpuCycle <= cycleBranchTaken; + end if; + elsif (opcInfo(opcStackUp) = '1') then + nextCpuCycle <= cycleStack1; + elsif opcInfo(opcStackAddr) = '1' + and opcInfo(opcStackData) = '1' then + nextCpuCycle <= cycleStack2; + elsif opcInfo(opcStackAddr) = '1' then + nextCpuCycle <= cycleStack1; + elsif opcInfo(opcStackData) = '1' then + nextCpuCycle <= cycleWrite; + elsif opcInfo(opcAbsolute) = '1' then + nextCpuCycle <= cycle3; + elsif opcInfo(opcIndirect) = '1' then + if opcInfo(indexX) = '1' then + nextCpuCycle <= cyclePreIndirect; + else + nextCpuCycle <= cycleIndirect; + end if; + elsif opcInfo(opcZeroPage) = '1' then + if opcInfo(opcWrite) = '1' then + if (opcInfo(indexX) = '1') + or (opcInfo(indexY) = '1') then + nextCpuCycle <= cyclePreWrite; + else + nextCpuCycle <= cycleWrite; + end if; + else + if (opcInfo(indexX) = '1') + or (opcInfo(indexY) = '1') then + nextCpuCycle <= cyclePreRead; + else + nextCpuCycle <= cycleRead2; + end if; + end if; + elsif opcInfo(opcJump) = '1' then + nextCpuCycle <= cycleJump; + end if; + when cycle3 => + nextCpuCycle <= cycleRead; + if opcInfo(opcWrite) = '1' then + if (opcInfo(indexX) = '1') + or (opcInfo(indexY) = '1') then + nextCpuCycle <= cyclePreWrite; + else + nextCpuCycle <= cycleWrite; + end if; + end if; + if (opcInfo(opcIndirect) = '1') + and (opcInfo(indexX) = '1') then + if opcInfo(opcWrite) = '1' then + nextCpuCycle <= cycleWrite; + else + nextCpuCycle <= cycleRead2; + end if; + end if; + when cyclePreIndirect => + nextCpuCycle <= cycleIndirect; + when cycleIndirect => + nextCpuCycle <= cycle3; + when cycleBranchTaken => + if indexOut(8) /= T(7) then + -- Page boundary crossing during branch. + nextCpuCycle <= cycleBranchPage; + end if; + when cyclePreRead => + if opcInfo(opcZeroPage) = '1' then + nextCpuCycle <= cycleRead2; + end if; + when cycleRead => + if opcInfo(opcJump) = '1' then + nextCpuCycle <= cycleJump; + elsif indexOut(8) = '1' then + -- Page boundary crossing while indexed addressing. + nextCpuCycle <= cycleRead2; + elsif opcInfo(opcRmw) = '1' then + nextCpuCycle <= cycleRmw; + if opcInfo(indexX) = '1' + or opcInfo(indexY) = '1' then + -- 6510 needs extra cycle for indexed addressing + -- combined with RMW indexing + nextCpuCycle <= cycleRead2; + end if; + end if; + when cycleRead2 => + if opcInfo(opcRmw) = '1' then + nextCpuCycle <= cycleRmw; + end if; + when cycleRmw => + nextCpuCycle <= cycleWrite; + when cyclePreWrite => + nextCpuCycle <= cycleWrite; + when cycleStack1 => + nextCpuCycle <= cycleRead; + if opcInfo(opcStackAddr) = '1' then + nextCpuCycle <= cycleStack2; + end if; + when cycleStack2 => + nextCpuCycle <= cycleStack3; + if opcInfo(opcRti) = '1' then + nextCpuCycle <= cycleRead; + end if; + if opcInfo(opcStackData) = '0' + and opcInfo(opcStackUp) = '1' then + nextCpuCycle <= cycleJump; + end if; + when cycleStack3 => + nextCpuCycle <= cycleRead; + if opcInfo(opcStackData) = '0' + or opcInfo(opcStackUp) = '1' then + nextCpuCycle <= cycleJump; + elsif opcInfo(opcStackAddr) = '1' then + nextCpuCycle <= cycleStack4; + end if; + when cycleStack4 => + nextCpuCycle <= cycleRead; + when cycleJump => + if opcInfo(opcIncrAfter) = '1' then + -- Insert extra cycle + nextCpuCycle <= cycleEnd; + end if; + when others => + null; + end case; + end process; + +-- ----------------------------------------------------------------------- +-- T register +-- ----------------------------------------------------------------------- +calcT: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + case theCpuCycle is + when cycle2 => + T <= di; + when cycleStack1 | cycleStack2 => + if opcInfo(opcStackUp) = '1' then + -- Read from stack + T <= di; + end if; + when cycleIndirect | cycleRead | cycleRead2 => + T <= di; + when others => + null; + end case; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- A register +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateA) = '1' then + A <= aluRegisterOut; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- X register +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateX) = '1' then + X <= aluRegisterOut; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Y register +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateY) = '1' then + Y <= aluRegisterOut; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- C flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateC) = '1' then + C <= aluC; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Z flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateZ) = '1' then + Z <= aluZ; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- I flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateI) = '1' then + I <= aluInput(2); + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- D flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateD) = '1' then + D <= aluInput(3); + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- V flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateV) = '1' then + V <= aluV; + end if; + end if; + if enable = '1' then + if soReg = '1' and so_n = '0' then + V <= '1'; + end if; + soReg <= so_n; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- N flag +-- ----------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if updateRegisters then + if opcInfo(opcUpdateN) = '1' then + N <= aluN; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Stack pointer +-- ----------------------------------------------------------------------- + process(clk) + variable sIncDec : unsigned(7 downto 0); + variable updateFlag : boolean; + begin + if rising_edge(clk) then + + if opcInfo(opcStackUp) = '1' then + sIncDec := S + 1; + else + sIncDec := S - 1; + end if; + + if enable = '1' then + updateFlag := false; + case nextCpuCycle is + when cycleStack1 => + if (opcInfo(opcStackUp) = '1') + or (opcInfo(opcStackData) = '1') then + updateFlag := true; + end if; + when cycleStack2 => + updateFlag := true; + when cycleStack3 => + updateFlag := true; + when cycleStack4 => + updateFlag := true; + when cycleRead => + if opcInfo(opcRti) = '1' then + updateFlag := true; + end if; + when cycleWrite => + if opcInfo(opcStackData) = '1' then + updateFlag := true; + end if; + when others => + null; + end case; + if updateFlag then + S <= sIncDec; + end if; + end if; + if updateRegisters then + if opcInfo(opcUpdateS) = '1' then + S <= aluRegisterOut; + end if; + end if; + end if; + end process; + +-- ----------------------------------------------------------------------- +-- Data out +-- ----------------------------------------------------------------------- +--calcDo: process(cpuNo, theCpuCycle, aluOut, PC, T) +calcDo: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + doReg <= aluRmwOut; + if opcInfo(opcInH) = '1' then + -- For illegal opcodes SHA, SHX, SHY, SHS + doReg <= aluRmwOut and myAddrIncrH; + end if; + + case nextCpuCycle is + when cycleStack2 => + if opcInfo(opcIRQ) = '1' + and irqActive = '0' then + doReg <= myAddrIncr(15 downto 8); + else + doReg <= PC(15 downto 8); + end if; + when cycleStack3 => + doReg <= PC(7 downto 0); + when cycleRmw => +-- do <= T; -- Read-modify-write write old value first. + doReg <= di; -- Read-modify-write write old value first. + when others => null; + end case; + end if; + end if; + end process; + do <= doReg; + + + +-- ----------------------------------------------------------------------- +-- Write enable +-- ----------------------------------------------------------------------- +calcWe: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + theWe <= '0'; + case nextCpuCycle is + when cycleStack1 => + if opcInfo(opcStackUp) = '0' + and ((opcInfo(opcStackAddr) = '0') + or (opcInfo(opcStackData) = '1')) then + theWe <= '1'; + end if; + when cycleStack2 | cycleStack3 | cycleStack4 => + if opcInfo(opcStackUp) = '0' then + theWe <= '1'; + end if; + when cycleRmw => + theWe <= '1'; + when cycleWrite => + theWe <= '1'; + when others => + null; + end case; + end if; + end if; + end process; + we <= theWe; + +-- ----------------------------------------------------------------------- +-- Program counter +-- ----------------------------------------------------------------------- +calcPC: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + case theCpuCycle is + when opcodeFetch => + PC <= myAddr; + when cycle2 => + if irqActive = '0' then + if opcInfo(opcSecondByte) = '1' then + PC <= myAddrIncr; + else + PC <= myAddr; + end if; + end if; + when cycle3 => + if opcInfo(opcAbsolute) = '1' then + PC <= myAddrIncr; + end if; + when others => + null; + end case; + end if; + end if; + end process; + debugPc <= PC; + +-- ----------------------------------------------------------------------- +-- Address generation +-- ----------------------------------------------------------------------- +calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset) + begin + nextAddr <= nextAddrIncr; + case theCpuCycle is + when cycle2 => + if opcInfo(opcStackAddr) = '1' + or opcInfo(opcStackData) = '1' then + nextAddr <= nextAddrStack; + elsif opcInfo(opcAbsolute) = '1' then + nextAddr <= nextAddrIncr; + elsif opcInfo(opcZeroPage) = '1' then + nextAddr <= nextAddrZeroPage; + elsif opcInfo(opcIndirect) = '1' then + nextAddr <= nextAddrZeroPage; + elsif opcInfo(opcSecondByte) = '1' then + nextAddr <= nextAddrIncr; + else + nextAddr <= nextAddrHold; + end if; + when cycle3 => + if (opcInfo(opcIndirect) = '1') + and (opcInfo(indexX) = '1') then + nextAddr <= nextAddrAbs; + else + nextAddr <= nextAddrAbsIndexed; + end if; + when cyclePreIndirect => + nextAddr <= nextAddrZPIndexed; + when cycleIndirect => + nextAddr <= nextAddrIncrL; + when cycleBranchTaken => + nextAddr <= nextAddrRelative; + when cycleBranchPage => + if T(7) = '0' then + nextAddr <= nextAddrIncrH; + else + nextAddr <= nextAddrDecrH; + end if; + when cyclePreRead => + nextAddr <= nextAddrZPIndexed; + when cycleRead => + nextAddr <= nextAddrPc; + if opcInfo(opcJump) = '1' then + -- Emulate 6510 bug, jmp(xxFF) fetches from same page. + -- Replace with nextAddrIncr if emulating 65C02 or later cpu. + nextAddr <= nextAddrIncrL; + elsif indexOut(8) = '1' then + nextAddr <= nextAddrIncrH; + elsif opcInfo(opcRmw) = '1' then + nextAddr <= nextAddrHold; + end if; + when cycleRead2 => + nextAddr <= nextAddrPc; + if opcInfo(opcRmw) = '1' then + nextAddr <= nextAddrHold; + end if; + when cycleRmw => + nextAddr <= nextAddrHold; + when cyclePreWrite => + nextAddr <= nextAddrHold; + if opcInfo(opcZeroPage) = '1' then + nextAddr <= nextAddrZPIndexed; + elsif indexOut(8) = '1' then + nextAddr <= nextAddrIncrH; + end if; + when cycleWrite => + nextAddr <= nextAddrPc; + when cycleStack1 => + nextAddr <= nextAddrStack; + when cycleStack2 => + nextAddr <= nextAddrStack; + when cycleStack3 => + nextAddr <= nextAddrStack; + if opcInfo(opcStackData) = '0' then + nextAddr <= nextAddrPc; + end if; + when cycleStack4 => + nextAddr <= nextAddrIrq; + when cycleJump => + nextAddr <= nextAddrAbs; + when others => + null; + end case; + if reset = '1' then + nextAddr <= nextAddrReset; + end if; + end process; + +indexAlu: process(opcInfo, myAddr, T, X, Y) + begin + if opcInfo(indexX) = '1' then + indexOut <= (B"0" & T) + (B"0" & X); + elsif opcInfo(indexY) = '1' then + indexOut <= (B"0" & T) + (B"0" & Y); + elsif opcInfo(opcBranch) = '1' then + indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0)); + else + indexOut <= B"0" & T; + end if; + end process; + +calcAddr: process(clk) + begin + if rising_edge(clk) then + if enable = '1' then + case nextAddr is + when nextAddrIncr => myAddr <= myAddrIncr; + when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0); + when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH; + when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH; + when nextAddrPc => myAddr <= PC; + when nextAddrIrq => + myAddr <= X"FFFE"; + if nmiReg = '0' then + myAddr <= X"FFFA"; + end if; + when nextAddrReset => myAddr <= X"FFFC"; + when nextAddrAbs => myAddr <= di & T; + when nextAddrAbsIndexed => myAddr <= di & indexOut(7 downto 0); + when nextAddrZeroPage => myAddr <= "00000000" & di; + when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0); + when nextAddrStack => myAddr <= "00000001" & S; + when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0); + when others => null; + end case; + end if; + end if; + end process; + + myAddrIncr <= myAddr + 1; + myAddrIncrH <= myAddr(15 downto 8) + 1; + myAddrDecrH <= myAddr(15 downto 8) - 1; + + addr <= myAddr; + + debugA <= A; + debugX <= X; + debugY <= Y; + debugS <= S; + +end architecture; + + diff --git a/disk_ii.vhd b/disk_ii.vhd new file mode 100644 index 0000000..30f87d1 --- /dev/null +++ b/disk_ii.vhd @@ -0,0 +1,288 @@ +------------------------------------------------------------------------------- +-- +-- Disk II emulator +-- +-- This is read-only and only feeds "pre-nibblized" data to the processor +-- It has a single-track buffer and only supports one drive (1). +-- +-- Stephen A. Edwards, sedwards@cs.columbia.edu +-- +------------------------------------------------------------------------------- +-- +-- Each track is represented as 0x1A00 bytes +-- Each disk image consists of 35 * 0x1A00 bytes = 0x38A00 (227.5 K) +-- +-- X = $60 for slot 6 +-- +-- Off On +-- C080,X C081,X Phase 0 Head Stepper Motor Control +-- C082,X C083,X Phase 1 +-- C084,X C085,X Phase 2 +-- C086,X C087,X Phase 3 +-- C088,X C089,X Motor On +-- C08A,X C08B,X Select Drive 2 (select drive 1 when off) +-- C08C,X C08D,X Q6 (Shift/load?) +-- C08E,X C08F,X Q7 (Write request to drive) +-- +-- +-- Q7 Q6 +-- 0 0 Read +-- 0 1 Sense write protect +-- 1 0 Write +-- 1 1 Load Write Latch +-- +-- Reading a byte: +-- LDA $C08E,X set read mode +-- ... +-- READ LDA $C08C,X +-- BPL READ +-- +-- Sense write protect: +-- LDA $C08D,X +-- LDA $C08E,X +-- BMI PROTECTED +-- +-- Writing +-- STA $C08F,X set write mode +-- .. +-- LDA DATA +-- STA $C08D,X load byte to write +-- STA $C08C,X write byte to disk +-- +-- Data bytes must be written in 32 cycle loops. +-- +-- There are 70 phases for the head stepper and and 35 tracks, +-- i.e., two phase changes per track. +-- +-- The disk spins at 300 rpm; one new bit arrives every 4 us +-- The processor's clock is 1 MHz = 1 us, so it takes 8 * 4 = 32 cycles +-- for a new byte to arrive +-- +-- This corresponds to dividing the 2 MHz signal by 64 to get the byte clock +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity disk_ii is + port ( + CLK_14M : in std_logic; + CLK_2M : in std_logic; + PRE_PHASE_ZERO : in std_logic; + IO_SELECT : in std_logic; -- e.g., C600 - C6FF ROM + DEVICE_SELECT : in std_logic; -- e.g., C0E0 - C0EF I/O locations + RESET : in std_logic; + A : in unsigned(15 downto 0); + D_IN : in unsigned(7 downto 0); -- From 6502 + D_OUT : out unsigned(7 downto 0); -- To 6502 + TRACK : out unsigned(5 downto 0); -- Current track (0-34) + track_addr : out unsigned(13 downto 0); + D1_ACTIVE : out std_logic; -- Disk 1 motor on + D2_ACTIVE : out std_logic; -- Disk 2 motor on + ram_write_addr : in unsigned(12 downto 0); -- Address for track RAM + ram_di : in unsigned(7 downto 0); -- Data to track RAM + ram_we : in std_logic -- RAM write enable + ); +end disk_ii; + +architecture rtl of disk_ii is + + signal motor_phase : std_logic_vector(3 downto 0); + signal drive_on : std_logic; + signal drive2_select : std_logic; + signal q6, q7 : std_logic; + + signal rom_dout : unsigned(7 downto 0); + + -- Current phase of the head. This is in half-steps to assign + -- a unique position to the case, say, when both phase 0 and phase 1 are + -- on simultaneously. phase(7 downto 2) is the track number + signal phase : unsigned(7 downto 0); -- 0 - 139 + + -- Storage for one track worth of data in "nibblized" form + type track_ram is array(0 to 6655) of unsigned(7 downto 0); + -- Double-ported RAM for holding a track + signal track_memory : track_ram; + signal ram_do : unsigned(7 downto 0); + + -- Lower bit indicates whether disk data is "valid" or not + -- RAM address is track_byte_addr(14 downto 1) + -- This makes it look to the software like new data is constantly + -- being read into the shift register, which indicates the data is + -- not yet ready. + signal track_byte_addr : unsigned(14 downto 0); + signal read_disk : std_logic; -- When C08C accessed + +begin + + interpret_io : process (CLK_2M) + begin + if rising_edge(CLK_2M) then + if reset = '1' then + motor_phase <= (others => '0'); + drive_on <= '0'; + drive2_select <= '0'; + q6 <= '0'; + q7 <= '0'; + else + if PRE_PHASE_ZERO = '1' and DEVICE_SELECT = '1' then + if A(3) = '0' then -- C080 - C087 + motor_phase(TO_INTEGER(A(2 downto 1))) <= A(0); + else + case A(2 downto 1) is + when "00" => drive_on <= A(0); -- C088 - C089 + when "01" => drive2_select <= A(0); -- C08A - C08B + when "10" => q6 <= A(0); -- C08C - C08D + when "11" => q7 <= A(0); -- C08E - C08F + when others => null; + end case; + end if; + end if; + end if; + end if; + end process; + + D1_ACTIVE <= drive_on and not drive2_select; + D2_ACTIVE <= drive_on and drive2_select; + + -- There are two cases: + -- + -- Current phase is odd (between two poles) + -- | + -- V + -- -3-2-1 0 1 2 3 + -- X X X X + -- 0 1 2 3 + -- + -- + -- Current phase is even (under a pole) + -- | + -- V + -- -4-3-2-1 0 1 2 3 4 + -- X X X X X + -- 0 1 2 3 0 + -- + + update_phase : process (CLK_14M) + variable phase_change : integer; + variable new_phase : integer; + variable rel_phase : std_logic_vector(3 downto 0); + begin + if rising_edge(CLK_14M) then + if reset = '1' then + phase <= TO_UNSIGNED(70, 8); -- Deliberately odd to test reset + else + phase_change := 0; + new_phase := TO_INTEGER(phase); + rel_phase := motor_phase; + case phase(2 downto 1) is + when "00" => + rel_phase := rel_phase(1 downto 0) & rel_phase(3 downto 2); + when "01" => + rel_phase := rel_phase(2 downto 0) & rel_phase(3); + when "10" => null; + when "11" => + rel_phase := rel_phase(0) & rel_phase(3 downto 1); + when others => null; + end case; + + if phase(0) = '1' then -- Phase is odd + case rel_phase is + when "0000" => phase_change := 0; + when "0001" => phase_change := -3; + when "0010" => phase_change := -1; + when "0011" => phase_change := -2; + when "0100" => phase_change := 1; + when "0101" => phase_change := -1; + when "0110" => phase_change := 0; + when "0111" => phase_change := -1; + when "1000" => phase_change := 3; + when "1001" => phase_change := 0; + when "1010" => phase_change := 1; + when "1011" => phase_change := -3; + when "1111" => phase_change := 0; + when others => null; + end case; + else -- Phase is even + case rel_phase is + when "0000" => phase_change := 0; + when "0001" => phase_change := -2; + when "0010" => phase_change := 0; + when "0011" => phase_change := -1; + when "0100" => phase_change := 2; + when "0101" => phase_change := 0; + when "0110" => phase_change := 1; + when "0111" => phase_change := 0; + when "1000" => phase_change := 0; + when "1001" => phase_change := 1; + when "1010" => phase_change := 2; + when "1011" => phase_change := -2; + when "1111" => phase_change := 0; + when others => null; + end case; + end if; + + if new_phase + phase_change <= 0 then + new_phase := 0; + elsif new_phase + phase_change > 139 then + new_phase := 139; + else + new_phase := new_phase + phase_change; + end if; + phase <= TO_UNSIGNED(new_phase, 8); + end if; + end if; + end process; + + TRACK <= phase(7 downto 2); + + -- Dual-ported RAM holding the contents of the track + track_storage : process (CLK_14M) + begin + if rising_edge(CLK_14M) then + if ram_we = '1' then + track_memory(to_integer(ram_write_addr)) <= ram_di; + end if; + ram_do <= track_memory(to_integer(track_byte_addr(14 downto 1))); + end if; + end process; + + -- Go to the next byte when the disk is accessed or if the counter times out + read_head : process (CLK_2M) + variable byte_delay : unsigned(5 downto 0); -- Accounts for disk spin rate + begin + if rising_edge(CLK_2M) then + if reset = '1' then + track_byte_addr <= (others => '0'); + byte_delay := (others => '0'); + else + byte_delay := byte_delay - 1; + if (read_disk = '1' and PRE_PHASE_ZERO = '1') or byte_delay = 0 then + byte_delay := (others => '0'); + if track_byte_addr = X"33FE" then + track_byte_addr <= (others => '0'); + else + track_byte_addr <= track_byte_addr + 1; + end if; + end if; + end if; + end if; + end process; + + rom : entity work.disk_ii_rom port map ( + addr => A(7 downto 0), + clk => CLK_14M, + dout => rom_dout); + + read_disk <= '1' when DEVICE_SELECT = '1' and A(3 downto 0) = x"C" else + '0'; -- C08C + + D_OUT <= rom_dout when IO_SELECT = '1' else + ram_do when read_disk = '1' and track_byte_addr(0) = '0' else + (others => '0'); + + track_addr <= track_byte_addr(14 downto 1); + +end rtl; diff --git a/disk_ii_rom.vhd b/disk_ii_rom.vhd new file mode 100644 index 0000000..4711ada --- /dev/null +++ b/disk_ii_rom.vhd @@ -0,0 +1,58 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity disk_ii_rom is + port ( + addr : in unsigned(7 downto 0); + clk : in std_logic; + dout : out unsigned(7 downto 0)); +end disk_ii_rom; + +architecture rtl of disk_ii_rom is + type rom_array is array(0 to 255) of unsigned(7 downto 0); + + constant ROM : rom_array := ( + X"a2", X"20", X"a0", X"00", X"a2", X"03", X"86", X"3c", + X"8a", X"0a", X"24", X"3c", X"f0", X"10", X"05", X"3c", + X"49", X"ff", X"29", X"7e", X"b0", X"08", X"4a", X"d0", + X"fb", X"98", X"9d", X"56", X"03", X"c8", X"e8", X"10", + X"e5", X"20", X"58", X"ff", X"ba", X"bd", X"00", X"01", + X"0a", X"0a", X"0a", X"0a", X"85", X"2b", X"aa", X"bd", + X"8e", X"c0", X"bd", X"8c", X"c0", X"bd", X"8a", X"c0", + X"bd", X"89", X"c0", X"a0", X"50", X"bd", X"80", X"c0", + X"98", X"29", X"03", X"0a", X"05", X"2b", X"aa", X"bd", + X"81", X"c0", X"a9", X"56", X"20", X"a8", X"fc", X"88", + X"10", X"eb", X"85", X"26", X"85", X"3d", X"85", X"41", + X"a9", X"08", X"85", X"27", X"18", X"08", X"bd", X"8c", + X"c0", X"10", X"fb", X"49", X"d5", X"d0", X"f7", X"bd", + X"8c", X"c0", X"10", X"fb", X"c9", X"aa", X"d0", X"f3", + X"ea", X"bd", X"8c", X"c0", X"10", X"fb", X"c9", X"96", + X"f0", X"09", X"28", X"90", X"df", X"49", X"ad", X"f0", + X"25", X"d0", X"d9", X"a0", X"03", X"85", X"40", X"bd", + X"8c", X"c0", X"10", X"fb", X"2a", X"85", X"3c", X"bd", + X"8c", X"c0", X"10", X"fb", X"25", X"3c", X"88", X"d0", + X"ec", X"28", X"c5", X"3d", X"d0", X"be", X"a5", X"40", + X"c5", X"41", X"d0", X"b8", X"b0", X"b7", X"a0", X"56", + X"84", X"3c", X"bc", X"8c", X"c0", X"10", X"fb", X"59", + X"d6", X"02", X"a4", X"3c", X"88", X"99", X"00", X"03", + X"d0", X"ee", X"84", X"3c", X"bc", X"8c", X"c0", X"10", + X"fb", X"59", X"d6", X"02", X"a4", X"3c", X"91", X"26", + X"c8", X"d0", X"ef", X"bc", X"8c", X"c0", X"10", X"fb", + X"59", X"d6", X"02", X"d0", X"87", X"a0", X"00", X"a2", + X"56", X"ca", X"30", X"fb", X"b1", X"26", X"5e", X"00", + X"03", X"2a", X"5e", X"00", X"03", X"2a", X"91", X"26", + X"c8", X"d0", X"ee", X"e6", X"27", X"e6", X"3d", X"a5", + X"3d", X"cd", X"00", X"08", X"a6", X"2b", X"90", X"db", + X"4c", X"01", X"08", X"00", X"00", X"00", X"00", X"00"); + +begin + +process (clk) + begin + if rising_edge(clk) then + dout <= ROM(TO_INTEGER(addr)); + end if; + end process; + +end rtl; diff --git a/dsk2nib/dsk2nib.c b/dsk2nib/dsk2nib.c new file mode 100644 index 0000000..402a5a1 --- /dev/null +++ b/dsk2nib/dsk2nib.c @@ -0,0 +1,228 @@ +/*********************************************************************** + * + * Apple ][ .dsk file to .nib file format converter + * + * Stephen A. Edwards, sedwards@cs.columbia.edu + * + * Adapted from the "dsk2pdb" program supplied with the PalmApple/Appalm ][ + * + *********************************************************************** + */ + +#include +#include +#include + +typedef unsigned char BYTE; + +#define VOLUME_NUMBER 254 + +#define TRACKS 35 +#define SECTORS 16 +#define SECTOR_SIZE 256 +#define DOS_TRACK_BYTES (SECTORS * SECTOR_SIZE) + +#define RAW_TRACK_BYTES 0x1A00 + + +FILE *disk_file; +BYTE dos_track[SECTORS * SECTOR_SIZE]; + +BYTE raw_track[RAW_TRACK_BYTES]; +BYTE *target; /* Where to write in the raw_track buffer */ + +#define write_byte(x) (*target++ = (x)) + +BYTE GCR_encoding_table[64] = { + 0x96, 0x97, 0x9A, 0x9B, 0x9D, 0x9E, 0x9F, 0xA6, + 0xA7, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, 0xB2, 0xB3, + 0xB4, 0xB5, 0xB6, 0xB7, 0xB9, 0xBA, 0xBB, 0xBC, + 0xBD, 0xBE, 0xBF, 0xCB, 0xCD, 0xCE, 0xCF, 0xD3, + 0xD6, 0xD7, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, + 0xDF, 0xE5, 0xE6, 0xE7, 0xE9, 0xEA, 0xEB, 0xEC, + 0xED, 0xEE, 0xEF, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, + 0xF7, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF }; + +int Swap_Bit[4] = { 0, 2, 1, 3 }; /* swap lower 2 bits */ +BYTE GCR_buffer[256]; +BYTE GCR_buffer2[86]; + +/* physical sector no. to DOS 3.3 logical sector no. table */ +int Logical_Sector[16] = { + 0x0, 0x7, 0xE, 0x6, 0xD, 0x5, 0xC, 0x4, + 0xB, 0x3, 0xA, 0x2, 0x9, 0x1, 0x8, 0xF }; + +/* + * write an FM encoded value, used in writing address fields + */ +void FM_encode( BYTE data ) +{ + write_byte( (data >> 1) | 0xAA ); + write_byte( data | 0xAA ); +} + +/* + * Write 0xFF sync bytes + */ +void write_sync( int length ) +{ + while( length-- ) write_byte( 0xFF ); +} + +void write_address_field( int volume, int track, int sector ) +{ + /* + * write address mark + */ + write_byte( 0xD5 ); + write_byte( 0xAA ); + write_byte( 0x96 ); + + /* + * write Volume, Track, Sector & Check-sum + */ + FM_encode( volume ); + FM_encode( track ); + FM_encode( sector ); + FM_encode( volume ^ track ^ sector ); + + /* + * write epilogue + */ + write_byte( 0xDE ); + write_byte( 0xAA ); + write_byte( 0xEB ); +} + +/* + * 6-and-2 group encoding: the heart of the "nibblization" procedure + */ +void encode62( BYTE *page ) +{ + int i, j; + + /* 86 * 3 = 258, so the first two byte are encoded twice */ + GCR_buffer2[0] = Swap_Bit[page[1] & 0x03]; + GCR_buffer2[1] = Swap_Bit[page[0] & 0x03]; + + /* save higher 6 bits in GCR_buffer and lower 2 bits in GCR_buffer2 */ + for( i = 255, j = 2; i >= 0; i--, j = j == 85? 0: j + 1 ) { + GCR_buffer2[j] = (GCR_buffer2[j] << 2) | Swap_Bit[page[i] & 0x03]; + GCR_buffer[i] = page[i] >> 2; + } + + /* clear off higher 2 bits of GCR_buffer2 set in the last call */ + for( i = 0; i < 86; i++ ) + GCR_buffer2[i] &= 0x3f; +} + +void write_data_field(BYTE *page) +{ + int i; + BYTE last, checksum; + + encode62(page); + + /* write prologue */ + write_byte( 0xD5 ); + write_byte( 0xAA ); + write_byte( 0xAD ); + + /* write GCR encoded data */ + for ( i = 0x55, last = 0 ; i >= 0 ; --i ) { + checksum = last ^ GCR_buffer2[i]; + write_byte( GCR_encoding_table[checksum] ); + last = GCR_buffer2[i]; + } + for ( i = 0 ; i < 256 ; ++i ) { + checksum = last ^ GCR_buffer[i]; + write_byte( GCR_encoding_table[checksum] ); + last = GCR_buffer[i]; + } + + /* write checksum and epilogue */ + write_byte( GCR_encoding_table[last] ); + write_byte( 0xDE ); + write_byte( 0xAA ); + write_byte( 0xEB ); +} + +int main(int argc, char **argv) +{ + char nibname[256], *p; + FILE *nib_file; + int track; + + if (argc < 2) { + fprintf(stderr, "Usage: %s [NIB file]\n", argv[0]); + exit(1); + } + + if (!(disk_file = fopen(argv[1], "rb"))) { + fprintf(stderr, "Unable to mount disk file \"%s\"\n", argv[1]); + exit(1); + } + + if (argc > 2) { + strcpy(nibname, argv[2]); + } else { + /* Strip leading pathname from DSK name */ + for (p = argv[1]; *p; p++) { + if (*p == '/' || *p == '\\') + argv[1] = p + 1; + } + strcpy(nibname, argv[1]); + /* Strip trailing .dsk, if any, from DSK name */ + p = nibname + strlen(nibname); + if (p[-4] == '.' && + (p[-3] == 'd' || p[-3] == 'D') && + (p[-2] == 's' || p[-2] == 'S') && + (p[-1] == 'k' || p[-1] == 'K')) p[-4] = 0; + strcat(nibname, ".nib"); + } + + if (!(nib_file = fopen(nibname, "wb"))) { + fprintf(stderr, "Unable to write \"%s\"\n", nibname); + exit(1); + } + + /* Read, convert, and write each track */ + + for (track = 0 ; track < TRACKS ; ++track ) { + int sector; + + fseek( disk_file, track * DOS_TRACK_BYTES, 0L ); + if ( fread(dos_track, 1, DOS_TRACK_BYTES, disk_file) != DOS_TRACK_BYTES ) { + fprintf(stderr, "Unexpected end of disk data\n"); + exit(1); + } + + target = raw_track; + + for ( sector = 0 ; sector < SECTORS ; sector ++ ) { + write_sync( 38 ); /* Inter-sector gap */ + write_address_field( VOLUME_NUMBER, track, sector ); + write_sync( 8 ); + write_data_field( dos_track + Logical_Sector[sector] * SECTOR_SIZE ); + } + + /* Pad rest of buffer with sync bytes */ + + while (target != &raw_track[RAW_TRACK_BYTES]) + write_byte( 0xff ); + + if ( fwrite(raw_track, 1, RAW_TRACK_BYTES, nib_file) != RAW_TRACK_BYTES) { + fprintf(stderr, "Error writing .nib file\n"); + exit(1); + } + } + + fclose(disk_file); + fclose(nib_file); + + return 0; +} + +/* Local Variables: */ +/* compile-command: "cc -O -Wall -pedantic -ansi -o dsk2nib dsk2nib.c" */ +/* End: */ diff --git a/dsk2nib/dsk2nib.exe b/dsk2nib/dsk2nib.exe new file mode 100644 index 0000000..b175a14 Binary files /dev/null and b/dsk2nib/dsk2nib.exe differ diff --git a/jtag.cdf b/jtag.cdf new file mode 100644 index 0000000..0f00f29 --- /dev/null +++ b/jtag.cdf @@ -0,0 +1,15 @@ +/* Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Ign) + Device PartName(SOCVHPS) MfrSpec(OpMask(0)); + P ActionCode(Cfg) + Device PartName(5CSEBA6U23) Path("output_files/") File("Apple-II.sof") MfrSpec(OpMask(1)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/jtag_lite.cdf b/jtag_lite.cdf new file mode 100644 index 0000000..8e64228 --- /dev/null +++ b/jtag_lite.cdf @@ -0,0 +1,15 @@ +/* Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition */ +JedecChain; + FileRevision(JESD32A); + DefaultMfr(6E); + + P ActionCode(Ign) + Device PartName(SOCVHPS) MfrSpec(OpMask(0)); + P ActionCode(Cfg) + Device PartName(5CSEBA6U23) Path("output_files/") File("Apple-II-lite.sof") MfrSpec(OpMask(1)); + +ChainEnd; + +AlteraBegin; + ChainType(JTAG); +AlteraEnd; diff --git a/keyboard.vhd b/keyboard.vhd new file mode 100644 index 0000000..e19c6ba --- /dev/null +++ b/keyboard.vhd @@ -0,0 +1,261 @@ +------------------------------------------------------------------------------- +-- +-- PS/2 Keyboard interface for the Apple ][ +-- +-- Stephen A. Edwards, sedwards@cs.columbia.edu +-- After an original by Alex Freed +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity keyboard is + + port ( + PS2_Clk : in std_logic; -- From PS/2 port + PS2_Data : in std_logic; -- From PS/2 port + CLK_14M : in std_logic; + reads : in std_logic; -- Read strobe + reset : in std_logic; + K : out unsigned(7 downto 0) -- Latched, decoded keyboard data + ); +end keyboard; + +architecture rtl of keyboard is + + signal code, latched_code : unsigned(7 downto 0); + signal code_available : std_logic; + signal ascii : unsigned(7 downto 0); -- decoded + signal shifted_code : unsigned(11 downto 0); + + signal key_pressed : std_logic; -- Key pressed & not read + signal ctrl, shift : std_logic; + + -- Special PS/2 keyboard codes + constant KEY_UP_CODE : unsigned(7 downto 0) := X"F0"; + constant EXTENDED_CODE : unsigned(7 downto 0) := X"E0"; + constant LEFT_SHIFT : unsigned(7 downto 0) := X"12"; + constant RIGHT_SHIFT : unsigned(7 downto 0) := X"59"; + constant LEFT_CTRL : unsigned(7 downto 0) := X"14"; + + type states is (IDLE, + HAVE_CODE, + DECODE, + GOT_KEY_UP_CODE, + GOT_KEY_UP2, + GOT_KEY_UP3, + KEY_UP, + NORMAL_KEY + ); + + signal state, next_state : states; + +begin + + ps2_controller : entity work.PS2_Ctrl port map ( + Clk => CLK_14M, + Reset => reset, + PS2_Clk => PS2_Clk, + PS2_Data => PS2_Data, + DoRead => code_available, + Scan_DAV => code_available, + Scan_Code => code); + + K <= key_pressed & "00" & ascii(4 downto 0) when ctrl = '1' else + key_pressed & ascii(6 downto 0); + + shift_ctrl : process (CLK_14M, reset) + begin + if reset = '1' then + shift <= '0'; + ctrl <= '0'; + elsif rising_edge(CLK_14M) then + if state = HAVE_CODE then + if code = LEFT_SHIFT or code = RIGHT_SHIFT then + shift <= '1'; + elsif code = LEFT_CTRL then + ctrl <= '1'; + end if; + elsif state = KEY_UP then + if code = LEFT_SHIFT or code = RIGHT_SHIFT then + shift <= '0'; + elsif code = LEFT_CTRL then + ctrl <= '0'; + end if; + end if; + end if; + end process shift_ctrl; + + fsm : process (CLK_14M, reset) + begin + if reset = '1' then + state <= IDLE; + latched_code <= (others => '0'); + key_pressed <= '0'; + elsif rising_edge(CLK_14M) then + state <= next_state; + if reads = '1' then key_pressed <= '0'; end if; + if state = NORMAL_KEY then + latched_code <= code ; + key_pressed <= '1'; + end if; + end if; + end process fsm; + + fsm_next_state : process (code, code_available, state) + begin + next_state <= state; + case state is + when IDLE => + if code_available = '1' then next_state <= HAVE_CODE; end if; + + when HAVE_CODE => + next_state <= DECODE; + + when DECODE => + if code = KEY_UP_CODE then + next_state <= GOT_KEY_UP_CODE; + elsif code = EXTENDED_CODE then -- Treat extended codes as normal + next_state <= IDLE; + elsif code = LEFT_SHIFT or code = RIGHT_SHIFT or code = LEFT_CTRL then + next_state <= IDLE; + else + next_state <= NORMAL_KEY; + end if; + + when GOT_KEY_UP_CODE => + next_state <= GOT_KEY_UP2; + + when GOT_KEY_UP2 => + next_state <= GOT_KEY_UP3; + + when GOT_KEY_UP3 => + if code_available = '1' then + next_state <= KEY_UP; + end if; + + when KEY_UP | NORMAL_KEY => + next_state <= IDLE; + end case; + end process fsm_next_state; + + -- PS/2 scancode to ASCII translation + + shifted_code <= "000" & shift & latched_code; + + with shifted_code select + ascii <= + X"08" when X"066", -- Backspace ("backspace" key) + X"08" when X"166", -- Backspace ("backspace" key) + X"09" when X"00d", -- Horizontal Tab + X"09" when X"10d", -- Horizontal Tab + X"0d" when X"05a", -- Carriage return ("enter" key) + X"0d" when X"15a", -- Carriage return ("enter" key) + X"1b" when X"076", -- Escape ("esc" key) + X"1b" when X"176", -- Escape ("esc" key) + X"20" when X"029", -- Space + X"20" when X"129", -- Space + X"21" when X"116", -- ! + X"22" when X"152", -- " + X"23" when X"126", -- # + X"24" when X"125", -- $ + X"25" when X"12e", -- + X"26" when X"13d", -- + X"27" when X"052", -- + X"28" when X"146", -- + X"29" when X"145", -- + X"2a" when X"13e", -- * + X"2b" when X"155", -- + + X"2c" when X"041", -- , + X"2d" when X"04e", -- - + X"2e" when X"049", -- . + X"2f" when X"04a", -- / + X"30" when X"045", -- 0 + X"31" when X"016", -- 1 + X"32" when X"01e", -- 2 + X"33" when X"026", -- 3 + X"34" when X"025", -- 4 + X"35" when X"02e", -- 5 + X"36" when X"036", -- 6 + X"37" when X"03d", -- 7 + X"38" when X"03e", -- 8 + X"39" when X"046", -- 9 + X"3a" when X"14c", -- : + X"3b" when X"04c", -- ; + X"3c" when X"141", -- < + X"3d" when X"055", -- = + X"3e" when X"149", -- > + X"3f" when X"14a", -- ? + X"40" when X"11e", -- @ + X"41" when X"11c", -- A + X"42" when X"132", -- B + X"43" when X"121", -- C + X"44" when X"123", -- D + X"45" when X"124", -- E + X"46" when X"12b", -- F + X"47" when X"134", -- G + X"48" when X"133", -- H + X"49" when X"143", -- I + X"4a" when X"13b", -- J + X"4b" when X"142", -- K + X"4c" when X"14b", -- L + X"4d" when X"13a", -- M + X"4e" when X"131", -- N + X"4f" when X"144", -- O + X"50" when X"14d", -- P + X"51" when X"115", -- Q + X"52" when X"12d", -- R + X"53" when X"11b", -- S + X"54" when X"12c", -- T + X"55" when X"13c", -- U + X"56" when X"12a", -- V + X"57" when X"11d", -- W + X"58" when X"122", -- X + X"59" when X"135", -- Y + X"5a" when X"11a", -- Z + X"5b" when X"054", -- [ + X"5c" when X"05d", -- \ + X"5d" when X"05b", -- ] + X"5e" when X"136", -- ^ + X"5f" when X"14e", -- _ + X"60" when X"00e", -- ` + X"41" when X"01c", -- A + X"42" when X"032", -- B + X"43" when X"021", -- C + X"44" when X"023", -- D + X"45" when X"024", -- E + X"46" when X"02b", -- F + X"47" when X"034", -- G + X"48" when X"033", -- H + X"49" when X"043", -- I + X"4a" when X"03b", -- J + X"4b" when X"042", -- K + X"4c" when X"04b", -- L + X"4d" when X"03a", -- M + X"4e" when X"031", -- N + X"4f" when X"044", -- O + X"50" when X"04d", -- P + X"51" when X"015", -- Q + X"52" when X"02d", -- R + X"53" when X"01b", -- S + X"54" when X"02c", -- T + X"55" when X"03c", -- U + X"56" when X"02a", -- V + X"57" when X"01d", -- W + X"58" when X"022", -- X + X"59" when X"035", -- Y + X"5a" when X"01a", -- Z + X"7b" when X"154", -- { + X"7c" when X"15d", -- | + X"7d" when X"15b", -- } + X"7e" when X"10e", -- ~ + X"7f" when X"071", -- (Delete OR DEL on numeric keypad) + X"15" when X"074", -- right arrow (cntrl U) + X"08" when X"06b", -- left arrow (BS) + X"0B" when X"075", -- (up arrow) + X"0A" when X"072", -- (down arrow, ^J, LF) + X"7f" when X"171", -- (Delete OR DEL on numeric keypad) + X"00" when others; + +end rtl; diff --git a/main_roms.vhd b/main_roms.vhd new file mode 100644 index 0000000..c39852a --- /dev/null +++ b/main_roms.vhd @@ -0,0 +1,1562 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity main_roms is + port ( + addr : in unsigned(13 downto 0); + clk : in std_logic; + dout : out unsigned(7 downto 0)); +end main_roms; + +architecture rtl of main_roms is + type rom_array is array(0 to 12287) of unsigned(7 downto 0); + + constant ROM : rom_array := ( + X"6f", X"d8", X"65", X"d7", X"f8", X"dc", X"94", X"d9", + X"b1", X"db", X"30", X"f3", X"d8", X"df", X"e1", X"db", + X"8f", X"f3", X"98", X"f3", X"e4", X"f1", X"dd", X"f1", + X"d4", X"f1", X"24", X"f2", X"31", X"f2", X"40", X"f2", + X"d7", X"f3", X"e1", X"f3", X"e8", X"f6", X"fd", X"f6", + X"68", X"f7", X"6e", X"f7", X"e6", X"f7", X"57", X"fc", + X"20", X"f7", X"26", X"f7", X"74", X"f7", X"6c", X"f2", + X"6e", X"f2", X"72", X"f2", X"76", X"f2", X"7f", X"f2", + X"4e", X"f2", X"6a", X"d9", X"55", X"f2", X"85", X"f2", + X"a5", X"f2", X"ca", X"f2", X"17", X"f3", X"bb", X"f3", + X"9e", X"f3", X"61", X"f2", X"45", X"da", X"3d", X"d9", + X"11", X"d9", X"c8", X"d9", X"48", X"d8", X"f4", X"03", + X"20", X"d9", X"6a", X"d9", X"db", X"d9", X"6d", X"d8", + X"eb", X"d9", X"83", X"e7", X"c8", X"d8", X"af", X"d8", + X"12", X"e3", X"7a", X"e7", X"d4", X"da", X"95", X"d8", + X"a4", X"d6", X"69", X"d6", X"9f", X"db", X"48", X"d6", + X"90", X"eb", X"23", X"ec", X"af", X"eb", X"0a", X"00", + X"de", X"e2", X"12", X"d4", X"cd", X"df", X"ff", X"e2", + X"8d", X"ee", X"ae", X"ef", X"41", X"e9", X"09", X"ef", + X"ea", X"ef", X"f1", X"ef", X"3a", X"f0", X"9e", X"f0", + X"64", X"e7", X"d6", X"e6", X"c5", X"e3", X"07", X"e7", + X"e5", X"e6", X"46", X"e6", X"5a", X"e6", X"86", X"e6", + X"91", X"e6", X"79", X"c0", X"e7", X"79", X"a9", X"e7", + X"7b", X"81", X"e9", X"7b", X"68", X"ea", X"7d", X"96", + X"ee", X"50", X"54", X"df", X"46", X"4e", X"df", X"7f", + X"cf", X"ee", X"7f", X"97", X"de", X"64", X"64", X"df", + X"45", X"4e", X"c4", X"46", X"4f", X"d2", X"4e", X"45", + X"58", X"d4", X"44", X"41", X"54", X"c1", X"49", X"4e", + X"50", X"55", X"d4", X"44", X"45", X"cc", X"44", X"49", + X"cd", X"52", X"45", X"41", X"c4", X"47", X"d2", X"54", + X"45", X"58", X"d4", X"50", X"52", X"a3", X"49", X"4e", + X"a3", X"43", X"41", X"4c", X"cc", X"50", X"4c", X"4f", + X"d4", X"48", X"4c", X"49", X"ce", X"56", X"4c", X"49", + X"ce", X"48", X"47", X"52", X"b2", X"48", X"47", X"d2", + X"48", X"43", X"4f", X"4c", X"4f", X"52", X"bd", X"48", + X"50", X"4c", X"4f", X"d4", X"44", X"52", X"41", X"d7", + X"58", X"44", X"52", X"41", X"d7", X"48", X"54", X"41", + X"c2", X"48", X"4f", X"4d", X"c5", X"52", X"4f", X"54", + X"bd", X"53", X"43", X"41", X"4c", X"45", X"bd", X"53", + X"48", X"4c", X"4f", X"41", X"c4", X"54", X"52", X"41", + X"43", X"c5", X"4e", X"4f", X"54", X"52", X"41", X"43", + X"c5", X"4e", X"4f", X"52", X"4d", X"41", X"cc", X"49", + X"4e", X"56", X"45", X"52", X"53", X"c5", X"46", X"4c", + X"41", X"53", X"c8", X"43", X"4f", X"4c", X"4f", X"52", + X"bd", X"50", X"4f", X"d0", X"56", X"54", X"41", X"c2", + X"48", X"49", X"4d", X"45", X"4d", X"ba", X"4c", X"4f", + X"4d", X"45", X"4d", X"ba", X"4f", X"4e", X"45", X"52", + X"d2", X"52", X"45", X"53", X"55", X"4d", X"c5", X"52", + X"45", X"43", X"41", X"4c", X"cc", X"53", X"54", X"4f", + X"52", X"c5", X"53", X"50", X"45", X"45", X"44", X"bd", + X"4c", X"45", X"d4", X"47", X"4f", X"54", X"cf", X"52", + X"55", X"ce", X"49", X"c6", X"52", X"45", X"53", X"54", + X"4f", X"52", X"c5", X"a6", X"47", X"4f", X"53", X"55", + X"c2", X"52", X"45", X"54", X"55", X"52", X"ce", X"52", + X"45", X"cd", X"53", X"54", X"4f", X"d0", X"4f", X"ce", + X"57", X"41", X"49", X"d4", X"4c", X"4f", X"41", X"c4", + X"53", X"41", X"56", X"c5", X"44", X"45", X"c6", X"50", + X"4f", X"4b", X"c5", X"50", X"52", X"49", X"4e", X"d4", + X"43", X"4f", X"4e", X"d4", X"4c", X"49", X"53", X"d4", + X"43", X"4c", X"45", X"41", X"d2", X"47", X"45", X"d4", + X"4e", X"45", X"d7", X"54", X"41", X"42", X"a8", X"54", + X"cf", X"46", X"ce", X"53", X"50", X"43", X"a8", X"54", + X"48", X"45", X"ce", X"41", X"d4", X"4e", X"4f", X"d4", + X"53", X"54", X"45", X"d0", X"ab", X"ad", X"aa", X"af", + X"de", X"41", X"4e", X"c4", X"4f", X"d2", X"be", X"bd", + X"bc", X"53", X"47", X"ce", X"49", X"4e", X"d4", X"41", + X"42", X"d3", X"55", X"53", X"d2", X"46", X"52", X"c5", + X"53", X"43", X"52", X"4e", X"a8", X"50", X"44", X"cc", + X"50", X"4f", X"d3", X"53", X"51", X"d2", X"52", X"4e", + X"c4", X"4c", X"4f", X"c7", X"45", X"58", X"d0", X"43", + X"4f", X"d3", X"53", X"49", X"ce", X"54", X"41", X"ce", + X"41", X"54", X"ce", X"50", X"45", X"45", X"cb", X"4c", + X"45", X"ce", X"53", X"54", X"52", X"a4", X"56", X"41", + X"cc", X"41", X"53", X"c3", X"43", X"48", X"52", X"a4", + X"4c", X"45", X"46", X"54", X"a4", X"52", X"49", X"47", + X"48", X"54", X"a4", X"4d", X"49", X"44", X"a4", X"00", + X"4e", X"45", X"58", X"54", X"20", X"57", X"49", X"54", + X"48", X"4f", X"55", X"54", X"20", X"46", X"4f", X"d2", + X"53", X"59", X"4e", X"54", X"41", X"d8", X"52", X"45", + X"54", X"55", X"52", X"4e", X"20", X"57", X"49", X"54", + X"48", X"4f", X"55", X"54", X"20", X"47", X"4f", X"53", + X"55", X"c2", X"4f", X"55", X"54", X"20", X"4f", X"46", + X"20", X"44", X"41", X"54", X"c1", X"49", X"4c", X"4c", + X"45", X"47", X"41", X"4c", X"20", X"51", X"55", X"41", + X"4e", X"54", X"49", X"54", X"d9", X"4f", X"56", X"45", + X"52", X"46", X"4c", X"4f", X"d7", X"4f", X"55", X"54", + X"20", X"4f", X"46", X"20", X"4d", X"45", X"4d", X"4f", + X"52", X"d9", X"55", X"4e", X"44", X"45", X"46", X"27", + X"44", X"20", X"53", X"54", X"41", X"54", X"45", X"4d", + X"45", X"4e", X"d4", X"42", X"41", X"44", X"20", X"53", + X"55", X"42", X"53", X"43", X"52", X"49", X"50", X"d4", + X"52", X"45", X"44", X"49", X"4d", X"27", X"44", X"20", + X"41", X"52", X"52", X"41", X"d9", X"44", X"49", X"56", + X"49", X"53", X"49", X"4f", X"4e", X"20", X"42", X"59", + X"20", X"5a", X"45", X"52", X"cf", X"49", X"4c", X"4c", + X"45", X"47", X"41", X"4c", X"20", X"44", X"49", X"52", + X"45", X"43", X"d4", X"54", X"59", X"50", X"45", X"20", + X"4d", X"49", X"53", X"4d", X"41", X"54", X"43", X"c8", + X"53", X"54", X"52", X"49", X"4e", X"47", X"20", X"54", + X"4f", X"4f", X"20", X"4c", X"4f", X"4e", X"c7", X"46", + X"4f", X"52", X"4d", X"55", X"4c", X"41", X"20", X"54", + X"4f", X"4f", X"20", X"43", X"4f", X"4d", X"50", X"4c", + X"45", X"d8", X"43", X"41", X"4e", X"27", X"54", X"20", + X"43", X"4f", X"4e", X"54", X"49", X"4e", X"55", X"c5", + X"55", X"4e", X"44", X"45", X"46", X"27", X"44", X"20", + X"46", X"55", X"4e", X"43", X"54", X"49", X"4f", X"ce", + X"20", X"45", X"52", X"52", X"4f", X"52", X"07", X"00", + X"20", X"49", X"4e", X"20", X"00", X"0d", X"42", X"52", + X"45", X"41", X"4b", X"07", X"00", X"ba", X"e8", X"e8", + X"e8", X"e8", X"bd", X"01", X"01", X"c9", X"81", X"d0", + X"21", X"a5", X"86", X"d0", X"0a", X"bd", X"02", X"01", + X"85", X"85", X"bd", X"03", X"01", X"85", X"86", X"dd", + X"03", X"01", X"d0", X"07", X"a5", X"85", X"dd", X"02", + X"01", X"f0", X"07", X"8a", X"18", X"69", X"12", X"aa", + X"d0", X"d8", X"60", X"20", X"e3", X"d3", X"85", X"6d", + X"84", X"6e", X"38", X"a5", X"96", X"e5", X"9b", X"85", + X"5e", X"a8", X"a5", X"97", X"e5", X"9c", X"aa", X"e8", + X"98", X"f0", X"23", X"a5", X"96", X"38", X"e5", X"5e", + X"85", X"96", X"b0", X"03", X"c6", X"97", X"38", X"a5", + X"94", X"e5", X"5e", X"85", X"94", X"b0", X"08", X"c6", + X"95", X"90", X"04", X"b1", X"96", X"91", X"94", X"88", + X"d0", X"f9", X"b1", X"96", X"91", X"94", X"c6", X"97", + X"c6", X"95", X"ca", X"d0", X"f2", X"60", X"0a", X"69", + X"36", X"b0", X"35", X"85", X"5e", X"ba", X"e4", X"5e", + X"90", X"2e", X"60", X"c4", X"70", X"90", X"28", X"d0", + X"04", X"c5", X"6f", X"90", X"22", X"48", X"a2", X"09", + X"98", X"48", X"b5", X"93", X"ca", X"10", X"fa", X"20", + X"84", X"e4", X"a2", X"f7", X"68", X"95", X"9d", X"e8", + X"30", X"fa", X"68", X"a8", X"68", X"c4", X"70", X"90", + X"06", X"d0", X"05", X"c5", X"6f", X"b0", X"01", X"60", + X"a2", X"4d", X"24", X"d8", X"10", X"03", X"4c", X"e9", + X"f2", X"20", X"fb", X"da", X"20", X"5a", X"db", X"bd", + X"60", X"d2", X"48", X"20", X"5c", X"db", X"e8", X"68", + X"10", X"f5", X"20", X"83", X"d6", X"a9", X"50", X"a0", + X"d3", X"20", X"3a", X"db", X"a4", X"76", X"c8", X"f0", + X"03", X"20", X"19", X"ed", X"20", X"fb", X"da", X"a2", + X"dd", X"20", X"2e", X"d5", X"86", X"b8", X"84", X"b9", + X"46", X"d8", X"20", X"b1", X"00", X"aa", X"f0", X"ec", + X"a2", X"ff", X"86", X"76", X"90", X"06", X"20", X"59", + X"d5", X"4c", X"05", X"d8", X"a6", X"af", X"86", X"69", + X"a6", X"b0", X"86", X"6a", X"20", X"0c", X"da", X"20", + X"59", X"d5", X"84", X"0f", X"20", X"1a", X"d6", X"90", + X"44", X"a0", X"01", X"b1", X"9b", X"85", X"5f", X"a5", + X"69", X"85", X"5e", X"a5", X"9c", X"85", X"61", X"a5", + X"9b", X"88", X"f1", X"9b", X"18", X"65", X"69", X"85", + X"69", X"85", X"60", X"a5", X"6a", X"69", X"ff", X"85", + X"6a", X"e5", X"9c", X"aa", X"38", X"a5", X"9b", X"e5", + X"69", X"a8", X"b0", X"03", X"e8", X"c6", X"61", X"18", + X"65", X"5e", X"90", X"03", X"c6", X"5f", X"18", X"b1", + X"5e", X"91", X"60", X"c8", X"d0", X"f9", X"e6", X"5f", + X"e6", X"61", X"ca", X"d0", X"f2", X"ad", X"00", X"02", + X"f0", X"38", X"a5", X"73", X"a4", X"74", X"85", X"6f", + X"84", X"70", X"a5", X"69", X"85", X"96", X"65", X"0f", + X"85", X"94", X"a4", X"6a", X"84", X"97", X"90", X"01", + X"c8", X"84", X"95", X"20", X"93", X"d3", X"a5", X"50", + X"a4", X"51", X"8d", X"fe", X"01", X"8c", X"ff", X"01", + X"a5", X"6d", X"a4", X"6e", X"85", X"69", X"84", X"6a", + X"a4", X"0f", X"b9", X"fb", X"01", X"88", X"91", X"9b", + X"d0", X"f8", X"20", X"65", X"d6", X"a5", X"67", X"a4", + X"68", X"85", X"5e", X"84", X"5f", X"18", X"a0", X"01", + X"b1", X"5e", X"d0", X"0b", X"a5", X"69", X"85", X"af", + X"a5", X"6a", X"85", X"b0", X"4c", X"3c", X"d4", X"a0", + X"04", X"c8", X"b1", X"5e", X"d0", X"fb", X"c8", X"98", + X"65", X"5e", X"aa", X"a0", X"00", X"91", X"5e", X"a5", + X"5f", X"69", X"00", X"c8", X"91", X"5e", X"86", X"5e", + X"85", X"5f", X"90", X"d2", X"a2", X"80", X"86", X"33", + X"20", X"6a", X"fd", X"e0", X"ef", X"90", X"02", X"a2", + X"ef", X"a9", X"00", X"9d", X"00", X"02", X"8a", X"f0", + X"0b", X"bd", X"ff", X"01", X"29", X"7f", X"9d", X"ff", + X"01", X"ca", X"d0", X"f5", X"a9", X"00", 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X"d0", X"c9", + X"c6", X"24", X"10", X"e8", X"a5", X"21", X"85", X"24", + X"c6", X"24", X"a5", X"22", X"c5", X"25", X"b0", X"0b", + X"c6", X"25", X"a5", X"25", X"20", X"c1", X"fb", X"65", + X"20", X"85", X"28", X"60", X"49", X"c0", X"f0", X"28", + X"69", X"fd", X"90", X"c0", X"f0", X"da", X"69", X"fd", + X"90", X"2c", X"f0", X"de", X"69", X"fd", X"90", X"5c", + X"d0", X"e9", X"a4", X"24", X"a5", X"25", X"48", X"20", + X"24", X"fc", X"20", X"9e", X"fc", X"a0", X"00", X"68", + X"69", X"00", X"c5", X"23", X"90", X"f0", X"b0", X"ca", + X"a5", X"22", X"85", X"25", X"a0", X"00", X"84", X"24", + X"f0", X"e4", X"a9", X"00", X"85", X"24", X"e6", X"25", + X"a5", X"25", X"c5", X"23", X"90", X"b6", X"c6", X"25", + X"a5", X"22", X"48", X"20", X"24", X"fc", X"a5", X"28", + X"85", X"2a", X"a5", X"29", X"85", X"2b", X"a4", X"21", + X"88", X"68", X"69", X"01", X"c5", X"23", X"b0", X"0d", + X"48", X"20", X"24", X"fc", X"b1", X"28", X"91", X"2a", + X"88", X"10", X"f9", X"30", X"e1", X"a0", X"00", X"20", + X"9e", X"fc", X"b0", X"86", X"a4", X"24", X"a9", X"a0", + X"91", X"28", X"c8", X"c4", X"21", X"90", X"f9", X"60", + X"38", X"48", X"e9", X"01", X"d0", X"fc", X"68", X"e9", + X"01", X"d0", X"f6", X"60", X"e6", X"42", X"d0", X"02", + X"e6", X"43", X"a5", X"3c", X"c5", X"3e", X"a5", X"3d", + X"e5", X"3f", X"e6", X"3c", X"d0", X"02", X"e6", X"3d", + X"60", X"a0", X"4b", X"20", X"db", X"fc", X"d0", X"f9", + X"69", X"fe", X"b0", X"f5", X"a0", X"21", X"20", X"db", + X"fc", X"c8", X"c8", X"88", X"d0", X"fd", X"90", X"05", + X"a0", X"32", X"88", X"d0", X"fd", X"ac", X"20", X"c0", + X"a0", X"2c", X"ca", X"60", X"a2", X"08", X"48", X"20", + X"fa", X"fc", X"68", X"2a", X"a0", X"3a", X"ca", X"d0", + X"f5", X"60", X"20", X"fd", X"fc", X"88", X"ad", X"60", + X"c0", X"45", X"2f", X"10", X"f8", X"45", X"2f", X"85", + X"2f", X"c0", X"80", X"60", X"a4", X"24", X"b1", X"28", + X"48", X"29", X"3f", X"09", X"40", X"91", X"28", X"68", + X"6c", X"38", X"00", X"e6", X"4e", X"d0", X"02", X"e6", + X"4f", X"2c", X"00", X"c0", X"10", X"f5", X"91", X"28", + X"ad", X"00", X"c0", X"2c", X"10", X"c0", X"60", X"20", + X"0c", X"fd", X"20", X"a5", X"fb", X"20", X"0c", X"fd", + X"c9", X"9b", X"f0", X"f3", X"60", X"a5", X"32", X"48", + X"a9", X"ff", X"85", X"32", X"bd", X"00", X"02", X"20", + X"ed", X"fd", X"68", X"85", X"32", X"bd", X"00", X"02", + X"c9", X"88", X"f0", X"1d", X"c9", X"98", X"f0", X"0a", + X"e0", X"f8", X"90", X"03", X"20", X"3a", X"ff", X"e8", + X"d0", X"13", X"a9", X"dc", X"20", X"ed", X"fd", X"20", + X"8e", X"fd", X"a5", X"33", X"20", X"ed", X"fd", X"a2", + X"01", X"8a", X"f0", X"f3", X"ca", X"20", X"35", X"fd", + X"c9", X"95", X"d0", X"02", X"b1", X"28", X"c9", X"e0", + X"90", X"02", X"29", X"df", X"9d", X"00", X"02", X"c9", + X"8d", X"d0", X"b2", X"20", X"9c", X"fc", X"a9", X"8d", + X"d0", X"5b", X"a4", X"3d", X"a6", X"3c", X"20", X"8e", + X"fd", X"20", X"40", X"f9", X"a0", X"00", X"a9", X"ad", + X"4c", X"ed", X"fd", X"a5", X"3c", X"09", X"07", X"85", + X"3e", X"a5", X"3d", X"85", X"3f", X"a5", X"3c", X"29", + X"07", X"d0", X"03", X"20", X"92", X"fd", X"a9", X"a0", + X"20", X"ed", X"fd", X"b1", X"3c", X"20", X"da", X"fd", + X"20", X"ba", X"fc", X"90", X"e8", X"60", X"4a", X"90", + X"ea", X"4a", X"4a", X"a5", X"3e", X"90", X"02", X"49", + X"ff", X"65", X"3c", X"48", X"a9", X"bd", X"20", X"ed", + X"fd", X"68", X"48", X"4a", X"4a", X"4a", X"4a", X"20", + X"e5", X"fd", X"68", X"29", X"0f", X"09", X"b0", X"c9", + X"ba", X"90", X"02", X"69", X"06", X"6c", X"36", X"00", + X"c9", X"a0", X"90", X"02", X"25", X"32", X"84", X"35", + X"48", X"20", X"78", X"fb", X"68", X"a4", X"35", X"60", + X"c6", X"34", X"f0", X"9f", X"ca", X"d0", X"16", X"c9", + X"ba", X"d0", X"bb", X"85", X"31", X"a5", X"3e", X"91", + X"40", X"e6", X"40", X"d0", X"02", X"e6", X"41", X"60", + X"a4", X"34", X"b9", X"ff", X"01", X"85", X"31", X"60", + X"a2", X"01", X"b5", X"3e", X"95", X"42", X"95", X"44", + X"ca", X"10", X"f7", X"60", X"b1", X"3c", X"91", X"42", + X"20", X"b4", X"fc", X"90", X"f7", X"60", X"b1", X"3c", + X"d1", X"42", X"f0", X"1c", X"20", X"92", X"fd", X"b1", + X"3c", X"20", X"da", X"fd", X"a9", X"a0", X"20", X"ed", + X"fd", X"a9", X"a8", X"20", X"ed", X"fd", X"b1", X"42", + X"20", X"da", X"fd", X"a9", X"a9", X"20", X"ed", X"fd", + X"20", X"b4", X"fc", X"90", X"d9", X"60", X"20", X"75", + X"fe", X"a9", X"14", X"48", X"20", X"d0", X"f8", X"20", + X"53", X"f9", X"85", X"3a", X"84", X"3b", X"68", X"38", + X"e9", X"01", X"d0", X"ef", X"60", X"8a", X"f0", X"07", + X"b5", X"3c", X"95", X"3a", X"ca", X"10", X"f9", X"60", + X"a0", X"3f", X"d0", X"02", X"a0", X"ff", X"84", X"32", + X"60", X"a9", X"00", X"85", X"3e", X"a2", X"38", X"a0", + X"1b", X"d0", X"08", X"a9", X"00", X"85", X"3e", X"a2", + X"36", X"a0", X"f0", X"a5", X"3e", X"29", X"0f", X"f0", + X"06", X"09", X"c0", X"a0", X"00", X"f0", X"02", X"a9", + X"fd", X"94", X"00", X"95", X"01", X"60", X"ea", X"ea", + X"4c", X"00", X"e0", X"4c", X"03", X"e0", X"20", X"75", + X"fe", X"20", X"3f", X"ff", X"6c", X"3a", X"00", X"4c", + X"d7", X"fa", X"60", X"ea", X"60", X"ea", X"ea", X"ea", + X"ea", X"ea", X"4c", X"f8", X"03", X"a9", X"40", X"20", + X"c9", X"fc", X"a0", X"27", X"a2", X"00", X"41", X"3c", + X"48", X"a1", X"3c", X"20", X"ed", X"fe", X"20", X"ba", + X"fc", X"a0", X"1d", X"68", X"90", X"ee", X"a0", X"22", + X"20", X"ed", X"fe", X"f0", X"4d", X"a2", X"10", X"0a", + X"20", X"d6", X"fc", X"d0", X"fa", X"60", X"20", X"00", + X"fe", X"68", X"68", X"d0", X"6c", X"20", X"fa", X"fc", + X"a9", X"16", X"20", X"c9", X"fc", X"85", X"2e", X"20", + X"fa", X"fc", X"a0", X"24", X"20", X"fd", X"fc", X"b0", + X"f9", X"20", X"fd", X"fc", X"a0", X"3b", X"20", X"ec", + X"fc", X"81", X"3c", X"45", X"2e", X"85", X"2e", X"20", + X"ba", X"fc", X"a0", X"35", X"90", X"f0", X"20", X"ec", + X"fc", X"c5", X"2e", X"f0", X"0d", X"a9", X"c5", X"20", + X"ed", X"fd", X"a9", X"d2", X"20", X"ed", X"fd", X"20", + X"ed", X"fd", X"a9", X"87", X"4c", X"ed", X"fd", X"a5", + X"48", X"48", X"a5", X"45", X"a6", X"46", X"a4", X"47", + X"28", X"60", X"85", X"45", X"86", X"46", X"84", X"47", + X"08", X"68", X"85", X"48", X"ba", X"86", X"49", X"d8", + X"60", X"20", X"84", X"fe", X"20", X"2f", X"fb", X"20", + X"93", X"fe", X"20", X"89", X"fe", X"d8", X"20", X"3a", + X"ff", X"a9", X"aa", X"85", X"33", X"20", X"67", X"fd", + X"20", X"c7", X"ff", X"20", X"a7", X"ff", X"84", X"34", + X"a0", X"17", X"88", X"30", X"e8", X"d9", X"cc", X"ff", + X"d0", X"f8", X"20", X"be", X"ff", X"a4", X"34", X"4c", + X"73", X"ff", X"a2", X"03", X"0a", X"0a", X"0a", X"0a", + X"0a", X"26", X"3e", X"26", X"3f", X"ca", X"10", X"f8", + X"a5", X"31", X"d0", X"06", X"b5", X"3f", X"95", X"3d", + X"95", X"41", X"e8", X"f0", X"f3", X"d0", X"06", X"a2", + X"00", X"86", X"3e", X"86", X"3f", X"b9", X"00", X"02", + X"c8", X"49", X"b0", X"c9", X"0a", X"90", X"d3", X"69", + X"88", X"c9", X"fa", X"b0", X"cd", X"60", X"a9", X"fe", + X"48", X"b9", X"e3", X"ff", X"48", X"a5", X"31", X"a0", + X"00", X"84", X"31", X"60", X"bc", X"b2", X"be", X"b2", + X"ef", X"c4", X"b2", X"a9", X"bb", X"a6", X"a4", X"06", + X"95", X"07", X"02", X"05", X"f0", X"00", X"eb", X"93", + X"a7", X"c6", X"99", X"b2", X"c9", X"be", X"c1", X"35", + X"8c", X"c4", X"96", X"af", X"17", X"17", X"2b", X"1f", + X"83", X"7f", X"5d", X"cc", X"b5", X"fc", X"17", X"17", + X"f5", X"03", X"fb", X"03", X"62", X"fa", X"59", X"ff"); + +begin + +process (clk) + begin + if rising_edge(clk) then + dout <= ROM(TO_INTEGER(addr)); + end if; + end process; + +end rtl; diff --git a/mockingboard/YM2149_volmix.vhd b/mockingboard/YM2149_volmix.vhd new file mode 100644 index 0000000..7afcfb1 --- /dev/null +++ b/mockingboard/YM2149_volmix.vhd @@ -0,0 +1,583 @@ +-- +-- A simulation model of YM2149 (AY-3-8910 with bells on) + +-- Copyright (c) MikeJ - Jan 2005 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email support@fpgaarcade.com +-- +-- Revision list +-- +-- version 001 initial release +-- +-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA +-- +-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V) +-- vol 15 .. 0 +-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132 +-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order +-- to produced all the required values. +-- (The first part of the curve is a bit steeper and the last bit is more linear than expected) +-- +-- NOTE, this component uses a volume table for accurate mixing of the three analogue channels, +-- where the outputs are wired together - like in the Atari ST + +library ieee; + use ieee.std_logic_1164.all; + use ieee.std_logic_arith.all; + use ieee.std_logic_unsigned.all; + +entity YM2149 is + port ( + -- data bus + I_DA : in std_logic_vector(7 downto 0); + O_DA : out std_logic_vector(7 downto 0); + O_DA_OE_L : out std_logic; + -- control + I_A9_L : in std_logic; + I_A8 : in std_logic; + I_BDIR : in std_logic; + I_BC2 : in std_logic; + I_BC1 : in std_logic; + I_SEL_L : in std_logic; + + O_AUDIO : out std_logic_vector(7 downto 0); + -- port a + I_IOA : in std_logic_vector(7 downto 0); + O_IOA : out std_logic_vector(7 downto 0); + O_IOA_OE_L : out std_logic; + -- port b + I_IOB : in std_logic_vector(7 downto 0); + O_IOB : out std_logic_vector(7 downto 0); + O_IOB_OE_L : out std_logic; + -- + ENA : in std_logic; -- clock enable for higher speed operation + RESET_L : in std_logic; + CLK : in std_logic -- note 6 Mhz + ); +end; + +architecture RTL of YM2149 is + + component vol_table + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(11 downto 0); + DATA : out std_logic_vector(9 downto 0) + ); + end component; + + -- signals + type array_16x8 is array (0 to 15) of std_logic_vector(7 downto 0); + type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0); + + signal cnt_div : std_logic_vector(3 downto 0) := (others => '0'); + signal noise_div : std_logic := '0'; + signal ena_div : std_logic; + signal ena_div_noise : std_logic; + signal poly17 : std_logic_vector(16 downto 0) := (others => '0'); + + -- registers + signal addr : std_logic_vector(7 downto 0); + signal busctrl_addr : std_logic; + signal busctrl_we : std_logic; + signal busctrl_re : std_logic; + + signal reg : array_16x8; + signal env_reset : std_logic; + signal ioa_inreg : std_logic_vector(7 downto 0); + signal iob_inreg : std_logic_vector(7 downto 0); + + signal noise_gen_cnt : std_logic_vector(4 downto 0); + signal noise_gen_op : std_logic; + signal tone_gen_cnt : array_3x12 := (others => (others => '0')); + signal tone_gen_op : std_logic_vector(3 downto 1) := "000"; + + signal env_gen_cnt : std_logic_vector(15 downto 0); + signal env_ena : std_logic; + signal env_hold : std_logic; + signal env_inc : std_logic; + signal env_vol : std_logic_vector(4 downto 0); + + signal vol_table_in : std_logic_vector(11 downto 0); + signal vol_table_out : std_logic_vector(9 downto 0); + +begin + -- cpu i/f + p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8) + variable cs : std_logic; + variable sel : std_logic_vector(2 downto 0); + begin + -- BDIR BC2 BC1 MODE + -- 0 0 0 inactive + -- 0 0 1 address + -- 0 1 0 inactive + -- 0 1 1 read + -- 1 0 0 address + -- 1 0 1 inactive + -- 1 1 0 write + -- 1 1 1 read + busctrl_addr <= '0'; + busctrl_we <= '0'; + busctrl_re <= '0'; + + cs := '0'; + if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then + cs := '1'; + end if; + + sel := (I_BDIR & I_BC2 & I_BC1); + case sel is + when "000" => null; + when "001" => busctrl_addr <= '1'; + when "010" => null; + when "011" => busctrl_re <= cs; + when "100" => busctrl_addr <= '1'; + when "101" => null; + when "110" => busctrl_we <= cs; + when "111" => busctrl_addr <= '1'; + when others => null; + end case; + end process; + + p_oe : process(busctrl_re) + begin + -- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns + O_DA_OE_L <= not (busctrl_re); + end process; + + -- CLOCKED + --p_waddr : process + --begin + ---- looks like registers are latches in real chip, but the address is caught at the end of the address state. + --wait until rising_edge(CLK); + + --if (RESET_L = '0') then + --addr <= (others => '0'); + --else + --if (busctrl_addr = '1') then + --addr <= I_DA; + --end if; + --end if; + --end process; + --p_wdata : process + --begin + ---- looks like registers are latches in real chip, but the address is caught at the end of the address state. + --wait until rising_edge(CLK); + --env_reset <= '0'; + + --if (RESET_L = '0') then + --reg <= (others => (others => '0')); + --env_reset <= '1'; + --else + --env_reset <= '0'; + --if (busctrl_we = '1') then + --case addr(3 downto 0) is + --when x"0" => reg(0) <= I_DA; + --when x"1" => reg(1) <= I_DA; + --when x"2" => reg(2) <= I_DA; + --when x"3" => reg(3) <= I_DA; + --when x"4" => reg(4) <= I_DA; + --when x"5" => reg(5) <= I_DA; + --when x"6" => reg(6) <= I_DA; + --when x"7" => reg(7) <= I_DA; + --when x"8" => reg(8) <= I_DA; + --when x"9" => reg(9) <= I_DA; + --when x"A" => reg(10) <= I_DA; + --when x"B" => reg(11) <= I_DA; + --when x"C" => reg(12) <= I_DA; + --when x"D" => reg(13) <= I_DA; env_reset <= '1'; + --when x"E" => reg(14) <= I_DA; + --when x"F" => reg(15) <= I_DA; + --when others => null; + --end case; + --end if; + --end if; + --end process; + + -- LATCHED, useful when emulating a real chip in circuit. Nasty as gated clock. + p_waddr : process(reset_l, busctrl_addr) + begin + -- looks like registers are latches in real chip, but the address is caught at the end of the address state. + if (RESET_L = '0') then + addr <= (others => '0'); + elsif falling_edge(busctrl_addr) then -- yuk + addr <= I_DA; + end if; + end process; + + p_wdata : process(reset_l, busctrl_we, addr) + begin + if (RESET_L = '0') then + reg <= (others => (others => '0')); + elsif falling_edge(busctrl_we) then + case addr(3 downto 0) is + when x"0" => reg(0) <= I_DA; + when x"1" => reg(1) <= I_DA; + when x"2" => reg(2) <= I_DA; + when x"3" => reg(3) <= I_DA; + when x"4" => reg(4) <= I_DA; + when x"5" => reg(5) <= I_DA; + when x"6" => reg(6) <= I_DA; + when x"7" => reg(7) <= I_DA; + when x"8" => reg(8) <= I_DA; + when x"9" => reg(9) <= I_DA; + when x"A" => reg(10) <= I_DA; + when x"B" => reg(11) <= I_DA; + when x"C" => reg(12) <= I_DA; + when x"D" => reg(13) <= I_DA; + when x"E" => reg(14) <= I_DA; + when x"F" => reg(15) <= I_DA; + when others => null; + end case; + end if; + + env_reset <= '0'; + if (busctrl_we = '1') and (addr(3 downto 0) = x"D") then + env_reset <= '1'; + end if; + end process; + + p_rdata : process(busctrl_re, addr, reg) + begin + O_DA <= (others => '0'); -- 'X' + if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator + case addr(3 downto 0) is + when x"0" => O_DA <= reg(0) ; + when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ; + when x"2" => O_DA <= reg(2) ; + when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ; + when x"4" => O_DA <= reg(4) ; + when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ; + when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ; + when x"7" => O_DA <= reg(7) ; + when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ; + when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ; + when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ; + when x"B" => O_DA <= reg(11); + when x"C" => O_DA <= reg(12); + when x"D" => O_DA <= "0000" & reg(13)(3 downto 0); + when x"E" => if (reg(7)(6) = '0') then -- input + O_DA <= ioa_inreg; + else + O_DA <= reg(14); -- read output reg + end if; + when x"F" => if (Reg(7)(7) = '0') then + O_DA <= iob_inreg; + else + O_DA <= reg(15); + end if; + when others => null; + end case; + end if; + end process; + -- + p_divider : process + begin + wait until rising_edge(CLK); + -- / 8 when SEL is high and /16 when SEL is low + if (ENA = '1') then + ena_div <= '0'; + ena_div_noise <= '0'; + if (cnt_div = "0000") then + cnt_div <= (not I_SEL_L) & "111"; + ena_div <= '1'; + + noise_div <= not noise_div; + if (noise_div = '1') then + ena_div_noise <= '1'; + end if; + else + cnt_div <= cnt_div - "1"; + end if; + end if; + end process; + + p_noise_gen : process + variable noise_gen_comp : std_logic_vector(4 downto 0); + variable poly17_zero : std_logic; + begin + wait until rising_edge(CLK); + + if (reg(6)(4 downto 0) = "00000") then + noise_gen_comp := "00000"; + else + noise_gen_comp := (reg(6)(4 downto 0) - "1"); + end if; + + poly17_zero := '0'; + if (poly17 = "00000000000000000") then poly17_zero := '1'; end if; + + if (ENA = '1') then + + if (ena_div_noise = '1') then -- divider ena + + if (noise_gen_cnt >= noise_gen_comp) then + noise_gen_cnt <= "00000"; + poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1); + else + noise_gen_cnt <= (noise_gen_cnt + "1"); + end if; + end if; + end if; + end process; + noise_gen_op <= poly17(0); + + p_tone_gens : process + variable tone_gen_freq : array_3x12; + variable tone_gen_comp : array_3x12; + begin + wait until rising_edge(CLK); + + -- looks like real chips count up - we need to get the Exact behaviour .. + tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0); + tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2); + tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4); + -- period 0 = period 1 + for i in 1 to 3 loop + if (tone_gen_freq(i) = x"000") then + tone_gen_comp(i) := x"000"; + else + tone_gen_comp(i) := (tone_gen_freq(i) - "1"); + end if; + end loop; + + if (ENA = '1') then + for i in 1 to 3 loop + if (ena_div = '1') then -- divider ena + + if (tone_gen_cnt(i) >= tone_gen_comp(i)) then + tone_gen_cnt(i) <= x"000"; + tone_gen_op(i) <= not tone_gen_op(i); + else + tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1"); + end if; + end if; + end loop; + end if; + end process; + + p_envelope_freq : process + variable env_gen_freq : std_logic_vector(15 downto 0); + variable env_gen_comp : std_logic_vector(15 downto 0); + begin + wait until rising_edge(CLK); + env_gen_freq := reg(12) & reg(11); + -- envelope freqs 1 and 0 are the same. + if (env_gen_freq = x"0000") then + env_gen_comp := x"0000"; + else + env_gen_comp := (env_gen_freq - "1"); + end if; + + if (ENA = '1') then + env_ena <= '0'; + if (ena_div = '1') then -- divider ena + if (env_gen_cnt >= env_gen_comp) then + env_gen_cnt <= x"0000"; + env_ena <= '1'; + else + env_gen_cnt <= (env_gen_cnt + "1"); + end if; + end if; + end if; + end process; + + p_envelope_shape : process(env_reset, CLK) + variable is_bot : boolean; + variable is_bot_p1 : boolean; + variable is_top_m1 : boolean; + variable is_top : boolean; + begin + -- envelope shapes + -- C AtAlH + -- 0 0 x x \___ + -- + -- 0 1 x x /___ + -- + -- 1 0 0 0 \\\\ + -- + -- 1 0 0 1 \___ + -- + -- 1 0 1 0 \/\/ + -- ___ + -- 1 0 1 1 \ + -- + -- 1 1 0 0 //// + -- ___ + -- 1 1 0 1 / + -- + -- 1 1 1 0 /\/\ + -- + -- 1 1 1 1 /___ + if (env_reset = '1') then + -- load initial state + if (reg(13)(2) = '0') then -- attack + env_vol <= "11111"; + env_inc <= '0'; -- -1 + else + env_vol <= "00000"; + env_inc <= '1'; -- +1 + end if; + env_hold <= '0'; + + elsif rising_edge(CLK) then + is_bot := (env_vol = "00000"); + is_bot_p1 := (env_vol = "00001"); + is_top_m1 := (env_vol = "11110"); + is_top := (env_vol = "11111"); + + if (ENA = '1') then + if (env_ena = '1') then + if (env_hold = '0') then + if (env_inc = '1') then + env_vol <= (env_vol + "00001"); + else + env_vol <= (env_vol + "11111"); + end if; + end if; + + -- envelope shape control. + if (reg(13)(3) = '0') then + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + else + if is_top then env_hold <= '1'; end if; + end if; + else + if (reg(13)(0) = '1') then -- hold = 1 + if (env_inc = '0') then -- down + if (reg(13)(1) = '1') then -- alt + if is_bot then env_hold <= '1'; end if; + else + if is_bot_p1 then env_hold <= '1'; end if; + end if; + else + if (reg(13)(1) = '1') then -- alt + if is_top then env_hold <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + end if; + end if; + + elsif (reg(13)(1) = '1') then -- alternate + if (env_inc = '0') then -- down + if is_bot_p1 then env_hold <= '1'; end if; + if is_bot then env_hold <= '0'; env_inc <= '1'; end if; + else + if is_top_m1 then env_hold <= '1'; end if; + if is_top then env_hold <= '0'; env_inc <= '0'; end if; + end if; + end if; + + end if; + end if; + end if; + end if; + end process; + + p_chan_mixer_table : process + variable chan_mixed : std_logic_vector(2 downto 0); + begin + wait until rising_edge(CLK); + if (ENA = '1') then + chan_mixed(0) := (reg(7)(0) or tone_gen_op(1)) and (reg(7)(3) or noise_gen_op); + chan_mixed(1) := (reg(7)(1) or tone_gen_op(2)) and (reg(7)(4) or noise_gen_op); + chan_mixed(2) := (reg(7)(2) or tone_gen_op(3)) and (reg(7)(5) or noise_gen_op); + + vol_table_in <= x"000"; + + if (chan_mixed(0) = '1') then + if (reg(8)(4) = '0') then + vol_table_in(3 downto 0) <= reg(8)(3 downto 0); + else + vol_table_in(3 downto 0) <= env_vol(4 downto 1); + end if; + end if; + + if (chan_mixed(1) = '1') then + if (reg(9)(4) = '0') then + vol_table_in(7 downto 4) <= reg(9)(3 downto 0); + else + vol_table_in(7 downto 4) <= env_vol(4 downto 1); + end if; + end if; + + if (chan_mixed(2) = '1') then + if (reg(10)(4) = '0') then + vol_table_in(11 downto 8) <= reg(10)(3 downto 0); + else + vol_table_in(11 downto 8) <= env_vol(4 downto 1); + end if; + end if; + end if; + end process; + + u_vol_table : vol_table + port map ( + CLK => clk, + ADDR => vol_table_in, + DATA => vol_table_out + ); + + p_op_mixer : process + variable chan_mixed : std_logic; + variable chan_amp : std_logic_vector(4 downto 0); + begin + wait until rising_edge(CLK); + + if (RESET_L = '0') then + O_AUDIO(7 downto 0) <= "00000000"; + else + O_AUDIO(7 downto 0) <= vol_table_out(9 downto 2); + end if; + end process; + + p_io_ports : process(reg) + begin + -- input low + O_IOA <= reg(14); + + O_IOA_OE_L <= not reg(7)(6); + O_IOB <= reg(15); + O_IOB_OE_L <= not reg(7)(7); + end process; + + p_io_ports_inreg : process + begin + wait until rising_edge(CLK); + ioa_inreg <= I_IOA; + iob_inreg <= I_IOB; + end process; +end architecture RTL; diff --git a/mockingboard/m6522.vhd b/mockingboard/m6522.vhd new file mode 100644 index 0000000..7a1691d --- /dev/null +++ b/mockingboard/m6522.vhd @@ -0,0 +1,893 @@ +-- +-- A simulation model of VIC20 hardware +-- Copyright (c) MikeJ - March 2003 +-- +-- All rights reserved +-- +-- Redistribution and use in source and synthezised forms, with or without +-- modification, are permitted provided that the following conditions are met: +-- +-- Redistributions of source code must retain the above copyright notice, +-- this list of conditions and the following disclaimer. +-- +-- Redistributions in synthesized form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in the +-- documentation and/or other materials provided with the distribution. +-- +-- Neither the name of the author nor the names of other contributors may +-- be used to endorse or promote products derived from this software without +-- specific prior written permission. +-- +-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +-- POSSIBILITY OF SUCH DAMAGE. +-- +-- You are responsible for any legal issues arising from your use of this code. +-- +-- The latest version of this file can be found at: www.fpgaarcade.com +-- +-- Email vic20@fpgaarcade.com +-- +-- +-- Revision list +-- +-- version 003 Clearing PB7 when T1C-H is written by hoglet +-- version 002 fix from Mark McDougall, untested +-- version 001 initial release +-- not very sure about the shift register, documentation is a bit light. + +library ieee ; + use ieee.std_logic_1164.all ; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + +--library UNISIM; +-- use UNISIM.Vcomponents.all; + +entity M6522 is + port ( + + I_RS : in std_logic_vector(3 downto 0); + I_DATA : in std_logic_vector(7 downto 0); + O_DATA : out std_logic_vector(7 downto 0); + O_DATA_OE_L : out std_logic; + + I_RW_L : in std_logic; + I_CS1 : in std_logic; + I_CS2_L : in std_logic; + + O_IRQ_L : out std_logic; -- note, not open drain + -- port a + I_CA1 : in std_logic; + I_CA2 : in std_logic; + O_CA2 : out std_logic; + O_CA2_OE_L : out std_logic; + + I_PA : in std_logic_vector(7 downto 0); + O_PA : out std_logic_vector(7 downto 0); + O_PA_OE_L : out std_logic_vector(7 downto 0); + + -- port b + I_CB1 : in std_logic; + O_CB1 : out std_logic; + O_CB1_OE_L : out std_logic; + + I_CB2 : in std_logic; + O_CB2 : out std_logic; + O_CB2_OE_L : out std_logic; + + I_PB : in std_logic_vector(7 downto 0); + O_PB : out std_logic_vector(7 downto 0); + O_PB_OE_L : out std_logic_vector(7 downto 0); + + I_P2_H : in std_logic; -- high for phase 2 clock ____----__ + RESET_L : in std_logic; + ENA_4 : in std_logic; -- clk enable + CLK : in std_logic + ); +end; + +architecture RTL of M6522 is + + signal phase : std_logic_vector(1 downto 0); + signal p2_h_t1 : std_logic; + signal cs : std_logic; + + -- registers + signal r_ddra : std_logic_vector(7 downto 0); + signal r_ora : std_logic_vector(7 downto 0); + signal r_ira : std_logic_vector(7 downto 0); + + signal r_ddrb : std_logic_vector(7 downto 0); + signal r_orb : std_logic_vector(7 downto 0); + signal r_irb : std_logic_vector(7 downto 0); + + signal r_t1l_l : std_logic_vector(7 downto 0); + signal r_t1l_h : std_logic_vector(7 downto 0); + signal r_t2l_l : std_logic_vector(7 downto 0); + signal r_t2l_h : std_logic_vector(7 downto 0); -- not in real chip + signal r_sr : std_logic_vector(7 downto 0); + signal r_acr : std_logic_vector(7 downto 0); + signal r_pcr : std_logic_vector(7 downto 0); + signal r_ifr : std_logic_vector(7 downto 0); + signal r_ier : std_logic_vector(6 downto 0); + + signal sr_write_ena : boolean; + signal sr_read_ena : boolean; + signal ifr_write_ena : boolean; + signal ier_write_ena : boolean; + signal clear_irq : std_logic_vector(7 downto 0); + signal load_data : std_logic_vector(7 downto 0); + + -- timer 1 + signal t1c : std_logic_vector(15 downto 0); + signal t1c_active : boolean; + signal t1c_done : boolean; + signal t1_w_reset_int : boolean; + signal t1_r_reset_int : boolean; + signal t1_load_counter : boolean; + signal t1_reload_counter : boolean; + signal t1_toggle : std_logic; + signal t1_irq : std_logic := '0'; + + -- timer 2 + signal t2c : std_logic_vector(15 downto 0); + signal t2c_active : boolean; + signal t2c_done : boolean; + signal t2_pb6 : std_logic; + signal t2_pb6_t1 : std_logic; + signal t2_w_reset_int : boolean; + signal t2_r_reset_int : boolean; + signal t2_load_counter : boolean; + signal t2_reload_counter : boolean; + signal t2_irq : std_logic := '0'; + signal t2_sr_ena : boolean; + + -- shift reg + signal sr_cnt : std_logic_vector(3 downto 0); + signal sr_cb1_oe_l : std_logic; + signal sr_cb1_out : std_logic; + signal sr_drive_cb2 : std_logic; + signal sr_strobe : std_logic; + signal sr_strobe_t1 : std_logic; + signal sr_strobe_falling : boolean; + signal sr_strobe_rising : boolean; + signal sr_irq : std_logic; + signal sr_out : std_logic; + signal sr_off_delay : std_logic; + + -- io + signal w_orb_hs : std_logic; + signal w_ora_hs : std_logic; + signal r_irb_hs : std_logic; + signal r_ira_hs : std_logic; + + signal ca_hs_sr : std_logic; + signal ca_hs_pulse : std_logic; + signal cb_hs_sr : std_logic; + signal cb_hs_pulse : std_logic; + + signal cb1_in_mux : std_logic; + signal ca1_ip_reg : std_logic; + signal cb1_ip_reg : std_logic; + signal ca1_int : boolean; + signal cb1_int : boolean; + signal ca1_irq : std_logic; + signal cb1_irq : std_logic; + + signal ca2_ip_reg : std_logic; + signal cb2_ip_reg : std_logic; + signal ca2_int : boolean; + signal cb2_int : boolean; + signal ca2_irq : std_logic; + signal cb2_irq : std_logic; + + signal final_irq : std_logic; +begin + p_phase : process + begin + -- internal clock phase + wait until rising_edge(CLK); + if (ENA_4 = '1') then + p2_h_t1 <= I_P2_H; + if (p2_h_t1 = '0') and (I_P2_H = '1') then + phase <= "11"; + else + phase <= phase + "1"; + end if; + end if; + end process; + + p_cs : process(I_CS1, I_CS2_L, I_P2_H) + begin + cs <= '0'; + if (I_CS1 = '1') and (I_CS2_L = '0') and (I_P2_H = '1') then + cs <= '1'; + end if; + end process; + + -- peripheral control reg (pcr) + -- 0 ca1 interrupt control (0 +ve edge, 1 -ve edge) + -- 3..1 ca2 operation + -- 000 input -ve edge + -- 001 independend interrupt input -ve edge + -- 010 input +ve edge + -- 011 independend interrupt input +ve edge + -- 100 handshake output + -- 101 pulse output + -- 110 low output + -- 111 high output + -- 7..4 as 3..0 for cb1,cb2 + + -- auxiliary control reg (acr) + -- 0 input latch PA (0 disable, 1 enable) + -- 1 input latch PB (0 disable, 1 enable) + -- 4..2 shift reg control + -- 000 disable + -- 001 shift in using t2 + -- 010 shift in using o2 + -- 011 shift in using ext clk + -- 100 shift out free running t2 rate + -- 101 shift out using t2 + -- 101 shift out using o2 + -- 101 shift out using ext clk + -- 5 t2 timer control (0 timed interrupt, 1 count down with pulses on pb6) + -- 7..6 t1 timer control + -- 00 timed interrupt each time t1 is loaded pb7 disable + -- 01 continuous interrupts pb7 disable + -- 00 timed interrupt each time t1 is loaded pb7 one shot output + -- 01 continuous interrupts pb7 square wave output + -- + + p_write_reg_reset : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + r_ora <= x"00"; r_orb <= x"00"; + r_ddra <= x"00"; r_ddrb <= x"00"; + r_acr <= x"00"; r_pcr <= x"00"; + + w_orb_hs <= '0'; + w_ora_hs <= '0'; + elsif rising_edge(CLK) then + if (ENA_4 = '1') then + w_orb_hs <= '0'; + w_ora_hs <= '0'; + if (cs = '1') and (I_RW_L = '0') then + case I_RS is + when x"0" => r_orb <= I_DATA; w_orb_hs <= '1'; + when x"1" => r_ora <= I_DATA; w_ora_hs <= '1'; + when x"2" => r_ddrb <= I_DATA; + when x"3" => r_ddra <= I_DATA; + + when x"B" => r_acr <= I_DATA; + when x"C" => r_pcr <= I_DATA; + when x"F" => r_ora <= I_DATA; + + when others => null; + end case; + end if; + + if (r_acr(7) = '1') then + if t1_load_counter then + r_orb(7) <= '0'; -- writing T1C-H resets bit 7 + elsif (t1_toggle = '1') then + r_orb(7) <= not r_orb(7); -- toggle + end if; + end if; + end if; + end if; + end process; + + p_write_reg : process + begin + wait until rising_edge(CLK); + if (ENA_4 = '1') then + t1_w_reset_int <= false; + t1_load_counter <= false; + + t2_w_reset_int <= false; + t2_load_counter <= false; + + load_data <= x"00"; + sr_write_ena <= false; + ifr_write_ena <= false; + ier_write_ena <= false; + + if (cs = '1') and (I_RW_L = '0') then + load_data <= I_DATA; + case I_RS is + when x"4" => r_t1l_l <= I_DATA; + when x"5" => r_t1l_h <= I_DATA; t1_w_reset_int <= true; + t1_load_counter <= true; + + when x"6" => r_t1l_l <= I_DATA; + when x"7" => r_t1l_h <= I_DATA; t1_w_reset_int <= true; + + when x"8" => r_t2l_l <= I_DATA; + when x"9" => r_t2l_h <= I_DATA; t2_w_reset_int <= true; + t2_load_counter <= true; + + when x"A" => sr_write_ena <= true; + when x"D" => ifr_write_ena <= true; + when x"E" => ier_write_ena <= true; + + when others => null; + end case; + end if; + end if; + end process; + + p_oe : process(cs, I_RW_L) + begin + O_DATA_OE_L <= '1'; + if (cs = '1') and (I_RW_L = '1') then + O_DATA_OE_L <= '0'; + end if; + end process; + + p_read : process + begin + wait until rising_edge(CLK); + + if ENA_4 = '1' then + t1_r_reset_int <= false; + t2_r_reset_int <= false; + sr_read_ena <= false; + r_irb_hs <= '0'; + r_ira_hs <= '0'; + + if (cs = '1') and (I_RW_L = '1') then + case I_RS is + --when x"0" => O_DATA <= r_irb; r_irb_hs <= '1'; + -- fix from Mark McDougall, untested + when x"0" => O_DATA <= (r_irb and not r_ddrb) or (r_orb and r_ddrb); r_irb_hs <= '1'; + when x"1" => O_DATA <= r_ira; r_ira_hs <= '1'; + when x"2" => O_DATA <= r_ddrb; + when x"3" => O_DATA <= r_ddra; + when x"4" => O_DATA <= t1c( 7 downto 0); t1_r_reset_int <= true; + when x"5" => O_DATA <= t1c(15 downto 8); + when x"6" => O_DATA <= r_t1l_l; + when x"7" => O_DATA <= r_t1l_h; + when x"8" => O_DATA <= t2c( 7 downto 0); t2_r_reset_int <= true; + when x"9" => O_DATA <= t2c(15 downto 8); + when x"A" => O_DATA <= r_sr; sr_read_ena <= true; + when x"B" => O_DATA <= r_acr; + when x"C" => O_DATA <= r_pcr; + when x"D" => O_DATA <= r_ifr; + when x"E" => O_DATA <= ('0' & r_ier); + when x"F" => O_DATA <= r_ira; + when others => null; + end case; + end if; + end if; + + end process; + -- + -- IO + -- + p_ca1_cb1_sel : process(sr_cb1_oe_l, sr_cb1_out, I_CB1) + begin + -- if the shift register is enabled, cb1 may be an output + -- in this case, we should listen to the CB1_OUT for the interrupt + if (sr_cb1_oe_l = '1') then + cb1_in_mux <= I_CB1; + else + cb1_in_mux <= sr_cb1_out; + end if; + end process; + + p_ca1_cb1_int : process(r_pcr, ca1_ip_reg, I_CA1, cb1_ip_reg, cb1_in_mux) + begin + if (r_pcr(0) = '0') then -- ca1 control + -- negative edge + ca1_int <= (ca1_ip_reg = '1') and (I_CA1 = '0'); + else + -- positive edge + ca1_int <= (ca1_ip_reg = '0') and (I_CA1 = '1'); + end if; + + if (r_pcr(4) = '0') then -- cb1 control + -- negative edge + cb1_int <= (cb1_ip_reg = '1') and (cb1_in_mux = '0'); + else + -- positive edge + cb1_int <= (cb1_ip_reg = '0') and (cb1_in_mux = '1'); + end if; + end process; + + p_ca2_cb2_int : process(r_pcr, ca2_ip_reg, I_CA2, cb2_ip_reg, I_CB2) + begin + ca2_int <= false; + if (r_pcr(3) = '0') then -- ca2 input + if (r_pcr(2) = '0') then -- ca2 edge + -- negative edge + ca2_int <= (ca2_ip_reg = '1') and (I_CA2 = '0'); + else + -- positive edge + ca2_int <= (ca2_ip_reg = '0') and (I_CA2 = '1'); + end if; + end if; + + cb2_int <= false; + if (r_pcr(7) = '0') then -- cb2 input + if (r_pcr(6) = '0') then -- cb2 edge + -- negative edge + cb2_int <= (cb2_ip_reg = '1') and (I_CB2 = '0'); + else + -- positive edge + cb2_int <= (cb2_ip_reg = '0') and (I_CB2 = '1'); + end if; + end if; + end process; + + p_ca2_cb2 : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + O_CA2 <= '0'; + O_CA2_OE_L <= '1'; + O_CB2 <= '0'; + O_CB2_OE_L <= '1'; + + ca_hs_sr <= '0'; + ca_hs_pulse <= '0'; + cb_hs_sr <= '0'; + cb_hs_pulse <= '0'; + elsif rising_edge(CLK) then + if (ENA_4 = '1') then + -- ca + if (phase = "00") and ((w_ora_hs = '1') or (r_ira_hs = '1')) then + ca_hs_sr <= '1'; + elsif ca1_int then + ca_hs_sr <= '0'; + end if; + + if (phase = "00") then + ca_hs_pulse <= w_ora_hs or r_ira_hs; + end if; + + O_CA2_OE_L <= not r_pcr(3); -- ca2 output + case r_pcr(3 downto 1) is + when "000" => O_CA2 <= '0'; -- input + when "001" => O_CA2 <= '0'; -- input + when "010" => O_CA2 <= '0'; -- input + when "011" => O_CA2 <= '0'; -- input + when "100" => O_CA2 <= not (ca_hs_sr); -- handshake + when "101" => O_CA2 <= not (ca_hs_pulse); -- pulse + when "110" => O_CA2 <= '0'; -- low + when "111" => O_CA2 <= '1'; -- high + when others => null; + end case; + + -- cb + if (phase = "00") and (w_orb_hs = '1') then + cb_hs_sr <= '1'; + elsif cb1_int then + cb_hs_sr <= '0'; + end if; + + if (phase = "00") then + cb_hs_pulse <= w_orb_hs; + end if; + + O_CB2_OE_L <= not (r_pcr(7) or sr_drive_cb2); -- cb2 output or serial + if (sr_drive_cb2 = '1') then -- serial output + O_CB2 <= sr_out; + else + case r_pcr(7 downto 5) is + when "000" => O_CB2 <= '0'; -- input + when "001" => O_CB2 <= '0'; -- input + when "010" => O_CB2 <= '0'; -- input + when "011" => O_CB2 <= '0'; -- input + when "100" => O_CB2 <= not (cb_hs_sr); -- handshake + when "101" => O_CB2 <= not (cb_hs_pulse); -- pulse + when "110" => O_CB2 <= '0'; -- low + when "111" => O_CB2 <= '1'; -- high + when others => null; + end case; + end if; + end if; + end if; + end process; + O_CB1 <= sr_cb1_out; + O_CB1_OE_L <= sr_cb1_oe_l; + + p_ca_cb_irq : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + ca1_irq <= '0'; + ca2_irq <= '0'; + cb1_irq <= '0'; + cb2_irq <= '0'; + elsif rising_edge(CLK) then + if (ENA_4 = '1') then + -- not pretty + if ca1_int then + ca1_irq <= '1'; + elsif (r_ira_hs = '1') or (w_ora_hs = '1') or (clear_irq(1) = '1') then + ca1_irq <= '0'; + end if; + + if ca2_int then + ca2_irq <= '1'; + else + if (((r_ira_hs = '1') or (w_ora_hs = '1')) and (r_pcr(1) = '0')) or + (clear_irq(0) = '1') then + ca2_irq <= '0'; + end if; + end if; + + if cb1_int then + cb1_irq <= '1'; + elsif (r_irb_hs = '1') or (w_orb_hs = '1') or (clear_irq(4) = '1') then + cb1_irq <= '0'; + end if; + + if cb2_int then + cb2_irq <= '1'; + else + if (((r_irb_hs = '1') or (w_orb_hs = '1')) and (r_pcr(5) = '0')) or + (clear_irq(3) = '1') then + cb2_irq <= '0'; + end if; + end if; + end if; + end if; + end process; + + p_input_reg : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + ca1_ip_reg <= '0'; + cb1_ip_reg <= '0'; + + ca2_ip_reg <= '0'; + cb2_ip_reg <= '0'; + + r_ira <= x"00"; + r_irb <= x"00"; + + elsif rising_edge(CLK) then + if (ENA_4 = '1') then + -- we have a fast clock, so we can have input registers + ca1_ip_reg <= I_CA1; + cb1_ip_reg <= cb1_in_mux; + + ca2_ip_reg <= I_CA2; + cb2_ip_reg <= I_CB2; + + if (r_acr(0) = '0') then + r_ira <= I_PA; + else -- enable latching + if ca1_int then + r_ira <= I_PA; + end if; + end if; + + if (r_acr(1) = '0') then + r_irb <= I_PB; + else -- enable latching + if cb1_int then + r_irb <= I_PB; + end if; + end if; + end if; + end if; + end process; + + + p_buffers : process(r_ddra, r_ora, r_ddrb, r_acr, r_orb) + begin + -- data direction reg (ddr) 0 = input, 1 = output + O_PA <= r_ora; + O_PA_OE_L <= not r_ddra; + + if (r_acr(7) = '1') then -- not clear if r_ddrb(7) must be 1 as well + O_PB_OE_L(7) <= '0'; -- an output if under t1 control + else + O_PB_OE_L(7) <= not (r_ddrb(7)); + end if; + + O_PB_OE_L(6 downto 0) <= not r_ddrb(6 downto 0); + O_PB(7 downto 0) <= r_orb(7 downto 0); + + end process; + -- + -- Timer 1 + -- + p_timer1_done : process(t1c,phase,r_acr) + variable done : boolean; + begin + done := (t1c = x"0000"); + t1c_done <= done and (phase = "11"); + --if (phase = "11") then + t1_reload_counter <= done and (r_acr(6) = '1'); + --end if; + end process; + + p_timer1 : process + begin + wait until rising_edge(CLK); + if (ENA_4 = '1') then + if t1_load_counter or (t1_reload_counter and phase = "11") then + t1c( 7 downto 0) <= r_t1l_l; + t1c(15 downto 8) <= r_t1l_h; + elsif (phase="11") then + t1c <= t1c - "1"; + end if; + + if t1_load_counter or t1_reload_counter then + t1c_active <= true; + elsif t1c_done then + t1c_active <= false; + end if; + if RESET_L = '0' then + t1c_active <= false; + end if; + + t1_toggle <= '0'; + if t1c_active and t1c_done then + t1_toggle <= '1'; + t1_irq <= '1'; + elsif RESET_L = '0' or t1_w_reset_int or t1_r_reset_int or (clear_irq(6) = '1') then + t1_irq <= '0'; + end if; + end if; + end process; + -- + -- Timer2 + -- + p_timer2_pb6_input : process + begin + wait until rising_edge(CLK); + if (ENA_4 = '1') then + if (phase = "01") then -- leading edge p2_h + t2_pb6 <= I_PB(6); + t2_pb6_t1 <= t2_pb6; + end if; + end if; + end process; + + p_timer2_done : process(t2c,phase) + variable done : boolean; + begin + done := (t2c = x"0000"); + t2c_done <= done and (phase = "11"); + --if (phase = "11") then + t2_reload_counter <= done; + --end if; + end process; + + p_timer2 : process + variable ena : boolean; + begin + wait until rising_edge(CLK); + if (ENA_4 = '1') then + if (r_acr(5) = '0') then + ena := true; + else + ena := (t2_pb6_t1 = '1') and (t2_pb6 = '0'); -- falling edge + end if; + + if t2_load_counter or (t2_reload_counter and phase = "11") then + -- not sure if t2c_reload should be here. Does timer2 just continue to + -- count down, or is it reloaded ? Reloaded makes more sense if using + -- it to generate a clock for the shift register. + t2c( 7 downto 0) <= r_t2l_l; + t2c(15 downto 8) <= r_t2l_h; + else + if (phase="11") and ena then -- or count mode + t2c <= t2c - "1"; + end if; + end if; + + t2_sr_ena <= (t2c(7 downto 0) = x"00") and (phase = "11"); + + if t2_load_counter then + t2c_active <= true; + elsif t2c_done then + t2c_active <= false; + end if; + if RESET_L = '0' then + t2c_active <= false; + end if; + + if t2c_active and t2c_done then + t2_irq <= '1'; + elsif RESET_L = '0' or t2_w_reset_int or t2_r_reset_int or (clear_irq(5) = '1') then + t2_irq <= '0'; + end if; + end if; + end process; + -- + -- Shift Register + -- + p_sr : process(RESET_L, CLK) + variable dir_out : std_logic; + variable ena : std_logic; + variable cb1_op : std_logic; + variable cb1_ip : std_logic; + variable use_t2 : std_logic; + variable free_run : std_logic; + variable sr_count_ena : boolean; + begin + if (RESET_L = '0') then + r_sr <= x"00"; + sr_drive_cb2 <= '0'; + sr_cb1_oe_l <= '1'; + sr_cb1_out <= '0'; + sr_strobe <= '1'; + sr_cnt <= "0000"; + sr_irq <= '0'; + sr_out <= '1'; + sr_off_delay <= '0'; + elsif rising_edge(CLK) then + if (ENA_4 = '1') then + -- decode mode + dir_out := r_acr(4); -- output on cb2 + cb1_op := '0'; + cb1_ip := '0'; + use_t2 := '0'; + free_run := '0'; + + case r_acr(4 downto 2) is + when "000" => ena := '0'; cb1_ip := '1'; + when "001" => ena := '1'; cb1_op := '1'; use_t2 := '1'; + when "010" => ena := '1'; cb1_op := '1'; + when "011" => ena := '1'; cb1_ip := '1'; + when "100" => ena := '1'; use_t2 := '1'; free_run := '1'; + when "101" => ena := '1'; cb1_op := '1'; use_t2 := '1'; + when "110" => ena := '1'; + when "111" => ena := '1'; cb1_ip := '1'; + when others => null; + end case; + + -- clock select + -- SR still runs even in disabled mode (on rising edge of CB1). It + -- just doesn't generate any interrupts. + -- Ref BBC micro advanced user guide p409 + if (cb1_ip = '1') then + sr_strobe <= I_CB1; + else + if (sr_cnt(3) = '0') and (free_run = '0') then + sr_strobe <= '1'; + else + if ((use_t2 = '1') and t2_sr_ena) or + ((use_t2 = '0') and (phase = "00")) then + sr_strobe <= not sr_strobe; + end if; + end if; + end if; + + -- latch on rising edge, shift on falling edge + if sr_write_ena then + r_sr <= load_data; + else + if (dir_out = '0') then + -- input + if (sr_cnt(3) = '1') or (cb1_ip = '1') then + if sr_strobe_rising then + r_sr(0) <= I_CB2; + elsif sr_strobe_falling then + r_sr(7 downto 1) <= r_sr(6 downto 0); + end if; + end if; + sr_out <= '1'; + else + -- output + if (sr_cnt(3) = '1') or (sr_off_delay = '1') or (cb1_ip = '1') or (free_run = '1') then + if sr_strobe_falling then + r_sr(7 downto 1) <= r_sr(6 downto 0); + r_sr(0) <= r_sr(7); + sr_out <= r_sr(7); + end if; + else + sr_out <= '1'; + end if; + end if; + end if; + + sr_count_ena := sr_strobe_rising; + + if ena = '1' and (sr_write_ena or sr_read_ena) then + -- some documentation says sr bit in IFR must be set as well ? + sr_cnt <= "1000"; + elsif sr_count_ena and (sr_cnt(3) = '1') then + sr_cnt <= sr_cnt + "1"; + end if; + + if (phase = "00") then + sr_off_delay <= sr_cnt(3); -- give some hold time when shifting out + end if; + + if sr_count_ena and (sr_cnt = "1111") and (ena = '1') and (free_run = '0') then + sr_irq <= '1'; + elsif sr_write_ena or sr_read_ena or (clear_irq(2) = '1') then + sr_irq <= '0'; + end if; + + -- assign ops + sr_drive_cb2 <= dir_out; + sr_cb1_oe_l <= not cb1_op; + sr_cb1_out <= sr_strobe; + end if; + end if; + end process; + + p_sr_strobe_rise_fall : process + begin + wait until rising_edge(CLK); + if (ENA_4 = '1') then + sr_strobe_t1 <= sr_strobe; + sr_strobe_rising <= (sr_strobe_t1 = '0') and (sr_strobe = '1'); + sr_strobe_falling <= (sr_strobe_t1 = '1') and (sr_strobe = '0'); + end if; + end process; + -- + -- Interrupts + -- + p_ier : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + r_ier <= "0000000"; + elsif rising_edge(CLK) then + if (ENA_4 = '1') then + if ier_write_ena then + if (load_data(7) = '1') then + -- set + r_ier <= r_ier or load_data(6 downto 0); + else + -- clear + r_ier <= r_ier and not load_data(6 downto 0); + end if; + end if; + end if; + end if; + end process; + + p_ifr : process(t1_irq, t2_irq, final_irq, ca1_irq, ca2_irq, sr_irq, + cb1_irq, cb2_irq) + begin + r_ifr(7) <= final_irq; + r_ifr(6) <= t1_irq; + r_ifr(5) <= t2_irq; + r_ifr(4) <= cb1_irq; + r_ifr(3) <= cb2_irq; + r_ifr(2) <= sr_irq; + r_ifr(1) <= ca1_irq; + r_ifr(0) <= ca2_irq; + + O_IRQ_L <= not final_irq; + end process; + + p_irq : process(RESET_L, CLK) + begin + if (RESET_L = '0') then + final_irq <= '0'; + elsif rising_edge(CLK) then + if (ENA_4 = '1') then + if ((r_ifr(6 downto 0) and r_ier(6 downto 0)) = "0000000") then + final_irq <= '0'; -- no interrupts + else + final_irq <= '1'; + end if; + end if; + end if; + end process; + + p_clear_irq : process(ifr_write_ena, load_data) + begin + clear_irq <= x"00"; + if ifr_write_ena then + clear_irq <= load_data; + end if; + end process; + +end architecture RTL; diff --git a/mockingboard/mockingboard.vhd b/mockingboard/mockingboard.vhd new file mode 100644 index 0000000..c9990cc --- /dev/null +++ b/mockingboard/mockingboard.vhd @@ -0,0 +1,214 @@ +-- +-- Mockingboard clone for the Apple II +-- Model A: two AY-3-8913 chips for six audio channels +-- +-- Top file by W. Soltys +-- +-- loosely based on: +-- http://www.downloads.reactivemicro.com/Public/Apple%20II%20Items/Hardware/Mockingboard_v1/Mockingboard-v1a-Docs.pdf +-- http://www.applelogic.org/CarteBlancheIIProj6.html +-- + +library ieee ; + use ieee.std_logic_1164.all ; + use ieee.std_logic_unsigned.all; + use ieee.numeric_std.all; + + +entity MOCKINGBOARD is + port ( + + I_ADDR : in std_logic_vector(7 downto 0); + I_DATA : in std_logic_vector(7 downto 0); + O_DATA : out std_logic_vector(7 downto 0); + + I_RW_L : in std_logic; + O_IRQ_L : out std_logic; + I_IOSEL_L : in std_logic; + I_RESET_L : in std_logic; + I_ENA_H : in std_logic; + + O_AUDIO_L : out std_logic_vector(7 downto 0); + O_AUDIO_R : out std_logic_vector(7 downto 0); + CLK_VIA : in std_logic; + CLK_PSG : in std_logic; + I_P2_H : in std_logic + ); + end; + + + architecture RTL of MOCKINGBOARD is + + signal o_pb_l : std_logic_vector(7 downto 0); + signal o_pb_r : std_logic_vector(7 downto 0); + + signal i_psg_r : std_logic_vector(7 downto 0); + signal i_psg_l : std_logic_vector(7 downto 0); + + signal o_data_l : std_logic_vector(7 downto 0); + signal o_data_r : std_logic_vector(7 downto 0); + + signal lvia_read : std_logic; + signal rvia_read : std_logic; + + signal lirq_l : std_logic; + signal rirq_l : std_logic; + + +begin + + O_DATA <= o_data_l when lvia_read = '1' else o_data_r when rvia_read = '1' else (others=>'Z'); + + lvia_read <= I_RW_L and not I_ADDR(7); + rvia_read <= I_RW_L and I_ADDR(7); + + O_IRQ_L <= lirq_l and rirq_l; + +-- Left Channel Combo + + m6522_left : work.M6522 + port map ( + I_RS => I_ADDR(3 downto 0), + I_DATA => I_DATA, + O_DATA => o_data_l, + O_DATA_OE_L => open, + + I_RW_L => I_RW_L, + I_CS1 => not I_ADDR(7), + I_CS2_L => I_IOSEL_L, + + O_IRQ_L => lirq_l, + -- port a + I_CA1 => '0', + I_CA2 => '0', + O_CA2 => open, + O_CA2_OE_L => open, + + I_PA => (others => '0'), + O_PA => i_psg_l, + O_PA_OE_L => open, + + -- port b + I_CB1 => '0', + O_CB1 => open, + O_CB1_OE_L => open, + + I_CB2 => '0', + O_CB2 => open, + O_CB2_OE_L => open, + + I_PB => (others => '0'), + O_PB => o_pb_l, + O_PB_OE_L => open, + + I_P2_H => I_P2_H, + RESET_L => I_RESET_L, + ENA_4 => '1', + CLK => CLK_VIA and I_ENA_H + ); + + + psg_left : work.YM2149 + port map ( + -- data bus + I_DA => i_psg_l, + O_DA => open, + O_DA_OE_L => open, + -- control + I_A9_L => '0', -- /A9 pulled down internally + I_A8 => '1', + I_BDIR => o_pb_l(1), + I_BC2 => '1', + I_BC1 => o_pb_l(0), + I_SEL_L => '1', -- /SEL is high for AY-3-8912 compatibility + + O_AUDIO => O_AUDIO_L, + -- port a + I_IOA => (others => '0'), -- port A unused + O_IOA => open, + O_IOA_OE_L => open, + -- port b + I_IOB => (others => '0'), -- port B unused + O_IOB => open, + O_IOB_OE_L => open, + -- + ENA => '1', + RESET_L => o_pb_l(2), + CLK => CLK_PSG and I_ENA_H + ); + + +-- Right Channel Combo + + m6522_right : work.M6522 + port map ( + I_RS => I_ADDR(3 downto 0), + I_DATA => I_DATA, + O_DATA => o_data_r, + O_DATA_OE_L => open, + + I_RW_L => I_RW_L, + I_CS1 => I_ADDR(7), + I_CS2_L => I_IOSEL_L, + + O_IRQ_L => rirq_l, + -- port a + I_CA1 => '0', + I_CA2 => '0', + O_CA2 => open, + O_CA2_OE_L => open, + + I_PA => (others => '0'), + O_PA => i_psg_r, + O_PA_OE_L => open, + + -- port b + I_CB1 => '0', + O_CB1 => open, + O_CB1_OE_L => open, + + I_CB2 => '0', + O_CB2 => open, + O_CB2_OE_L => open, + + I_PB => (others => '0'), + O_PB => o_pb_r, + O_PB_OE_L => open, + + I_P2_H => I_P2_H, + RESET_L => I_RESET_L, + ENA_4 => '1', + CLK => CLK_VIA and I_ENA_H + ); + + + psg_right : work.YM2149 + port map ( + -- data bus + I_DA => i_psg_r, + O_DA => open, + O_DA_OE_L => open, + -- control + I_A9_L => '0', -- /A9 pulled down internally + I_A8 => '1', + I_BDIR => o_pb_r(1), + I_BC2 => '1', + I_BC1 => o_pb_r(0), + I_SEL_L => '1', -- /SEL is high for AY-3-8912 compatibility + + O_AUDIO => O_AUDIO_R, + -- port a + I_IOA => (others => '0'), -- port A unused + O_IOA => open, + O_IOA_OE_L => open, + -- port b + I_IOB => (others => '0'), -- port B unused + O_IOB => open, + O_IOB_OE_L => open, + -- + ENA => '1', + RESET_L => o_pb_r(2), + CLK => CLK_PSG and I_ENA_H + ); + +end architecture RTL; \ No newline at end of file diff --git a/mockingboard/schematic.gif b/mockingboard/schematic.gif new file mode 100644 index 0000000..2767e6d Binary files /dev/null and b/mockingboard/schematic.gif differ diff --git a/mockingboard/vol_table_array.vhd b/mockingboard/vol_table_array.vhd new file mode 100644 index 0000000..ea644ea --- /dev/null +++ b/mockingboard/vol_table_array.vhd @@ -0,0 +1,540 @@ +-- generated with tablegen by MikeJ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vol_table is + port ( + CLK : in std_logic; + ADDR : in std_logic_vector(11 downto 0); + DATA : out std_logic_vector(9 downto 0) + ); +end; + +architecture RTL of vol_table is + + + type ROM_ARRAY is array(0 to 4095) of std_logic_vector(11 downto 0); + constant ROM : ROM_ARRAY := ( + x"000",x"002",x"004",x"006",x"009",x"00D",x"014",x"01B", -- 0x0000 + x"027",x"036",x"050",x"06D",x"0A5",x"0EB",x"17D",x"24D", -- 0x0008 + x"002",x"005",x"007",x"009",x"00D",x"010",x"016",x"01D", -- 0x0010 + x"02A",x"038",x"051",x"06F",x"0A7",x"0ED",x"17E",x"24D", -- 0x0018 + x"004",x"007",x"009",x"00B",x"00E",x"012",x"018",x"020", -- 0x0020 + x"02B",x"03A",x"054",x"071",x"0A9",x"0EF",x"17E",x"24D", -- 0x0028 + x"006",x"009",x"00B",x"00D",x"011",x"014",x"01A",x"021", -- 0x0030 + x"02E",x"03C",x"055",x"073",x"0AB",x"0F0",x"17F",x"24D", -- 0x0038 + x"009",x"00D",x"00E",x"011",x"014",x"018",x"01D",x"024", -- 0x0040 + x"031",x"03F",x"058",x"076",x"0AD",x"0F3",x"180",x"24D", -- 0x0048 + x"00D",x"010",x"012",x"014",x"018",x"01B",x"021",x"028", -- 0x0050 + x"035",x"042",x"05C",x"079",x"0B0",x"0F5",x"182",x"24D", -- 0x0058 + x"014",x"016",x"018",x"01A",x"01D",x"021",x"027",x"02F", -- 0x0060 + x"03A",x"049",x"062",x"07E",x"0B5",x"0FA",x"184",x"24D", -- 0x0068 + x"01B",x"01D",x"020",x"021",x"024",x"028",x"02F",x"035", -- 0x0070 + x"042",x"050",x"068",x"085",x"0BB",x"0FE",x"188",x"24D", -- 0x0078 + x"027",x"02A",x"02B",x"02E",x"031",x"035",x"03A",x"042", -- 0x0080 + x"04D",x"05C",x"073",x"091",x"0C5",x"108",x"18E",x"24D", -- 0x0088 + x"036",x"038",x"03A",x"03C",x"03F",x"042",x"049",x"050", -- 0x0090 + x"05C",x"06A",x"082",x"09D",x"0D2",x"114",x"19A",x"24D", -- 0x0098 + x"050",x"051",x"054",x"055",x"058",x"05C",x"062",x"068", -- 0x00A0 + x"073",x"082",x"098",x"0B4",x"0E7",x"128",x"1AB",x"254", -- 0x00A8 + x"06D",x"06F",x"071",x"073",x"076",x"079",x"07E",x"085", -- 0x00B0 + x"091",x"09D",x"0B4",x"0D0",x"102",x"142",x"1C1",x"264", -- 0x00B8 + x"0A5",x"0A7",x"0A9",x"0AB",x"0AD",x"0B0",x"0B5",x"0BB", -- 0x00C0 + x"0C5",x"0D2",x"0E7",x"102",x"133",x"172",x"1ED",x"27C", -- 0x00C8 + x"0EB",x"0ED",x"0EF",x"0F0",x"0F3",x"0F5",x"0FA",x"0FE", -- 0x00D0 + x"108",x"114",x"128",x"142",x"172",x"1AF",x"21D",x"2AB", -- 0x00D8 + x"17D",x"17E",x"17E",x"17F",x"180",x"182",x"184",x"188", -- 0x00E0 + x"18E",x"19A",x"1AB",x"1C1",x"1ED",x"21D",x"284",x"30A", -- 0x00E8 + x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x00F0 + x"24D",x"24D",x"254",x"264",x"27C",x"2AB",x"30A",x"379", -- 0x00F8 + x"002",x"005",x"006",x"009",x"00C",x"010",x"016",x"01D", -- 0x0100 + x"02A",x"038",x"052",x"06F",x"0A7",x"0ED",x"17E",x"24E", -- 0x0108 + x"005",x"007",x"009",x"00B",x"00F",x"012",x"018",x"01F", -- 0x0110 + x"02C",x"03A",x"053",x"071",x"0A9",x"0EF",x"17F",x"24E", -- 0x0118 + x"006",x"009",x"00B",x"00D",x"011",x"014",x"01B",x"022", -- 0x0120 + x"02E",x"03D",x"056",x"073",x"0AB",x"0F0",x"180",x"24E", -- 0x0128 + x"009",x"00B",x"00D",x"010",x"013",x"016",x"01C",x"023", -- 0x0130 + x"030",x"03E",x"057",x"075",x"0AD",x"0F2",x"181",x"24E", -- 0x0138 + x"00C",x"00F",x"011",x"013",x"016",x"01A",x"01F",x"027", -- 0x0140 + x"033",x"041",x"05B",x"078",x"0AF",x"0F4",x"181",x"24E", -- 0x0148 + x"010",x"012",x"014",x"016",x"01A",x"01D",x"023",x"02A", -- 0x0150 + x"037",x"044",x"05E",x"07B",x"0B2",x"0F7",x"183",x"24E", -- 0x0158 + x"016",x"018",x"01B",x"01C",x"01F",x"023",x"02A",x"031", -- 0x0160 + x"03D",x"04B",x"064",x"080",x"0B7",x"0FB",x"185",x"24E", -- 0x0168 + x"01D",x"01F",x"022",x"023",x"027",x"02A",x"031",x"037", -- 0x0170 + x"044",x"052",x"06A",x"087",x"0BD",x"100",x"189",x"24E", -- 0x0178 + x"02A",x"02C",x"02E",x"030",x"033",x"037",x"03D",x"044", -- 0x0180 + x"04F",x"05E",x"075",x"092",x"0C7",x"10A",x"190",x"24E", -- 0x0188 + x"038",x"03A",x"03D",x"03E",x"041",x"044",x"04B",x"052", -- 0x0190 + x"05E",x"06C",x"083",x"09F",x"0D4",x"115",x"19B",x"24E", -- 0x0198 + x"052",x"053",x"056",x"057",x"05B",x"05E",x"064",x"06A", -- 0x01A0 + x"075",x"083",x"09A",x"0B6",x"0E9",x"12A",x"1AD",x"256", -- 0x01A8 + x"06F",x"071",x"073",x"075",x"078",x"07B",x"080",x"087", -- 0x01B0 + x"092",x"09F",x"0B6",x"0D1",x"104",x"143",x"1C2",x"265", -- 0x01B8 + x"0A7",x"0A9",x"0AB",x"0AD",x"0AF",x"0B2",x"0B7",x"0BD", -- 0x01C0 + x"0C7",x"0D4",x"0E9",x"104",x"135",x"174",x"1EE",x"27D", -- 0x01C8 + x"0ED",x"0EF",x"0F0",x"0F2",x"0F4",x"0F7",x"0FB",x"100", -- 0x01D0 + x"10A",x"115",x"12A",x"143",x"174",x"1B0",x"21E",x"2AC", -- 0x01D8 + x"17E",x"17F",x"180",x"181",x"181",x"183",x"185",x"189", -- 0x01E0 + x"190",x"19B",x"1AD",x"1C2",x"1EE",x"21E",x"285",x"30B", -- 0x01E8 + x"24E",x"24E",x"24E",x"24E",x"24E",x"24E",x"24E",x"24E", -- 0x01F0 + x"24E",x"24E",x"256",x"265",x"27D",x"2AC",x"30B",x"379", -- 0x01F8 + x"004",x"006",x"008",x"00A",x"00D",x"011",x"018",x"01F", -- 0x0200 + x"02B",x"039",x"053",x"070",x"0A8",x"0EE",x"17F",x"24F", -- 0x0208 + x"006",x"009",x"00B",x"00D",x"011",x"014",x"01A",x"021", -- 0x0210 + x"02E",x"03C",x"055",x"073",x"0AB",x"0F0",x"180",x"24F", -- 0x0218 + x"008",x"00B",x"00D",x"00F",x"012",x"016",x"01C",x"023", -- 0x0220 + x"02F",x"03E",x"057",x"074",x"0AC",x"0F2",x"181",x"24F", -- 0x0228 + x"00A",x"00D",x"00F",x"011",x"014",x"018",x"01E",x"025", -- 0x0230 + x"031",x"040",x"059",x"077",x"0AE",x"0F3",x"182",x"24F", -- 0x0238 + x"00D",x"011",x"012",x"014",x"018",x"01B",x"021",x"028", -- 0x0240 + x"035",x"043",x"05C",x"079",x"0B0",x"0F5",x"183",x"24F", -- 0x0248 + x"011",x"014",x"016",x"018",x"01B",x"01F",x"025",x"02C", -- 0x0250 + x"039",x"046",x"05F",x"07C",x"0B3",x"0F8",x"184",x"24F", -- 0x0258 + x"018",x"01A",x"01C",x"01E",x"021",x"025",x"02B",x"032", -- 0x0260 + x"03E",x"04C",x"065",x"082",x"0B8",x"0FD",x"186",x"24F", -- 0x0268 + x"01F",x"021",x"023",x"025",x"028",x"02C",x"032",x"039", -- 0x0270 + x"045",x"053",x"06C",x"088",x"0BE",x"101",x"18A",x"24F", -- 0x0278 + x"02B",x"02E",x"02F",x"031",x"035",x"039",x"03E",x"045", -- 0x0280 + x"051",x"05F",x"077",x"094",x"0C8",x"10B",x"191",x"24F", -- 0x0288 + x"039",x"03C",x"03E",x"040",x"043",x"046",x"04C",x"053", -- 0x0290 + x"05F",x"06D",x"085",x"0A0",x"0D5",x"116",x"19C",x"24F", -- 0x0298 + x"053",x"055",x"057",x"059",x"05C",x"05F",x"065",x"06C", -- 0x02A0 + x"077",x"085",x"09B",x"0B7",x"0EA",x"12B",x"1AE",x"256", -- 0x02A8 + x"070",x"073",x"074",x"077",x"079",x"07C",x"082",x"088", -- 0x02B0 + x"094",x"0A0",x"0B7",x"0D3",x"105",x"144",x"1C3",x"266", -- 0x02B8 + x"0A8",x"0AB",x"0AC",x"0AE",x"0B0",x"0B3",x"0B8",x"0BE", -- 0x02C0 + x"0C8",x"0D5",x"0EA",x"105",x"136",x"175",x"1EF",x"27E", -- 0x02C8 + x"0EE",x"0F0",x"0F2",x"0F3",x"0F5",x"0F8",x"0FC",x"101", -- 0x02D0 + x"10B",x"116",x"12B",x"144",x"175",x"1B1",x"21F",x"2AD", -- 0x02D8 + x"17F",x"180",x"181",x"182",x"183",x"184",x"186",x"18A", -- 0x02E0 + x"191",x"19C",x"1AE",x"1C3",x"1EF",x"21F",x"285",x"30B", -- 0x02E8 + x"24E",x"24E",x"24E",x"24E",x"24E",x"24E",x"24E",x"24E", -- 0x02F0 + x"24E",x"24E",x"256",x"266",x"27E",x"2AD",x"30B",x"37A", -- 0x02F8 + x"006",x"009",x"00A",x"00D",x"010",x"014",x"01A",x"021", -- 0x0300 + x"02D",x"03B",x"055",x"072",x"0AA",x"0F0",x"181",x"250", -- 0x0308 + x"009",x"00B",x"00D",x"00F",x"013",x"016",x"01C",x"023", -- 0x0310 + x"030",x"03E",x"057",x"075",x"0AD",x"0F2",x"182",x"250", -- 0x0318 + x"00A",x"00D",x"00F",x"011",x"014",x"018",x"01F",x"026", -- 0x0320 + x"031",x"040",x"059",x"076",x"0AE",x"0F3",x"183",x"250", -- 0x0328 + x"00D",x"00F",x"011",x"014",x"017",x"01A",x"020",x"027", -- 0x0330 + x"034",x"042",x"05B",x"079",x"0B0",x"0F5",x"183",x"250", -- 0x0338 + x"010",x"013",x"014",x"017",x"01A",x"01E",x"023",x"02A", -- 0x0340 + x"037",x"045",x"05E",x"07B",x"0B2",x"0F7",x"184",x"250", -- 0x0348 + x"014",x"016",x"018",x"01A",x"01E",x"021",x"027",x"02E", -- 0x0350 + x"03B",x"048",x"061",x"07E",x"0B5",x"0FA",x"186",x"250", -- 0x0358 + x"01A",x"01C",x"01F",x"020",x"023",x"027",x"02D",x"034", -- 0x0360 + x"040",x"04E",x"067",x"084",x"0BA",x"0FE",x"188",x"250", -- 0x0368 + x"021",x"023",x"026",x"027",x"02A",x"02E",x"034",x"03B", -- 0x0370 + x"047",x"055",x"06E",x"08A",x"0C0",x"103",x"18C",x"250", -- 0x0378 + x"02D",x"030",x"031",x"034",x"037",x"03B",x"040",x"047", -- 0x0380 + x"053",x"061",x"079",x"096",x"0CA",x"10C",x"192",x"250", -- 0x0388 + x"03B",x"03E",x"040",x"042",x"045",x"048",x"04E",x"055", -- 0x0390 + x"061",x"06F",x"087",x"0A2",x"0D7",x"118",x"19E",x"250", -- 0x0398 + x"055",x"057",x"059",x"05B",x"05E",x"061",x"067",x"06E", -- 0x03A0 + x"079",x"087",x"09D",x"0B9",x"0EC",x"12C",x"1AF",x"258", -- 0x03A8 + x"072",x"075",x"076",x"079",x"07B",x"07E",x"084",x"08A", -- 0x03B0 + x"096",x"0A2",x"0B9",x"0D4",x"106",x"145",x"1C4",x"267", -- 0x03B8 + x"0AA",x"0AD",x"0AE",x"0B0",x"0B2",x"0B5",x"0BA",x"0C0", -- 0x03C0 + x"0CA",x"0D7",x"0EC",x"106",x"137",x"176",x"1F0",x"27F", -- 0x03C8 + x"0F0",x"0F2",x"0F3",x"0F5",x"0F7",x"0FA",x"0FE",x"103", -- 0x03D0 + x"10C",x"118",x"12C",x"145",x"176",x"1B2",x"220",x"2AE", -- 0x03D8 + x"181",x"182",x"183",x"183",x"184",x"186",x"188",x"18C", -- 0x03E0 + x"192",x"19E",x"1AF",x"1C4",x"1F0",x"220",x"286",x"30C", -- 0x03E8 + x"250",x"250",x"250",x"250",x"250",x"250",x"250",x"250", -- 0x03F0 + x"250",x"250",x"257",x"267",x"27F",x"2AE",x"30C",x"37A", -- 0x03F8 + x"009",x"00C",x"00D",x"010",x"013",x"017",x"01D",x"024", -- 0x0400 + x"030",x"03E",x"058",x"075",x"0AD",x"0F3",x"183",x"251", -- 0x0408 + x"00C",x"00E",x"010",x"012",x"016",x"019",x"01F",x"026", -- 0x0410 + x"033",x"041",x"05A",x"077",x"0AF",x"0F4",x"184",x"251", -- 0x0418 + x"00D",x"010",x"012",x"014",x"017",x"01B",x"022",x"029", -- 0x0420 + x"034",x"043",x"05C",x"079",x"0B1",x"0F6",x"185",x"251", -- 0x0428 + x"010",x"012",x"014",x"017",x"01A",x"01D",x"023",x"02A", -- 0x0430 + x"037",x"045",x"05E",x"07B",x"0B2",x"0F7",x"185",x"251", -- 0x0438 + x"013",x"016",x"017",x"01A",x"01D",x"021",x"026",x"02D", -- 0x0440 + x"03A",x"048",x"061",x"07E",x"0B4",x"0FA",x"186",x"251", -- 0x0448 + x"017",x"019",x"01B",x"01D",x"021",x"024",x"02A",x"031", -- 0x0450 + x"03E",x"04B",x"064",x"081",x"0B8",x"0FC",x"188",x"251", -- 0x0458 + x"01D",x"01F",x"022",x"023",x"026",x"02A",x"030",x"037", -- 0x0460 + x"043",x"051",x"06A",x"086",x"0BC",x"101",x"18A",x"251", -- 0x0468 + x"024",x"026",x"029",x"02A",x"02D",x"031",x"037",x"03E", -- 0x0470 + x"04A",x"058",x"070",x"08C",x"0C2",x"105",x"18E",x"251", -- 0x0478 + x"030",x"033",x"034",x"037",x"03A",x"03E",x"043",x"04A", -- 0x0480 + x"056",x"064",x"07B",x"098",x"0CD",x"10F",x"194",x"251", -- 0x0488 + x"03E",x"041",x"043",x"045",x"048",x"04B",x"051",x"058", -- 0x0490 + x"064",x"072",x"089",x"0A4",x"0D9",x"11A",x"1A0",x"251", -- 0x0498 + x"058",x"05A",x"05C",x"05E",x"061",x"064",x"06A",x"070", -- 0x04A0 + x"07B",x"089",x"0A0",x"0BB",x"0EE",x"12E",x"1B1",x"259", -- 0x04A8 + x"075",x"077",x"079",x"07B",x"07E",x"081",x"086",x"08C", -- 0x04B0 + x"098",x"0A4",x"0BB",x"0D6",x"109",x"147",x"1C6",x"269", -- 0x04B8 + x"0AD",x"0AF",x"0B1",x"0B2",x"0B4",x"0B8",x"0BC",x"0C2", -- 0x04C0 + x"0CD",x"0D9",x"0EE",x"109",x"139",x"178",x"1F2",x"280", -- 0x04C8 + x"0F3",x"0F4",x"0F6",x"0F7",x"0FA",x"0FC",x"101",x"105", -- 0x04D0 + x"10E",x"11A",x"12E",x"147",x"178",x"1B3",x"221",x"2AF", -- 0x04D8 + x"183",x"184",x"185",x"185",x"186",x"188",x"18A",x"18E", -- 0x04E0 + x"194",x"1A0",x"1B1",x"1C6",x"1F1",x"221",x"287",x"30D", -- 0x04E8 + x"251",x"251",x"251",x"251",x"251",x"251",x"251",x"251", -- 0x04F0 + x"251",x"251",x"259",x"269",x"280",x"2AF",x"30D",x"37B", -- 0x04F8 + x"00D",x"010",x"011",x"014",x"017",x"01B",x"021",x"028", -- 0x0500 + x"034",x"042",x"05C",x"078",x"0B0",x"0F6",x"186",x"254", -- 0x0508 + x"010",x"012",x"014",x"016",x"01A",x"01D",x"023",x"02A", -- 0x0510 + x"036",x"044",x"05D",x"07B",x"0B2",x"0F7",x"187",x"254", -- 0x0518 + x"011",x"014",x"016",x"018",x"01B",x"01F",x"025",x"02C", -- 0x0520 + x"038",x"047",x"05F",x"07C",x"0B4",x"0F9",x"187",x"254", -- 0x0528 + x"014",x"016",x"018",x"01B",x"01E",x"021",x"027",x"02E", -- 0x0530 + x"03A",x"048",x"061",x"07F",x"0B5",x"0FA",x"188",x"254", -- 0x0538 + x"017",x"01A",x"01B",x"01E",x"021",x"025",x"02A",x"031", -- 0x0540 + x"03D",x"04B",x"064",x"081",x"0B8",x"0FD",x"189",x"254", -- 0x0548 + x"01B",x"01D",x"01F",x"021",x"025",x"028",x"02E",x"035", -- 0x0550 + x"041",x"04E",x"067",x"084",x"0BB",x"0FF",x"18A",x"254", -- 0x0558 + x"021",x"023",x"025",x"027",x"02A",x"02E",x"034",x"03B", -- 0x0560 + x"047",x"055",x"06D",x"089",x"0BF",x"104",x"18D",x"254", -- 0x0568 + x"028",x"02A",x"02C",x"02E",x"031",x"035",x"03B",x"041", -- 0x0570 + x"04E",x"05B",x"074",x"090",x"0C6",x"108",x"191",x"254", -- 0x0578 + x"034",x"036",x"038",x"03A",x"03D",x"041",x"047",x"04E", -- 0x0580 + x"059",x"067",x"07E",x"09B",x"0D0",x"112",x"197",x"254", -- 0x0588 + x"042",x"044",x"047",x"048",x"04B",x"04E",x"055",x"05B", -- 0x0590 + x"067",x"075",x"08C",x"0A8",x"0DC",x"11D",x"1A2",x"254", -- 0x0598 + x"05C",x"05D",x"05F",x"061",x"064",x"067",x"06D",x"074", -- 0x05A0 + x"07E",x"08C",x"0A3",x"0BE",x"0F1",x"131",x"1B3",x"25B", -- 0x05A8 + x"078",x"07B",x"07C",x"07F",x"081",x"084",x"089",x"090", -- 0x05B0 + x"09B",x"0A8",x"0BE",x"0D9",x"10B",x"14A",x"1C8",x"26B", -- 0x05B8 + x"0B0",x"0B2",x"0B4",x"0B5",x"0B8",x"0BB",x"0BF",x"0C6", -- 0x05C0 + x"0D0",x"0DC",x"0F1",x"10B",x"13C",x"17A",x"1F4",x"282", -- 0x05C8 + x"0F6",x"0F7",x"0F9",x"0FA",x"0FD",x"0FF",x"103",x"108", -- 0x05D0 + x"111",x"11D",x"131",x"14A",x"17A",x"1B6",x"223",x"2B0", -- 0x05D8 + x"186",x"187",x"187",x"188",x"189",x"18A",x"18D",x"191", -- 0x05E0 + x"197",x"1A2",x"1B3",x"1C8",x"1F4",x"223",x"289",x"30E", -- 0x05E8 + x"253",x"253",x"253",x"253",x"253",x"253",x"253",x"253", -- 0x05F0 + x"253",x"253",x"25B",x"26B",x"282",x"2B0",x"30E",x"37C", -- 0x05F8 + x"014",x"016",x"018",x"01A",x"01D",x"021",x"027",x"02E", -- 0x0600 + x"03A",x"048",x"061",x"07E",x"0B5",x"0FA",x"18A",x"256", -- 0x0608 + x"016",x"018",x"01B",x"01C",x"020",x"023",x"029",x"030", -- 0x0610 + x"03C",x"04A",x"063",x"080",x"0B7",x"0FC",x"18B",x"256", -- 0x0618 + x"018",x"01B",x"01C",x"01E",x"021",x"025",x"02B",x"032", -- 0x0620 + x"03E",x"04C",x"065",x"081",x"0B9",x"0FD",x"18B",x"256", -- 0x0628 + x"01A",x"01C",x"01E",x"021",x"024",x"027",x"02D",x"034", -- 0x0630 + x"040",x"04E",x"066",x"084",x"0BA",x"0FF",x"18C",x"256", -- 0x0638 + x"01D",x"020",x"021",x"024",x"027",x"02B",x"030",x"037", -- 0x0640 + x"043",x"051",x"069",x"086",x"0BC",x"101",x"18D",x"256", -- 0x0648 + x"021",x"023",x"025",x"027",x"02B",x"02E",x"034",x"03B", -- 0x0650 + x"047",x"054",x"06D",x"089",x"0C0",x"104",x"18E",x"256", -- 0x0658 + x"027",x"029",x"02B",x"02D",x"030",x"034",x"03A",x"041", -- 0x0660 + x"04C",x"05A",x"073",x"08E",x"0C4",x"108",x"191",x"256", -- 0x0668 + x"02E",x"030",x"032",x"034",x"037",x"03B",x"041",x"047", -- 0x0670 + x"053",x"061",x"079",x"094",x"0CA",x"10D",x"194",x"256", -- 0x0678 + x"03A",x"03C",x"03E",x"040",x"043",x"047",x"04C",x"053", -- 0x0680 + x"05F",x"06C",x"083",x"0A0",x"0D4",x"116",x"19B",x"256", -- 0x0688 + x"048",x"04A",x"04C",x"04E",x"051",x"054",x"05A",x"061", -- 0x0690 + x"06C",x"07A",x"091",x"0AC",x"0E0",x"121",x"1A6",x"256", -- 0x0698 + x"061",x"063",x"065",x"066",x"069",x"06D",x"073",x"079", -- 0x06A0 + x"083",x"091",x"0A7",x"0C3",x"0F5",x"135",x"1B7",x"25E", -- 0x06A8 + x"07E",x"080",x"081",x"084",x"086",x"089",x"08E",x"094", -- 0x06B0 + x"0A0",x"0AC",x"0C3",x"0DE",x"10F",x"14E",x"1CB",x"26D", -- 0x06B8 + x"0B5",x"0B7",x"0B9",x"0BA",x"0BC",x"0C0",x"0C4",x"0CA", -- 0x06C0 + x"0D4",x"0E0",x"0F5",x"10F",x"13F",x"17E",x"1F6",x"284", -- 0x06C8 + x"0FA",x"0FC",x"0FD",x"0FF",x"101",x"103",x"108",x"10C", -- 0x06D0 + x"116",x"121",x"135",x"14E",x"17D",x"1B8",x"226",x"2B2", -- 0x06D8 + x"18A",x"18B",x"18B",x"18C",x"18D",x"18E",x"191",x"194", -- 0x06E0 + x"19B",x"1A6",x"1B7",x"1CB",x"1F6",x"226",x"28B",x"30F", -- 0x06E8 + x"256",x"256",x"256",x"256",x"256",x"256",x"256",x"256", -- 0x06F0 + x"256",x"256",x"25E",x"26D",x"284",x"2B2",x"30F",x"37D", -- 0x06F8 + x"01B",x"01D",x"01F",x"021",x"024",x"028",x"02E",x"034", -- 0x0700 + x"041",x"04E",x"067",x"084",x"0BB",x"100",x"18E",x"25A", -- 0x0708 + x"01D",x"01F",x"022",x"023",x"027",x"02A",x"030",x"037", -- 0x0710 + x"043",x"050",x"069",x"086",x"0BD",x"101",x"18F",x"25A", -- 0x0718 + x"01F",x"022",x"023",x"025",x"028",x"02C",x"032",x"039", -- 0x0720 + x"044",x"053",x"06B",x"087",x"0BE",x"103",x"190",x"25A", -- 0x0728 + x"021",x"023",x"025",x"028",x"02B",x"02E",x"034",x"03B", -- 0x0730 + x"047",x"054",x"06D",x"08A",x"0C0",x"104",x"191",x"25A", -- 0x0738 + x"024",x"027",x"028",x"02B",x"02E",x"031",x"037",x"03E", -- 0x0740 + x"04A",x"057",x"070",x"08C",x"0C2",x"107",x"191",x"25A", -- 0x0748 + x"028",x"02A",x"02C",x"02E",x"031",x"034",x"03B",x"041", -- 0x0750 + x"04D",x"05A",x"073",x"08F",x"0C5",x"109",x"193",x"25A", -- 0x0758 + x"02E",x"030",x"032",x"034",x"037",x"03B",x"041",x"047", -- 0x0760 + x"053",x"060",x"079",x"094",x"0CA",x"10D",x"195",x"25A", -- 0x0768 + x"034",x"037",x"039",x"03B",x"03E",x"041",x"047",x"04D", -- 0x0770 + x"059",x"067",x"07F",x"09A",x"0D0",x"112",x"199",x"25A", -- 0x0778 + x"041",x"043",x"044",x"047",x"04A",x"04D",x"053",x"059", -- 0x0780 + x"065",x"072",x"089",x"0A5",x"0D9",x"11B",x"19F",x"25A", -- 0x0788 + x"04E",x"050",x"053",x"054",x"057",x"05A",x"060",x"067", -- 0x0790 + x"072",x"080",x"097",x"0B2",x"0E6",x"126",x"1AA",x"25A", -- 0x0798 + x"067",x"069",x"06B",x"06D",x"070",x"073",x"079",x"07F", -- 0x07A0 + x"089",x"097",x"0AD",x"0C8",x"0FA",x"13A",x"1BB",x"262", -- 0x07A8 + x"084",x"086",x"087",x"08A",x"08C",x"08F",x"094",x"09A", -- 0x07B0 + x"0A5",x"0B2",x"0C8",x"0E3",x"114",x"152",x"1CF",x"271", -- 0x07B8 + x"0BB",x"0BD",x"0BE",x"0C0",x"0C2",x"0C5",x"0CA",x"0D0", -- 0x07C0 + x"0D9",x"0E6",x"0FA",x"114",x"144",x"182",x"1FA",x"287", -- 0x07C8 + x"0FF",x"101",x"102",x"104",x"106",x"108",x"10D",x"112", -- 0x07D0 + x"11B",x"126",x"13A",x"152",x"181",x"1BC",x"229",x"2B5", -- 0x07D8 + x"18E",x"18F",x"190",x"191",x"191",x"193",x"195",x"199", -- 0x07E0 + x"19F",x"1AA",x"1BB",x"1CF",x"1F9",x"229",x"28D",x"312", -- 0x07E8 + x"25A",x"25A",x"25A",x"25A",x"25A",x"25A",x"25A",x"25A", -- 0x07F0 + x"25A",x"25A",x"261",x"270",x"287",x"2B5",x"312",x"37F", -- 0x07F8 + x"027",x"02A",x"02B",x"02D",x"030",x"034",x"03A",x"041", -- 0x0800 + x"04C",x"05A",x"072",x"08E",x"0C5",x"109",x"197",x"261", -- 0x0808 + x"02A",x"02C",x"02E",x"030",x"033",x"036",x"03C",x"043", -- 0x0810 + x"04F",x"05C",x"074",x"090",x"0C7",x"10B",x"198",x"261", -- 0x0818 + x"02B",x"02E",x"030",x"032",x"035",x"038",x"03E",x"045", -- 0x0820 + x"050",x"05E",x"076",x"092",x"0C8",x"10C",x"198",x"261", -- 0x0828 + x"02D",x"030",x"032",x"034",x"037",x"03A",x"040",x"046", -- 0x0830 + x"052",x"060",x"078",x"094",x"0CA",x"10E",x"199",x"261", -- 0x0838 + x"030",x"033",x"035",x"037",x"03A",x"03E",x"043",x"049", -- 0x0840 + x"055",x"062",x"07B",x"096",x"0CC",x"110",x"19A",x"261", -- 0x0848 + x"034",x"036",x"038",x"03A",x"03E",x"041",x"046",x"04D", -- 0x0850 + x"059",x"065",x"07E",x"099",x"0CF",x"112",x"19B",x"261", -- 0x0858 + x"03A",x"03C",x"03E",x"040",x"043",x"046",x"04C",x"053", -- 0x0860 + x"05E",x"06B",x"083",x"09E",x"0D3",x"117",x"19E",x"261", -- 0x0868 + x"041",x"043",x"045",x"046",x"049",x"04D",x"053",x"059", -- 0x0870 + x"065",x"072",x"089",x"0A4",x"0D9",x"11B",x"1A1",x"261", -- 0x0878 + x"04C",x"04F",x"050",x"052",x"055",x"059",x"05E",x"065", -- 0x0880 + x"070",x"07D",x"094",x"0AF",x"0E3",x"124",x"1A7",x"261", -- 0x0888 + x"05A",x"05C",x"05E",x"060",x"062",x"065",x"06B",x"072", -- 0x0890 + x"07D",x"08A",x"0A1",x"0BB",x"0EF",x"12F",x"1B2",x"261", -- 0x0898 + x"072",x"074",x"076",x"078",x"07B",x"07E",x"083",x"089", -- 0x08A0 + x"094",x"0A1",x"0B6",x"0D1",x"103",x"142",x"1C2",x"268", -- 0x08A8 + x"08E",x"090",x"092",x"094",x"096",x"099",x"09E",x"0A4", -- 0x08B0 + x"0AF",x"0BB",x"0D1",x"0EB",x"11C",x"15A",x"1D6",x"277", -- 0x08B8 + x"0C5",x"0C7",x"0C8",x"0CA",x"0CC",x"0CF",x"0D3",x"0D9", -- 0x08C0 + x"0E3",x"0EF",x"103",x"11C",x"14B",x"189",x"200",x"28D", -- 0x08C8 + x"109",x"10A",x"10C",x"10D",x"110",x"112",x"116",x"11B", -- 0x08D0 + x"123",x"12F",x"142",x"15A",x"189",x"1C3",x"22F",x"2BA", -- 0x08D8 + x"197",x"198",x"198",x"199",x"19A",x"19B",x"19E",x"1A1", -- 0x08E0 + x"1A7",x"1B2",x"1C2",x"1D6",x"200",x"22F",x"292",x"315", -- 0x08E8 + x"260",x"260",x"260",x"260",x"260",x"260",x"260",x"260", -- 0x08F0 + x"260",x"260",x"268",x"276",x"28C",x"2BA",x"315",x"382", -- 0x08F8 + x"036",x"038",x"039",x"03B",x"03E",x"042",x"048",x"04E", -- 0x0900 + x"05A",x"067",x"07F",x"09A",x"0D0",x"114",x"1A1",x"268", -- 0x0908 + x"038",x"03A",x"03C",x"03E",x"041",x"044",x"04A",x"050", -- 0x0910 + x"05C",x"069",x"080",x"09C",x"0D2",x"116",x"1A1",x"268", -- 0x0918 + x"039",x"03C",x"03E",x"040",x"043",x"046",x"04C",x"052", -- 0x0920 + x"05D",x"06B",x"083",x"09E",x"0D4",x"117",x"1A2",x"268", -- 0x0928 + x"03B",x"03E",x"040",x"042",x"045",x"048",x"04D",x"054", -- 0x0930 + x"05F",x"06C",x"084",x"0A0",x"0D5",x"119",x"1A3",x"268", -- 0x0938 + x"03E",x"041",x"043",x"045",x"048",x"04B",x"050",x"057", -- 0x0940 + x"062",x"06F",x"087",x"0A2",x"0D7",x"11B",x"1A3",x"268", -- 0x0948 + x"042",x"044",x"046",x"048",x"04B",x"04E",x"054",x"05A", -- 0x0950 + x"066",x"072",x"08A",x"0A5",x"0DA",x"11D",x"1A5",x"268", -- 0x0958 + x"048",x"04A",x"04C",x"04D",x"050",x"054",x"05A",x"060", -- 0x0960 + x"06B",x"078",x"090",x"0AA",x"0DF",x"121",x"1A7",x"268", -- 0x0968 + x"04E",x"050",x"052",x"054",x"057",x"05A",x"060",x"066", -- 0x0970 + x"071",x"07E",x"095",x"0B0",x"0E4",x"126",x"1AB",x"268", -- 0x0978 + x"05A",x"05C",x"05D",x"05F",x"062",x"066",x"06B",x"071", -- 0x0980 + x"07C",x"089",x"09F",x"0BB",x"0EE",x"12E",x"1B0",x"268", -- 0x0988 + x"067",x"069",x"06B",x"06C",x"06F",x"072",x"078",x"07E", -- 0x0990 + x"089",x"096",x"0AC",x"0C6",x"0F9",x"139",x"1BB",x"268", -- 0x0998 + x"07F",x"080",x"083",x"084",x"087",x"08A",x"090",x"095", -- 0x09A0 + x"09F",x"0AC",x"0C1",x"0DC",x"10D",x"14C",x"1CB",x"26F", -- 0x09A8 + x"09A",x"09C",x"09E",x"0A0",x"0A2",x"0A5",x"0AA",x"0B0", -- 0x09B0 + x"0BB",x"0C6",x"0DC",x"0F6",x"126",x"163",x"1DE",x"27E", -- 0x09B8 + x"0D0",x"0D2",x"0D4",x"0D5",x"0D7",x"0DA",x"0DF",x"0E4", -- 0x09C0 + x"0EE",x"0F9",x"10D",x"126",x"154",x"192",x"207",x"293", -- 0x09C8 + x"114",x"115",x"117",x"118",x"11A",x"11C",x"121",x"125", -- 0x09D0 + x"12E",x"138",x"14C",x"163",x"191",x"1CA",x"235",x"2BF", -- 0x09D8 + x"1A1",x"1A1",x"1A2",x"1A3",x"1A3",x"1A5",x"1A7",x"1AB", -- 0x09E0 + x"1B0",x"1BB",x"1CB",x"1DE",x"207",x"235",x"298",x"31A", -- 0x09E8 + x"268",x"268",x"268",x"268",x"268",x"268",x"268",x"268", -- 0x09F0 + x"268",x"268",x"26F",x"27D",x"293",x"2BF",x"31A",x"386", -- 0x09F8 + x"050",x"052",x"053",x"055",x"058",x"05B",x"061",x"067", -- 0x0A00 + x"072",x"07E",x"096",x"0B0",x"0E5",x"128",x"1B1",x"275", -- 0x0A08 + x"052",x"054",x"056",x"057",x"05B",x"05D",x"063",x"069", -- 0x0A10 + x"074",x"080",x"097",x"0B2",x"0E7",x"129",x"1B2",x"275", -- 0x0A18 + x"053",x"056",x"057",x"059",x"05C",x"05F",x"065",x"06B", -- 0x0A20 + x"075",x"082",x"099",x"0B4",x"0E8",x"12B",x"1B3",x"275", -- 0x0A28 + x"055",x"057",x"059",x"05B",x"05E",x"061",x"066",x"06C", -- 0x0A30 + x"077",x"084",x"09B",x"0B6",x"0EA",x"12C",x"1B4",x"275", -- 0x0A38 + x"058",x"05B",x"05C",x"05E",x"061",x"064",x"069",x"06F", -- 0x0A40 + x"07A",x"086",x"09D",x"0B8",x"0EC",x"12E",x"1B4",x"275", -- 0x0A48 + x"05B",x"05D",x"05F",x"061",x"064",x"067",x"06C",x"073", -- 0x0A50 + x"07E",x"089",x"0A0",x"0BA",x"0EE",x"130",x"1B6",x"275", -- 0x0A58 + x"061",x"063",x"065",x"066",x"069",x"06C",x"072",x"078", -- 0x0A60 + x"082",x"08F",x"0A5",x"0BF",x"0F3",x"134",x"1B8",x"275", -- 0x0A68 + x"067",x"069",x"06B",x"06C",x"06F",x"073",x"078",x"07E", -- 0x0A70 + x"088",x"095",x"0AB",x"0C5",x"0F8",x"138",x"1BB",x"275", -- 0x0A78 + x"072",x"074",x"075",x"077",x"07A",x"07E",x"082",x"088", -- 0x0A80 + x"093",x"09F",x"0B5",x"0CF",x"101",x"141",x"1C0",x"275", -- 0x0A88 + x"07E",x"080",x"082",x"084",x"086",x"089",x"08F",x"095", -- 0x0A90 + x"09F",x"0AB",x"0C1",x"0DA",x"10C",x"14B",x"1CB",x"275", -- 0x0A98 + x"096",x"097",x"099",x"09B",x"09D",x"0A0",x"0A5",x"0AB", -- 0x0AA0 + x"0B5",x"0C1",x"0D5",x"0EF",x"11F",x"15D",x"1DA",x"27C", -- 0x0AA8 + x"0B0",x"0B2",x"0B4",x"0B6",x"0B8",x"0BA",x"0BF",x"0C5", -- 0x0AB0 + x"0CF",x"0DA",x"0EF",x"108",x"136",x"172",x"1EC",x"28A", -- 0x0AB8 + x"0E5",x"0E7",x"0E8",x"0EA",x"0EC",x"0EE",x"0F3",x"0F8", -- 0x0AC0 + x"101",x"10C",x"11E",x"136",x"164",x"1A0",x"213",x"29E", -- 0x0AC8 + x"127",x"128",x"12A",x"12B",x"12D",x"12F",x"133",x"137", -- 0x0AD0 + x"140",x"14A",x"15D",x"172",x"19F",x"1D7",x"240",x"2C8", -- 0x0AD8 + x"1B1",x"1B2",x"1B3",x"1B4",x"1B4",x"1B6",x"1B8",x"1BB", -- 0x0AE0 + x"1C0",x"1CB",x"1DA",x"1EC",x"212",x"240",x"2A1",x"320", -- 0x0AE8 + x"274",x"274",x"274",x"274",x"274",x"274",x"274",x"274", -- 0x0AF0 + x"274",x"274",x"27B",x"288",x"29D",x"2C8",x"320",x"38B", -- 0x0AF8 + x"06D",x"06F",x"070",x"072",x"075",x"078",x"07D",x"082", -- 0x0B00 + x"08C",x"097",x"0AE",x"0C6",x"0F9",x"13B",x"1C0",x"27D", -- 0x0B08 + x"06F",x"071",x"073",x"074",x"077",x"079",x"07E",x"084", -- 0x0B10 + x"08E",x"099",x"0AF",x"0C8",x"0FB",x"13C",x"1C1",x"27D", -- 0x0B18 + x"070",x"073",x"074",x"076",x"078",x"07B",x"080",x"086", -- 0x0B20 + x"08F",x"09B",x"0B1",x"0CA",x"0FD",x"13D",x"1C1",x"27D", -- 0x0B28 + x"072",x"074",x"076",x"078",x"07A",x"07D",x"082",x"087", -- 0x0B30 + x"091",x"09C",x"0B2",x"0CB",x"0FE",x"13F",x"1C2",x"27D", -- 0x0B38 + x"075",x"077",x"078",x"07A",x"07D",x"080",x"084",x"08A", -- 0x0B40 + x"094",x"09F",x"0B5",x"0CD",x"100",x"141",x"1C2",x"27D", -- 0x0B48 + x"078",x"079",x"07B",x"07D",x"080",x"082",x"087",x"08D", -- 0x0B50 + x"097",x"0A1",x"0B7",x"0D0",x"102",x"142",x"1C4",x"27D", -- 0x0B58 + x"07D",x"07E",x"080",x"082",x"084",x"087",x"08C",x"092", -- 0x0B60 + x"09B",x"0A6",x"0BC",x"0D4",x"106",x"146",x"1C6",x"27D", -- 0x0B68 + x"082",x"084",x"086",x"087",x"08A",x"08D",x"092",x"097", -- 0x0B70 + x"0A1",x"0AC",x"0C1",x"0D9",x"10B",x"14A",x"1C9",x"27D", -- 0x0B78 + x"08C",x"08E",x"08F",x"091",x"094",x"097",x"09B",x"0A1", -- 0x0B80 + x"0AA",x"0B5",x"0CA",x"0E3",x"113",x"151",x"1CE",x"27D", -- 0x0B88 + x"097",x"099",x"09B",x"09C",x"09F",x"0A1",x"0A6",x"0AC", -- 0x0B90 + x"0B5",x"0C1",x"0D5",x"0ED",x"11D",x"15B",x"1D7",x"27D", -- 0x0B98 + x"0AE",x"0AF",x"0B1",x"0B2",x"0B5",x"0B7",x"0BC",x"0C1", -- 0x0BA0 + x"0CA",x"0D5",x"0E7",x"100",x"12F",x"16B",x"1E5",x"283", -- 0x0BA8 + x"0C6",x"0C8",x"0CA",x"0CB",x"0CD",x"0D0",x"0D4",x"0D9", -- 0x0BB0 + x"0E3",x"0ED",x"100",x"118",x"145",x"17F",x"1F6",x"290", -- 0x0BB8 + x"0F9",x"0FB",x"0FD",x"0FE",x"100",x"102",x"106",x"10B", -- 0x0BC0 + x"113",x"11D",x"12E",x"145",x"170",x"1AB",x"21A",x"2A2", -- 0x0BC8 + x"139",x"13A",x"13C",x"13D",x"13F",x"141",x"144",x"148", -- 0x0BD0 + x"150",x"159",x"16B",x"17F",x"1A9",x"1DF",x"245",x"2CA", -- 0x0BD8 + x"1C0",x"1C1",x"1C1",x"1C2",x"1C2",x"1C4",x"1C6",x"1C9", -- 0x0BE0 + x"1CE",x"1D7",x"1E5",x"1F6",x"219",x"245",x"2A2",x"31E", -- 0x0BE8 + x"27B",x"27B",x"27B",x"27B",x"27B",x"27B",x"27B",x"27B", -- 0x0BF0 + x"27B",x"27B",x"282",x"28E",x"2A1",x"2CA",x"31E",x"386", -- 0x0BF8 + x"0A5",x"0A7",x"0A8",x"0A9",x"0AB",x"0AE",x"0B2",x"0B7", -- 0x0C00 + x"0C0",x"0C9",x"0DD",x"0F3",x"123",x"162",x"1E0",x"292", -- 0x0C08 + x"0A7",x"0A8",x"0AA",x"0AB",x"0AE",x"0B0",x"0B4",x"0B9", -- 0x0C10 + x"0C1",x"0CB",x"0DE",x"0F5",x"125",x"163",x"1E1",x"292", -- 0x0C18 + x"0A8",x"0AA",x"0AB",x"0AD",x"0AF",x"0B1",x"0B6",x"0BA", -- 0x0C20 + x"0C2",x"0CC",x"0E0",x"0F6",x"126",x"164",x"1E1",x"292", -- 0x0C28 + x"0A9",x"0AB",x"0AD",x"0AE",x"0B0",x"0B2",x"0B7",x"0BB", -- 0x0C30 + x"0C4",x"0CD",x"0E1",x"0F8",x"127",x"165",x"1E2",x"292", -- 0x0C38 + x"0AB",x"0AE",x"0AF",x"0B0",x"0B2",x"0B5",x"0B9",x"0BD", -- 0x0C40 + x"0C6",x"0CF",x"0E3",x"0F9",x"129",x"167",x"1E2",x"292", -- 0x0C48 + x"0AE",x"0B0",x"0B1",x"0B2",x"0B5",x"0B7",x"0BB",x"0C0", -- 0x0C50 + x"0C9",x"0D2",x"0E5",x"0FB",x"12B",x"168",x"1E3",x"292", -- 0x0C58 + x"0B2",x"0B4",x"0B6",x"0B7",x"0B9",x"0BB",x"0C0",x"0C4", -- 0x0C60 + x"0CC",x"0D6",x"0E9",x"0FF",x"12E",x"16C",x"1E5",x"292", -- 0x0C68 + x"0B7",x"0B9",x"0BA",x"0BB",x"0BD",x"0C0",x"0C4",x"0C9", -- 0x0C70 + x"0D1",x"0DB",x"0EE",x"103",x"132",x"16F",x"1E8",x"292", -- 0x0C78 + x"0C0",x"0C1",x"0C2",x"0C4",x"0C6",x"0C9",x"0CC",x"0D1", -- 0x0C80 + x"0D9",x"0E2",x"0F5",x"10B",x"139",x"175",x"1EC",x"292", -- 0x0C88 + x"0C9",x"0CB",x"0CC",x"0CD",x"0CF",x"0D2",x"0D6",x"0DB", -- 0x0C90 + x"0E2",x"0EC",x"0FF",x"114",x"142",x"17D",x"1F4",x"292", -- 0x0C98 + x"0DD",x"0DE",x"0E0",x"0E1",x"0E3",x"0E5",x"0E9",x"0EE", -- 0x0CA0 + x"0F5",x"0FF",x"10E",x"126",x"152",x"18B",x"1FF",x"298", -- 0x0CA8 + x"0F3",x"0F5",x"0F6",x"0F8",x"0F9",x"0FB",x"0FF",x"103", -- 0x0CB0 + x"10B",x"114",x"126",x"13B",x"164",x"19C",x"20E",x"2A2", -- 0x0CB8 + x"123",x"125",x"126",x"127",x"129",x"12B",x"12E",x"132", -- 0x0CC0 + x"139",x"142",x"150",x"164",x"18D",x"1C4",x"22E",x"2B2", -- 0x0CC8 + x"160",x"161",x"162",x"163",x"164",x"166",x"169",x"16C", -- 0x0CD0 + x"173",x"17A",x"18B",x"19C",x"1C2",x"1F4",x"256",x"2D5", -- 0x0CD8 + x"1E0",x"1E1",x"1E1",x"1E2",x"1E2",x"1E3",x"1E5",x"1E8", -- 0x0CE0 + x"1EC",x"1F4",x"1FF",x"20E",x"22B",x"256",x"2AD",x"324", -- 0x0CE8 + x"290",x"290",x"290",x"290",x"290",x"290",x"290",x"290", -- 0x0CF0 + x"290",x"290",x"295",x"2A0",x"2B0",x"2D5",x"324",x"388", -- 0x0CF8 + x"0EB",x"0ED",x"0EE",x"0EF",x"0F1",x"0F3",x"0F7",x"0FB", -- 0x0D00 + x"103",x"10B",x"11E",x"132",x"160",x"19D",x"217",x"2C2", -- 0x0D08 + x"0ED",x"0EE",x"0F0",x"0F1",x"0F3",x"0F5",x"0F8",x"0FD", -- 0x0D10 + x"104",x"10C",x"11F",x"134",x"162",x"19E",x"217",x"2C2", -- 0x0D18 + x"0EE",x"0F0",x"0F1",x"0F2",x"0F4",x"0F6",x"0FA",x"0FE", -- 0x0D20 + x"105",x"10E",x"120",x"135",x"163",x"19F",x"217",x"2C2", -- 0x0D28 + x"0EF",x"0F1",x"0F2",x"0F3",x"0F5",x"0F7",x"0FB",x"0FF", -- 0x0D30 + x"106",x"10F",x"121",x"136",x"164",x"1A0",x"218",x"2C2", -- 0x0D38 + x"0F1",x"0F3",x"0F4",x"0F5",x"0F7",x"0F9",x"0FD",x"101", -- 0x0D40 + x"108",x"111",x"123",x"137",x"165",x"1A1",x"218",x"2C2", -- 0x0D48 + x"0F3",x"0F5",x"0F6",x"0F7",x"0F9",x"0FB",x"0FF",x"103", -- 0x0D50 + x"10B",x"113",x"125",x"139",x"167",x"1A3",x"219",x"2C2", -- 0x0D58 + x"0F7",x"0F8",x"0FA",x"0FB",x"0FD",x"0FF",x"103",x"107", -- 0x0D60 + x"10E",x"116",x"128",x"13C",x"16A",x"1A6",x"21B",x"2C2", -- 0x0D68 + x"0FB",x"0FD",x"0FE",x"0FF",x"101",x"103",x"107",x"10B", -- 0x0D70 + x"112",x"11A",x"12C",x"140",x"16D",x"1A8",x"21D",x"2C2", -- 0x0D78 + x"103",x"104",x"105",x"106",x"108",x"10B",x"10E",x"112", -- 0x0D80 + x"119",x"121",x"133",x"147",x"173",x"1AE",x"221",x"2C2", -- 0x0D88 + x"10B",x"10C",x"10E",x"10F",x"111",x"113",x"116",x"11A", -- 0x0D90 + x"121",x"12A",x"13B",x"14F",x"17B",x"1B5",x"228",x"2C2", -- 0x0D98 + x"11E",x"11F",x"120",x"121",x"123",x"125",x"128",x"12C", -- 0x0DA0 + x"133",x"13B",x"149",x"15F",x"18B",x"1C1",x"232",x"2C6", -- 0x0DA8 + x"132",x"134",x"135",x"136",x"137",x"139",x"13C",x"140", -- 0x0DB0 + x"147",x"14F",x"15F",x"173",x"19A",x"1D0",x"23F",x"2D0", -- 0x0DB8 + x"160",x"162",x"163",x"164",x"165",x"167",x"16A",x"16D", -- 0x0DC0 + x"173",x"17B",x"187",x"19A",x"1C1",x"1F7",x"25C",x"2DE", -- 0x0DC8 + x"19A",x"19B",x"19C",x"19D",x"19E",x"1A0",x"1A2",x"1A5", -- 0x0DD0 + x"1AB",x"1B2",x"1C1",x"1D0",x"1F3",x"224",x"282",x"2FD", -- 0x0DD8 + x"217",x"217",x"217",x"218",x"218",x"219",x"21B",x"21D", -- 0x0DE0 + x"221",x"228",x"232",x"23F",x"259",x"282",x"2D5",x"348", -- 0x0DE8 + x"2BE",x"2BE",x"2BE",x"2BE",x"2BE",x"2BE",x"2BE",x"2BE", -- 0x0DF0 + x"2BE",x"2BE",x"2C3",x"2CC",x"2DA",x"2FD",x"348",x"3AA", -- 0x0DF8 + x"17D",x"17E",x"17E",x"17F",x"181",x"183",x"185",x"188", -- 0x0E00 + x"18E",x"194",x"1A4",x"1B5",x"1DF",x"218",x"288",x"325", -- 0x0E08 + x"17E",x"17F",x"180",x"180",x"182",x"184",x"186",x"189", -- 0x0E10 + x"18F",x"195",x"1A4",x"1B6",x"1E0",x"219",x"288",x"325", -- 0x0E18 + x"17E",x"180",x"180",x"182",x"183",x"185",x"187",x"18A", -- 0x0E20 + x"18F",x"196",x"1A5",x"1B6",x"1E0",x"219",x"289",x"325", -- 0x0E28 + x"17F",x"180",x"182",x"183",x"184",x"185",x"188",x"18B", -- 0x0E30 + x"190",x"197",x"1A6",x"1B7",x"1E1",x"21A",x"289",x"325", -- 0x0E38 + x"181",x"182",x"183",x"184",x"185",x"187",x"189",x"18C", -- 0x0E40 + x"192",x"198",x"1A7",x"1B8",x"1E2",x"21B",x"289",x"325", -- 0x0E48 + x"183",x"184",x"185",x"185",x"187",x"188",x"18B",x"18E", -- 0x0E50 + x"194",x"199",x"1A9",x"1BA",x"1E4",x"21C",x"28A",x"325", -- 0x0E58 + x"185",x"186",x"187",x"188",x"189",x"18B",x"18E",x"191", -- 0x0E60 + x"196",x"19C",x"1AB",x"1BC",x"1E6",x"21E",x"28B",x"325", -- 0x0E68 + x"188",x"189",x"18A",x"18B",x"18C",x"18E",x"191",x"194", -- 0x0E70 + x"199",x"19F",x"1AE",x"1BF",x"1E8",x"220",x"28D",x"325", -- 0x0E78 + x"18E",x"18F",x"18F",x"190",x"192",x"194",x"196",x"199", -- 0x0E80 + x"19E",x"1A4",x"1B3",x"1C4",x"1ED",x"224",x"290",x"325", -- 0x0E88 + x"194",x"195",x"196",x"197",x"198",x"199",x"19C",x"19F", -- 0x0E90 + x"1A4",x"1AA",x"1B9",x"1C9",x"1F2",x"229",x"295",x"325", -- 0x0E98 + x"1A4",x"1A4",x"1A5",x"1A6",x"1A7",x"1A9",x"1AB",x"1AE", -- 0x0EA0 + x"1B3",x"1B9",x"1C3",x"1D8",x"200",x"232",x"29C",x"328", -- 0x0EA8 + x"1B5",x"1B6",x"1B6",x"1B7",x"1B8",x"1BA",x"1BC",x"1BF", -- 0x0EB0 + x"1C4",x"1C9",x"1D8",x"1E8",x"20B",x"23D",x"2A5",x"32F", -- 0x0EB8 + x"1DF",x"1E0",x"1E0",x"1E1",x"1E2",x"1E4",x"1E6",x"1E8", -- 0x0EC0 + x"1ED",x"1F2",x"1FB",x"20B",x"22E",x"260",x"2BD",x"339", -- 0x0EC8 + x"214",x"214",x"215",x"216",x"217",x"218",x"21A",x"21C", -- 0x0ED0 + x"220",x"225",x"232",x"23D",x"25B",x"287",x"2DF",x"352", -- 0x0ED8 + x"288",x"288",x"289",x"289",x"289",x"28A",x"28B",x"28D", -- 0x0EE0 + x"290",x"295",x"29C",x"2A5",x"2B8",x"2DF",x"32B",x"396", -- 0x0EE8 + x"320",x"320",x"320",x"320",x"320",x"320",x"320",x"320", -- 0x0EF0 + x"320",x"320",x"324",x"32B",x"335",x"352",x"396",x"3F3", -- 0x0EF8 + x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F00 + x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F08 + x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F10 + x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F18 + x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F20 + x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F28 + x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F30 + x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F38 + x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F40 + x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F48 + x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F50 + x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F58 + x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F60 + x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F68 + x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F70 + x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F78 + x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F80 + x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F88 + x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D",x"24D", -- 0x0F90 + x"24D",x"24D",x"254",x"25C",x"27C",x"2AB",x"302",x"379", -- 0x0F98 + x"254",x"254",x"254",x"254",x"254",x"254",x"254",x"254", -- 0x0FA0 + x"254",x"254",x"254",x"264",x"284",x"2AB",x"302",x"379", -- 0x0FA8 + x"25C",x"25C",x"25C",x"25C",x"25C",x"25C",x"25C",x"25C", -- 0x0FB0 + x"25C",x"25C",x"264",x"26C",x"284",x"2AB",x"302",x"379", -- 0x0FB8 + x"27C",x"27C",x"27C",x"27C",x"27C",x"27C",x"27C",x"27C", -- 0x0FC0 + x"27C",x"27C",x"27C",x"284",x"29C",x"2C3",x"30A",x"379", -- 0x0FC8 + x"2A3",x"2A3",x"2A3",x"2A3",x"2A3",x"2A3",x"2A3",x"2A3", -- 0x0FD0 + x"2A3",x"2A3",x"2AB",x"2AB",x"2BB",x"2DB",x"322",x"381", -- 0x0FD8 + x"302",x"302",x"302",x"302",x"302",x"302",x"302",x"302", -- 0x0FE0 + x"302",x"302",x"302",x"302",x"302",x"322",x"359",x"3B0", -- 0x0FE8 + x"371",x"371",x"371",x"371",x"371",x"371",x"371",x"371", -- 0x0FF0 + x"371",x"371",x"371",x"371",x"371",x"381",x"3B0",x"3FF" -- 0x0FF8 + ); + +begin + + p_rom : process + begin + wait until rising_edge(CLK); + DATA <= ROM(to_integer(unsigned(ADDR)))(9 downto 0); + end process; +end RTL; diff --git a/ramcard.v b/ramcard.v new file mode 100644 index 0000000..7d93dcf --- /dev/null +++ b/ramcard.v @@ -0,0 +1,65 @@ +// taken from the Apple II project by Alex Freed +// and modified for own use + +module ramcard(mclk28,reset_in,addr,ram_addr, we, card_ram_we,card_ram_rd, bank1); + input mclk28; + input reset_in; + input [15:0] addr; + output [17:0] ram_addr; + input we; + output card_ram_we; + output card_ram_rd; + output bank1; + + reg bank1, read_en, write_en, pre_wr_en, bankB, sat_read_en, sat_write_en, sat_pre_wr_en, sat_en; + reg [2:0] bank16k; + reg [15:0] addr2; + wire Dxxx,DEF; + + always @(posedge mclk28) begin + addr2 <= addr; + if(reset_in) begin + bank1 <= 0; + read_en <= 0; + write_en <= 1; + pre_wr_en <= 0; + + bankB <= 0; + sat_read_en <= 0; + sat_write_en <= 0; + sat_pre_wr_en <= 0; + end + else + begin + if((addr[15:4] == 'hC08) & (addr2 != addr)) begin + // Looks like a Language Card in slot 0 + bank1 <= addr[3]; + pre_wr_en <= addr[0] & ~we; + write_en <= addr[0] & pre_wr_en & ~we; + read_en <= ~(addr[0] ^ addr[1]); + end + if((addr[15:4] == 'hC0D) & (addr2 != addr)) begin + // Looks like Saturn128 Card in slot 5 + if(addr[2] == 0) begin + // State selection + bankB <= addr[3]; + sat_pre_wr_en <= addr[0]; + sat_write_en <= addr[0] & sat_pre_wr_en; + sat_read_en <= ~(addr[0] ^ addr[1]); + end + else + begin + // 16K bank selection + bank16k <= {addr[3], addr[1], addr[0]}; + end + end + end + end + + assign Dxxx = (addr[15:12] == 4'b1101); + assign DEF = ((addr[15:14] == 2'b11) & (addr[13:12] != 2'b00)); + assign ram_addr = ((sat_write_en || sat_read_en) && DEF)?{1'b1, bank16k, addr[13], addr[12] & ~(bankB & Dxxx), addr[11:0]}:{2'b0,addr[15:13], addr[12] & ~(bank1 & Dxxx), addr[11:0]}; + assign card_ram_we = (write_en | sat_write_en); + assign card_ram_rd = (read_en | sat_read_en); + +endmodule diff --git a/roms.mif b/roms.mif new file mode 100644 index 0000000..285e83f --- /dev/null +++ b/roms.mif @@ -0,0 +1,524 @@ +-- http://srecord.sourceforge.net/ +-- +-- Generated automatically by srec_cat -o --mif +-- +DEPTH = 12288; +WIDTH = 8; +ADDRESS_RADIX = HEX; +DATA_RADIX = HEX; +CONTENT BEGIN +0000: 6F D8 65 D7 F8 DC 94 D9 B1 DB 30 F3 D8 DF E1 DB 8F F3 98 F3 E4 F1 DD F1; +0018: D4 F1 24 F2 31 F2 40 F2 D7 F3 E1 F3 E8 F6 FD F6 68 F7 6E F7 E6 F7 57 FC; +0030: 20 F7 26 F7 74 F7 6C F2 6E F2 72 F2 76 F2 7F F2 4E F2 6A D9 55 F2 85 F2; +0048: A5 F2 CA F2 17 F3 BB F3 9E F3 61 F2 45 DA 3D D9 11 D9 C8 D9 48 D8 F4 03; +0060: 20 D9 6A D9 DB D9 6D D8 EB D9 83 E7 C8 D8 AF D8 12 E3 7A E7 D4 DA 95 D8; +0078: A4 D6 69 D6 9F DB 48 D6 90 EB 23 EC AF EB 0A 00 DE E2 12 D4 CD DF FF E2; +0090: 8D EE AE EF 41 E9 09 EF EA EF F1 EF 3A F0 9E F0 64 E7 D6 E6 C5 E3 07 E7; +00A8: E5 E6 46 E6 5A E6 86 E6 91 E6 79 C0 E7 79 A9 E7 7B 81 E9 7B 68 EA 7D 96; +00C0: EE 50 54 DF 46 4E DF 7F CF EE 7F 97 DE 64 64 DF 45 4E C4 46 4F D2 4E 45; +00D8: 58 D4 44 41 54 C1 49 4E 50 55 D4 44 45 CC 44 49 CD 52 45 41 C4 47 D2 54; +00F0: 45 58 D4 50 52 A3 49 4E A3 43 41 4C CC 50 4C 4F D4 48 4C 49 CE 56 4C 49; +0108: CE 48 47 52 B2 48 47 D2 48 43 4F 4C 4F 52 BD 48 50 4C 4F D4 44 52 41 D7; +0120: 58 44 52 41 D7 48 54 41 C2 48 4F 4D C5 52 4F 54 BD 53 43 41 4C 45 BD 53; +0138: 48 4C 4F 41 C4 54 52 41 43 C5 4E 4F 54 52 41 43 C5 4E 4F 52 4D 41 CC 49; +0150: 4E 56 45 52 53 C5 46 4C 41 53 C8 43 4F 4C 4F 52 BD 50 4F D0 56 54 41 C2; +0168: 48 49 4D 45 4D BA 4C 4F 4D 45 4D BA 4F 4E 45 52 D2 52 45 53 55 4D C5 52; +0180: 45 43 41 4C CC 53 54 4F 52 C5 53 50 45 45 44 BD 4C 45 D4 47 4F 54 CF 52; +0198: 55 CE 49 C6 52 45 53 54 4F 52 C5 A6 47 4F 53 55 C2 52 45 54 55 52 CE 52; +01B0: 45 CD 53 54 4F D0 4F CE 57 41 49 D4 4C 4F 41 C4 53 41 56 C5 44 45 C6 50; +01C8: 4F 4B C5 50 52 49 4E D4 43 4F 4E D4 4C 49 53 D4 43 4C 45 41 D2 47 45 D4; +01E0: 4E 45 D7 54 41 42 A8 54 CF 46 CE 53 50 43 A8 54 48 45 CE 41 D4 4E 4F D4; +01F8: 53 54 45 D0 AB AD AA AF DE 41 4E C4 4F D2 BE BD BC 53 47 CE 49 4E D4 41; +0210: 42 D3 55 53 D2 46 52 C5 53 43 52 4E A8 50 44 CC 50 4F D3 53 51 D2 52 4E; +0228: C4 4C 4F C7 45 58 D0 43 4F D3 53 49 CE 54 41 CE 41 54 CE 50 45 45 CB 4C; +0240: 45 CE 53 54 52 A4 56 41 CC 41 53 C3 43 48 52 A4 4C 45 46 54 A4 52 49 47; +0258: 48 54 A4 4D 49 44 A4 00 4E 45 58 54 20 57 49 54 48 4F 55 54 20 46 4F D2; +0270: 53 59 4E 54 41 D8 52 45 54 55 52 4E 20 57 49 54 48 4F 55 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+-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: roms.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY roms IS + PORT + ( + address : IN STD_LOGIC_VECTOR (13 DOWNTO 0); + clock : IN STD_LOGIC := '1'; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END roms; + + +ARCHITECTURE SYN OF roms IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); + +BEGIN + q <= sub_wire0(7 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_a => "NONE", + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => "../roms.mif", + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 16384, + operation_mode => "ROM", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + widthad_a => 14, + width_a => 8, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => address, + clock0 => clock, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "../roms.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "14" +-- Retrieval info: PRIVATE: WidthData NUMERIC "8" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "../roms.hex" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +-- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL roms.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL roms.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL roms.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL roms.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL roms_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/spram.vhd b/spram.vhd new file mode 100644 index 0000000..3e306f8 --- /dev/null +++ b/spram.vhd @@ -0,0 +1,90 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY spram IS + GENERIC + ( + init_file : string := ""; + widthad_a : natural; + width_a : natural := 8; + outdata_reg_a : string := "UNREGISTERED" + ); + PORT + ( + address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); +END spram; + + +ARCHITECTURE SYN OF spram IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + + + + COMPONENT altsyncram + GENERIC ( + clock_enable_input_a : STRING; + clock_enable_output_a : STRING; + init_file : STRING; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + numwords_a : NATURAL; + operation_mode : STRING; + outdata_aclr_a : STRING; + outdata_reg_a : STRING; + power_up_uninitialized : STRING; + read_during_write_mode_port_a : STRING; + widthad_a : NATURAL; + width_a : NATURAL; + width_byteena_a : NATURAL + ); + PORT ( + wren_a : IN STD_LOGIC ; + clock0 : IN STD_LOGIC ; + address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); + q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); + data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + q <= sub_wire0(width_a-1 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => init_file, + intended_device_family => "Cyclone III", + lpm_hint => "ENABLE_RUNTIME_MOD=NO", + lpm_type => "altsyncram", + numwords_a => 49152, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => outdata_reg_a, + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => widthad_a, + width_a => width_a, + width_byteena_a => 1 + ) + PORT MAP ( + wren_a => wren, + clock0 => clock, + address_a => address, + data_a => data, + q_a => sub_wire0 + ); + + + +END SYN; diff --git a/sys/build_id.tcl b/sys/build_id.tcl new file mode 100644 index 0000000..7ef0665 --- /dev/null +++ b/sys/build_id.tcl @@ -0,0 +1,35 @@ +# ================================================================================ +# +# Build ID Verilog Module Script +# Jeff Wiencrot - 8/1/2011 +# +# Generates a Verilog module that contains a timestamp, +# from the current build. These values are available from the build_date, build_time, +# physical_address, and host_name output ports of the build_id module in the build_id.v +# Verilog source file. +# +# ================================================================================ + +proc generateBuildID_Verilog {} { + + # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) + set buildDate [ clock format [ clock seconds ] -format %y%m%d ] + set buildTime [ clock format [ clock seconds ] -format %H%M%S ] + + # Create a Verilog file for output + set outputFileName "build_id.v" + set outputFile [open $outputFileName "w"] + + # Output the Verilog source + puts $outputFile "`define BUILD_DATE \"$buildDate\"" + puts $outputFile "`define BUILD_TIME \"$buildTime\"" + close $outputFile + + # Send confirmation message to the Messages window + post_message "Generated build identification Verilog module: [pwd]/$outputFileName" + post_message "Date: $buildDate" + post_message "Time: $buildTime" +} + +# Comment out this line to prevent the process from automatically executing when the file is sourced: +generateBuildID_Verilog \ No newline at end of file diff --git a/sys/ddram.sv b/sys/ddram.sv new file mode 100644 index 0000000..21a1ed6 --- /dev/null +++ b/sys/ddram.sv @@ -0,0 +1,132 @@ +// +// ddram.v +// +// DE10-nano DDR3 memory interface +// +// Copyright (c) 2017 Sorgelig +// +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// ------------------------------------------ +// + +// 8-bit version + +module ddram +( + input reset, + input DDRAM_CLK, + + input DDRAM_BUSY, + output [7:0] DDRAM_BURSTCNT, + output [28:0] DDRAM_ADDR, + input [63:0] DDRAM_DOUT, + input DDRAM_DOUT_READY, + output DDRAM_RD, + output [63:0] DDRAM_DIN, + output [7:0] DDRAM_BE, + output DDRAM_WE, + + input [27:0] addr, // 256MB at the end of 1GB + output [7:0] dout, // data output to cpu + input [7:0] din, // data input from cpu + input we, // cpu requests write + input rd, // cpu requests read + output ready // dout is valid. Ready to accept new read/write. +); + +assign DDRAM_BURSTCNT = 1; +assign DDRAM_BE = (8'd1< +// Copyright (c) 2017 Sorgelig (port to DE10-nano) +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +/////////////////////////////////////////////////////////////////////// + +// +// Use buffer to access SD card. It's time-critical part. +// +// for synchronous projects default value for PS2DIV is fine for any frequency of system clock. +// clk_ps2 = CLK_SYS/(PS2DIV*2) +// + +// WIDE=1 for 16 bit file I/O +// VDNUM 1-4 +module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0) +( + input clk_sys, + inout [43:0] HPS_BUS, + + // parameter STRLEN and the actual length of conf_str have to match + input [(8*STRLEN)-1:0] conf_str, + + output reg [15:0] joystick_0, + output reg [15:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + + output [1:0] buttons, + output forced_scandoubler, + + output reg [31:0] status, + + // SD config + output reg [VD:0] img_mounted, // signaling that new image has been mounted + output reg img_readonly, // mounted as read only. valid only for active bit in img_mounted + output reg [63:0] img_size, // size of image in bytes. valid only for active bit in img_mounted + + // SD block level access + input [31:0] sd_lba, + input [VD:0] sd_rd, // only single sd_rd can be active at any given time + input [VD:0] sd_wr, // only single sd_wr can be active at any given time + output reg sd_ack, + + // do not use in new projects. + // CID and CSD are fake except CSD image size field. + input sd_conf, + output reg sd_ack_conf, + + // SD byte level access. Signals for 2-PORT altsyncram. + output reg [AW:0] sd_buff_addr, + output reg [DW:0] sd_buff_dout, + input [DW:0] sd_buff_din, + output reg sd_buff_wr, + + // ARM -> FPGA download + output reg ioctl_download = 0, // signal indicating an active download + output reg [7:0] ioctl_index, // menu index used to upload the file + output reg ioctl_wr, + output reg [24:0] ioctl_addr, // in WIDE mode address will be incremented by 2 + output reg [DW:0] ioctl_dout, + input ioctl_wait, + + // RTC MSM6242B layout + output reg [64:0] RTC, + + // Seconds since 1970-01-01 00:00:00 + output reg [32:0] TIMESTAMP, + + // ps2 keyboard emulation + output ps2_kbd_clk_out, + output ps2_kbd_data_out, + input ps2_kbd_clk_in, + input ps2_kbd_data_in, + + input [2:0] ps2_kbd_led_status, + input [2:0] ps2_kbd_led_use, + + output ps2_mouse_clk_out, + output ps2_mouse_data_out, + input ps2_mouse_clk_in, + input ps2_mouse_data_in, + + // ps2 alternative interface. + output reg [65:0] ps2_key = 0, // up to 8 bytes per key (pause) + output reg [24:0] ps2_mouse = 0 +); + +localparam DW = (WIDE) ? 15 : 7; +localparam AW = (WIDE) ? 7 : 8; +localparam VD = VDNUM-1; + +wire io_wait = ioctl_wait; +wire io_enable= |HPS_BUS[35:34]; +wire io_strobe= HPS_BUS[33]; +wire io_wide = (WIDE) ? 1'b1 : 1'b0; +wire [15:0] io_din = HPS_BUS[31:16]; +reg [15:0] io_dout; + +assign HPS_BUS[37] = io_wait; +assign HPS_BUS[36] = clk_sys; +assign HPS_BUS[32] = io_wide; +assign HPS_BUS[15:0] = io_dout; + +reg [7:0] cfg; +assign buttons = cfg[1:0]; +//cfg[2] - vga_scaler handled in sys_top +//cfg[3] - csync handled in sys_top +assign forced_scandoubler = cfg[4]; +//cfg[5] - ypbpr handled in sys_top + +// command byte read by the io controller +wire [15:0] sd_cmd = +{ + 2'b00, + (VDNUM>=4) ? sd_wr[3] : 1'b0, + (VDNUM>=3) ? sd_wr[2] : 1'b0, + (VDNUM>=2) ? sd_wr[1] : 1'b0, + + (VDNUM>=4) ? sd_rd[3] : 1'b0, + (VDNUM>=3) ? sd_rd[2] : 1'b0, + (VDNUM>=2) ? sd_rd[1] : 1'b0, + + 4'h5, sd_conf, 1'b1, + sd_wr[0], + sd_rd[0] +}; + +///////////////// calc video parameters ////////////////// + +wire clk_100 = HPS_BUS[43]; +wire clk_vid = HPS_BUS[42]; +wire ce_pix = HPS_BUS[41]; +wire de = HPS_BUS[40]; +wire hs = HPS_BUS[39]; +wire vs = HPS_BUS[38]; + +reg [31:0] vid_hcnt = 0; +reg [31:0] vid_vcnt = 0; +reg [7:0] vid_nres = 0; +integer hcnt; + +always @(posedge clk_vid) begin + integer vcnt; + reg old_vs= 0, old_de = 0; + reg calch = 0; + + if(ce_pix) begin + old_vs <= vs; + old_de <= de; + + if(~vs & ~old_de & de) vcnt <= vcnt + 1; + if(calch & de) hcnt <= hcnt + 1; + if(old_de & ~de) calch <= 0; + + if(old_vs & ~vs) begin + if(hcnt && vcnt) begin + if(vid_hcnt != hcnt || vid_vcnt != vcnt) vid_nres <= vid_nres + 1'd1; + vid_hcnt <= hcnt; + vid_vcnt <= vcnt; + end + vcnt <= 0; + hcnt <= 0; + calch <= 1; + end + end +end + +reg [31:0] vid_htime = 0; +reg [31:0] vid_vtime = 0; +reg [31:0] vid_pix = 0; + +always @(posedge clk_100) begin + integer vtime, htime, hcnt; + reg old_vs, old_hs, old_vs2, old_hs2, old_de, old_de2; + reg calch = 0; + + old_vs <= vs; + old_hs <= hs; + + old_vs2 <= old_vs; + old_hs2 <= old_hs; + + vtime <= vtime + 1'd1; + htime <= htime + 1'd1; + + if(~old_vs2 & old_vs) begin + vid_pix <= hcnt; + vid_vtime <= vtime; + vtime <= 0; + hcnt <= 0; + end + + if(old_vs2 & ~old_vs) calch <= 1; + + if(~old_hs2 & old_hs) begin + vid_htime <= htime; + htime <= 0; + end + + old_de <= de; + old_de2 <= old_de; + + if(calch & old_de) hcnt <= hcnt + 1; + if(old_de2 & ~old_de) calch <= 0; +end + +///////////////////////////////////////////////////////// + +always@(posedge clk_sys) begin + reg [15:0] cmd; + reg [9:0] byte_cnt; // counts bytes + reg [2:0] b_wr; + reg [2:0] stick_idx; + reg ps2skip = 0; + + sd_buff_wr <= b_wr[0]; + if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1; + b_wr <= (b_wr<<1); + + {kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0; + ps2_key[65] <= kbd_txempty; + + if(~io_enable) begin + if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24]; + if(cmd == 5 && !ps2skip) ps2_key[64] <= ~ps2_key[64]; + if(cmd == 'h22) RTC[64] <= ~RTC[64]; + if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32]; + cmd <= 0; + byte_cnt <= 0; + sd_ack <= 0; + sd_ack_conf <= 0; + io_dout <= 0; + ps2skip <= 0; + end else begin + if(io_strobe) begin + + io_dout <= 0; + if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1; + + if(byte_cnt == 0) begin + cmd <= io_din; + + case(io_din) + 'h19: sd_ack_conf <= 1; + 'h17, + 'h18: sd_ack <= 1; + endcase + + sd_buff_addr <= 0; + img_mounted <= 0; + if(io_din == 5) ps2_key[63:0] <= 0; + end else begin + + case(cmd) + // buttons and switches + 'h01: cfg <= io_din[7:0]; + 'h02: joystick_0 <= io_din; + 'h03: joystick_1 <= io_din; + + // store incoming ps2 mouse bytes + 'h04: begin + mouse_data <= io_din[7:0]; + mouse_we <= 1; + if(&io_din[15:8]) ps2skip <= 1; + if(~&io_din[15:8] & ~ps2skip) begin + case(byte_cnt) + 1: ps2_mouse[7:0] <= io_din[7:0]; + 2: ps2_mouse[15:8] <= io_din[7:0]; + 3: ps2_mouse[23:16] <= io_din[7:0]; + endcase + end + end + + // store incoming ps2 keyboard bytes + 'h05: begin + if(&io_din[15:8]) ps2skip <= 1; + if(~&io_din[15:8] & ~ps2skip) ps2_key[63:0] <= {ps2_key[55:0], io_din[7:0]}; + kbd_data <= io_din[7:0]; + kbd_we <= 1; + end + + // reading config string + 'h14: begin + // returning a byte from string + if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8]; + end + + // reading sd card status + 'h16: begin + case(byte_cnt) + 1: io_dout <= sd_cmd; + 2: io_dout <= sd_lba[15:0]; + 3: io_dout <= sd_lba[31:16]; + endcase + end + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 'h19, + // send sector IO -> FPGA + // flag that download begins + 'h17: begin + sd_buff_dout <= io_din[DW:0]; + b_wr <= 1; + end + + // reading sd card write data + 'h18: begin + if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; + io_dout <= sd_buff_din; + end + + // joystick analog + 'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= io_din[2:0]; + if(byte_cnt == 2) begin + if(stick_idx == 0) joystick_analog_0 <= io_din; + if(stick_idx == 1) joystick_analog_1 <= io_din; + end + end + + // notify image selection + 'h1c: begin + img_mounted <= io_din[VD:0] ? io_din[VD:0] : 1'b1; + img_readonly <= io_din[7]; + end + + // send image info + 'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din; + + // status, 32bit version + 'h1e: if(byte_cnt==1) status[15:0] <= io_din; + else if(byte_cnt==2) status[31:16] <= io_din; + + // reading keyboard LED status + 'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]}; + + // reading ps2 keyboard/mouse control + 'h21: begin + if(byte_cnt == 1) begin + io_dout <= kbd_data_host; + kbd_rd <= 1; + end + + if(byte_cnt == 2) begin + io_dout <= mouse_data_host; + mouse_rd <= 1; + end + end + //RTC + 'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din; + + //Video res. + 'h23: begin + case(byte_cnt) + 1: io_dout <= vid_nres; + 2: io_dout <= vid_hcnt[15:0]; + 3: io_dout <= vid_hcnt[31:16]; + 4: io_dout <= vid_vcnt[15:0]; + 5: io_dout <= vid_vcnt[31:16]; + 6: io_dout <= vid_htime[15:0]; + 7: io_dout <= vid_htime[31:16]; + 8: io_dout <= vid_vtime[15:0]; + 9: io_dout <= vid_vtime[31:16]; + 10: io_dout <= vid_pix[15:0]; + 11: io_dout <= vid_pix[31:16]; + endcase + end + + //RTC + 'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din; + endcase + end + end + end +end + + +/////////////////////////////// PS2 /////////////////////////////// +reg clk_ps2; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + clk_ps2 <= ~clk_ps2; + cnt <= 0; + end +end + +reg [7:0] kbd_data; +reg kbd_we; +wire [8:0] kbd_data_host; +reg kbd_rd; +wire kbd_txempty; + +ps2_device keyboard +( + .clk_sys(clk_sys), + + .wdata(kbd_data), + .we(kbd_we), + + .ps2_clk(clk_ps2), + .ps2_clk_out(ps2_kbd_clk_out), + .ps2_dat_out(ps2_kbd_data_out), + .tx_empty(kbd_txempty), + + .ps2_clk_in(ps2_kbd_clk_in || !PS2WE), + .ps2_dat_in(ps2_kbd_data_in || !PS2WE), + + .rdata(kbd_data_host), + .rd(kbd_rd) +); + +reg [7:0] mouse_data; +reg mouse_we; +wire [8:0] mouse_data_host; +reg mouse_rd; + +ps2_device mouse +( + .clk_sys(clk_sys), + + .wdata(mouse_data), + .we(mouse_we), + + .ps2_clk(clk_ps2), + .ps2_clk_out(ps2_mouse_clk_out), + .ps2_dat_out(ps2_mouse_data_out), + + .ps2_clk_in(ps2_mouse_clk_in || !PS2WE), + .ps2_dat_in(ps2_mouse_data_in || !PS2WE), + + .rdata(mouse_data_host), + .rd(mouse_rd) +); + + +/////////////////////////////// DOWNLOADING /////////////////////////////// + +localparam UIO_FILE_TX = 8'h53; +localparam UIO_FILE_TX_DAT = 8'h54; +localparam UIO_FILE_INDEX = 8'h55; + +always@(posedge clk_sys) begin + reg [15:0] cmd; + reg has_cmd; + reg [24:0] addr; + reg wr; + + ioctl_wr <= wr; + wr <= 0; + + if(~io_enable) has_cmd <= 0; + else begin + if(io_strobe) begin + + if(!has_cmd) begin + cmd <= io_din; + has_cmd <= 1; + end else begin + + case(cmd) + UIO_FILE_INDEX: + begin + ioctl_index <= io_din[7:0]; + end + + UIO_FILE_TX: + begin + if(io_din[7:0]) begin + addr <= 0; + ioctl_download <= 1; + end else begin + ioctl_addr <= addr; + ioctl_download <= 0; + end + end + + UIO_FILE_TX_DAT: + begin + ioctl_addr <= addr; + ioctl_dout <= io_din[DW:0]; + wr <= 1; + addr <= addr + (WIDE ? 2'd2 : 2'd1); + end + endcase + end + end + end +end + +endmodule + +////////////////////////////////////////////////////////////////////////////////// + + +module ps2_device #(parameter PS2_FIFO_BITS=5) +( + input clk_sys, + + input [7:0] wdata, + input we, + + input ps2_clk, + output reg ps2_clk_out, + output reg ps2_dat_out, + output reg tx_empty, + + input ps2_clk_in, + input ps2_dat_in, + + output [8:0] rdata, + input rd +); + + +(* ramstyle = "logic" *) reg [7:0] fifo[1<= 1)&&(tx_state < 9)) begin + ps2_dat_out <= tx_byte[0]; // data bits + tx_byte[6:0] <= tx_byte[7:1]; // shift down + if(tx_byte[0]) + parity <= !parity; + end + + // transmission of parity + if(tx_state == 9) ps2_dat_out <= parity; + + // transmission of stop bit + if(tx_state == 10) ps2_dat_out <= 1; // stop bit is 1 + + // advance state machine + if(tx_state < 11) tx_state <= tx_state + 1'd1; + else tx_state <= 0; + end + end + end + + if(~old_clk & ps2_clk) ps2_clk_out <= 1; + if(old_clk & ~ps2_clk) ps2_clk_out <= ((tx_state == 0) && (rx_state<2)); + +end + +endmodule diff --git a/sys/hq2x.sv b/sys/hq2x.sv new file mode 100644 index 0000000..02b8543 --- /dev/null +++ b/sys/hq2x.sv @@ -0,0 +1,416 @@ +// +// +// Copyright (c) 2012-2013 Ludvig Strigeus +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on + +`define BITS_TO_FIT(N) ( \ + N <= 2 ? 0 : \ + N <= 4 ? 1 : \ + N <= 8 ? 2 : \ + N <= 16 ? 3 : \ + N <= 32 ? 4 : \ + N <= 64 ? 5 : \ + N <= 128 ? 6 : \ + N <= 256 ? 7 : \ + N <= 512 ? 8 : \ + N <= 1024 ? 9 : \ + N <= 2048 ?10 : 11 ) + +module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) +( + input clk, + input ce_x4, + input [DWIDTH:0] inputpixel, + input mono, + input disable_hq2x, + input reset_frame, + input reset_line, + input [1:0] read_y, + input [AWIDTH+1:0] read_x, + output [DWIDTH:0] outpixel +); + + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +localparam DWIDTH = HALF_DEPTH ? 11 : 23; + +wire [5:0] hqTable[256] = '{ + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, + 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 +}; + +reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; +reg [23:0] A, B, D, F, G, H; +reg [7:0] pattern, nextpatt; +reg [1:0] i; +reg [7:0] y; + +wire curbuf = y[0]; +reg prevbuf = 0; +wire iobuf = !curbuf; + +wire diff0, diff1; +DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); +DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); + +wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; + +wire [23:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; +wire [23:0] blend_result; +Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); + +reg Curr2_addr1; +reg [AWIDTH:0] Curr2_addr2; +wire [23:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; +wire [DWIDTH:0] Curr2tmp; + +reg [AWIDTH:0] wrin_addr2; +reg [DWIDTH:0] wrpix; +reg wrin_en; + +function [23:0] h2rgb; + input [11:0] v; +begin + h2rgb = mono ? {v[7:0], v[7:0], v[7:0]} : {v[11:8],v[11:8],v[7:4],v[7:4],v[3:0],v[3:0]}; +end +endfunction + +function [11:0] rgb2h; + input [23:0] v; +begin + rgb2h = mono ? {4'b0000, v[23:20], v[19:16]} : {v[23:20], v[15:12], v[7:4]}; +end +endfunction + +hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in +( + .clk(clk), + + .rdaddr(Curr2_addr2), + .rdbuf(Curr2_addr1), + .q(Curr2tmp), + + .wraddr(wrin_addr2), + .wrbuf(iobuf), + .data(wrpix), + .wren(wrin_en) +); + +reg [1:0] wrout_addr1; +reg [AWIDTH+1:0] wrout_addr2; +reg wrout_en; +reg [DWIDTH:0] wrdata; + +hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out +( + .clk(clk), + + .rdaddr(read_x), + .rdbuf(read_y), + .q(outpixel), + + .wraddr(wrout_addr2), + .wrbuf(wrout_addr1), + .data(wrdata), + .wren(wrout_en) +); + +always @(posedge clk) begin + reg [AWIDTH:0] offs; + reg old_reset_line; + reg old_reset_frame; + + wrout_en <= 0; + wrin_en <= 0; + + if(ce_x4) begin + + pattern <= new_pattern; + + if(~&offs) begin + if (i == 0) begin + Curr2_addr1 <= prevbuf; + Curr2_addr2 <= offs; + end + if (i == 1) begin + Prev2 <= Curr2; + Curr2_addr1 <= curbuf; + Curr2_addr2 <= offs; + end + if (i == 2) begin + Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; + wrpix <= inputpixel; + wrin_addr2 <= offs; + wrin_en <= 1; + end + if (i == 3) begin + offs <= offs + 1'd1; + end + + if(HALF_DEPTH) wrdata <= rgb2h(blend_result); + else wrdata <= blend_result; + + wrout_addr1 <= {curbuf, i[1]}; + wrout_addr2 <= {offs, i[1]^i[0]}; + wrout_en <= 1; + end + + if(i==3) begin + nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; + {A, G} <= {Prev0, Next0}; + {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; + {Prev0, Prev1} <= {Prev1, Prev2}; + {Curr0, Curr1} <= {Curr1, Curr2}; + {Next0, Next1} <= {Next1, Next2}; + end else begin + nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; + {B, F, H, D} <= {F, H, D, B}; + end + + i <= i + 1'b1; + if(old_reset_line && ~reset_line) begin + old_reset_frame <= reset_frame; + offs <= 0; + i <= 0; + y <= y + 1'd1; + prevbuf <= curbuf; + if(old_reset_frame & ~reset_frame) begin + y <= 0; + prevbuf <= 0; + end + end + + old_reset_line <= reset_line; + end +end + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module hq2x_in #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH); + wire [DWIDTH:0] out[2]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); +endmodule + + +module hq2x_out #(parameter LENGTH, parameter DWIDTH) +( + input clk, + + input [AWIDTH:0] rdaddr, + input [1:0] rdbuf, + output[DWIDTH:0] q, + + input [AWIDTH:0] wraddr, + input [1:0] wrbuf, + input [DWIDTH:0] data, + input wren +); + + localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); + wire [DWIDTH:0] out[4]; + assign q = out[rdbuf]; + + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); + hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); +endmodule + + +module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) +( + input clock, + input [DWIDTH:0] data, + input [AWIDTH:0] rdaddress, + input [AWIDTH:0] wraddress, + input wren, + output logic [DWIDTH:0] q +); + +logic [DWIDTH:0] ram[0:NUMWORDS-1]; + +always_ff@(posedge clock) begin + if(wren) ram[wraddress] <= data; + q <= ram[rdaddress]; +end + +endmodule + +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +module DiffCheck +( + input [23:0] rgb1, + input [23:0] rgb2, + output result +); + + wire [7:0] r = rgb1[7:1] - rgb2[7:1]; + wire [7:0] g = rgb1[15:9] - rgb2[15:9]; + wire [7:0] b = rgb1[23:17] - rgb2[23:17]; + wire [8:0] t = $signed(r) + $signed(b); + wire [8:0] gx = {g[7], g}; + wire [9:0] y = $signed(t) + $signed(gx); + wire [8:0] u = $signed(r) - $signed(b); + wire [9:0] v = $signed({g, 1'b0}) - $signed(t); + + // if y is inside (-96..96) + wire y_inside = (y < 10'h60 || y >= 10'h3a0); + + // if u is inside (-16, 16) + wire u_inside = (u < 9'h10 || u >= 9'h1f0); + + // if v is inside (-24, 24) + wire v_inside = (v < 10'h18 || v >= 10'h3e8); + assign result = !(y_inside && u_inside && v_inside); +endmodule + +module InnerBlend +( + input [8:0] Op, + input [7:0] A, + input [7:0] B, + input [7:0] C, + output [7:0] O +); + + function [10:0] mul8x3; + input [7:0] op1; + input [2:0] op2; + begin + mul8x3 = 11'd0; + if(op2[0]) mul8x3 = mul8x3 + op1; + if(op2[1]) mul8x3 = mul8x3 + {op1, 1'b0}; + if(op2[2]) mul8x3 = mul8x3 + {op1, 2'b00}; + end + endfunction + + wire OpOnes = Op[4]; + wire [10:0] Amul = mul8x3(A, Op[7:5]); + wire [10:0] Bmul = mul8x3(B, {Op[3:2], 1'b0}); + wire [10:0] Cmul = mul8x3(C, {Op[1:0], 1'b0}); + wire [10:0] At = Amul; + wire [10:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; + wire [10:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; + wire [11:0] Res = {At, 1'b0} + Bt + Ct; + assign O = Op[8] ? A : Res[11:4]; +endmodule + +module Blend +( + input [5:0] rule, + input disable_hq2x, + input [23:0] E, + input [23:0] A, + input [23:0] B, + input [23:0] D, + input [23:0] F, + input [23:0] H, + output [23:0] Result +); + + reg [1:0] input_ctrl; + reg [8:0] op; + localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A + localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 + localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 + localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 + localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 + localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 + localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 + localparam AB = 2'b00; + localparam AD = 2'b01; + localparam DB = 2'b10; + localparam BD = 2'b11; + wire is_diff; + DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); + + always @* begin + case({!is_diff, rule[5:2]}) + 1,17: {op, input_ctrl} = {BLEND1, AB}; + 2,18: {op, input_ctrl} = {BLEND1, DB}; + 3,19: {op, input_ctrl} = {BLEND1, BD}; + 4,20: {op, input_ctrl} = {BLEND2, DB}; + 5,21: {op, input_ctrl} = {BLEND2, AB}; + 6,22: {op, input_ctrl} = {BLEND2, AD}; + + 8: {op, input_ctrl} = {BLEND0, 2'bxx}; + 9: {op, input_ctrl} = {BLEND0, 2'bxx}; + 10: {op, input_ctrl} = {BLEND0, 2'bxx}; + 11: {op, input_ctrl} = {BLEND1, AB}; + 12: {op, input_ctrl} = {BLEND1, AB}; + 13: {op, input_ctrl} = {BLEND1, AB}; + 14: {op, input_ctrl} = {BLEND1, DB}; + 15: {op, input_ctrl} = {BLEND1, BD}; + + 24: {op, input_ctrl} = {BLEND2, DB}; + 25: {op, input_ctrl} = {BLEND5, DB}; + 26: {op, input_ctrl} = {BLEND6, DB}; + 27: {op, input_ctrl} = {BLEND2, DB}; + 28: {op, input_ctrl} = {BLEND4, DB}; + 29: {op, input_ctrl} = {BLEND5, DB}; + 30: {op, input_ctrl} = {BLEND3, BD}; + 31: {op, input_ctrl} = {BLEND3, DB}; + default: {op, input_ctrl} = {11{1'bx}}; + endcase + + // Setting op[8] effectively disables HQ2X because blend will always return E. + if (disable_hq2x) op[8] = 1; + end + + // Generate inputs to the inner blender. Valid combinations. + // 00: E A B + // 01: E A D + // 10: E D B + // 11: E B D + wire [23:0] Input1 = E; + wire [23:0] Input2 = !input_ctrl[1] ? A : + !input_ctrl[0] ? D : B; + + wire [23:0] Input3 = !input_ctrl[0] ? B : D; + InnerBlend inner_blend1(op, Input1[7:0], Input2[7:0], Input3[7:0], Result[7:0]); + InnerBlend inner_blend2(op, Input1[15:8], Input2[15:8], Input3[15:8], Result[15:8]); + InnerBlend inner_blend3(op, Input1[23:16], Input2[23:16], Input3[23:16], Result[23:16]); +endmodule diff --git a/sys/i2c.v b/sys/i2c.v new file mode 100644 index 0000000..911330f --- /dev/null +++ b/sys/i2c.v @@ -0,0 +1,69 @@ + +module I2C_Controller +( + input CLK, + + input START, + input [23:0] I2C_DATA, + output reg END = 1, + output reg ACK = 0, + + //I2C bus + output I2C_SCL, + inout I2C_SDA +); + + +// Clock Setting +parameter CLK_Freq = 50_000_000; // 50 MHz +parameter I2C_Freq = 400_000; // 400 KHz + +reg I2C_CLOCK; +always@(negedge CLK) begin + integer mI2C_CLK_DIV = 0; + if(mI2C_CLK_DIV < (CLK_Freq/I2C_Freq)) begin + mI2C_CLK_DIV <= mI2C_CLK_DIV + 1; + end else begin + mI2C_CLK_DIV <= 0; + I2C_CLOCK <= ~I2C_CLOCK; + end +end + +assign I2C_SCL = SCLK | I2C_CLOCK; +assign I2C_SDA = SDO ? 1'bz : 1'b0; + +reg SCLK = 1, SDO = 1; + +always @(posedge CLK) begin + reg old_clk; + reg old_st; + + reg [5:0] SD_COUNTER = 'b111111; + reg [0:31] SD; + + old_clk <= I2C_CLOCK; + old_st <= START; + + if(~old_st && START) begin + SCLK <= 1; + SDO <= 1; + ACK <= 0; + END <= 0; + SD <= {2'b10, I2C_DATA[23:16], 1'b1, I2C_DATA[15:8], 1'b1, I2C_DATA[7:0], 4'b1011}; + SD_COUNTER <= 0; + end else begin + if(~old_clk && I2C_CLOCK && ~&SD_COUNTER) begin + SD_COUNTER <= SD_COUNTER + 6'd1; + case(SD_COUNTER) + 01: SCLK <= 0; + 10,19,28: ACK <= ACK | I2C_SDA; + 29: SCLK <= 1; + 32: END <= 1; + endcase + end + + if(old_clk && ~I2C_CLOCK && ~SD_COUNTER[5]) SDO <= SD[SD_COUNTER[4:0]]; + end +end + +endmodule diff --git a/sys/i2s.v b/sys/i2s.v new file mode 100644 index 0000000..4de12b5 --- /dev/null +++ b/sys/i2s.v @@ -0,0 +1,85 @@ + +module i2s +#( + parameter CLK_RATE = 50000000, + parameter AUDIO_DW = 16, + parameter AUDIO_RATE = 96000 +) +( + input reset, + input clk_sys, + input half_rate, + + output reg sclk, + output reg lrclk, + output reg sdata, + + input [AUDIO_DW-1:0] left_chan, + input [AUDIO_DW-1:0] right_chan +); + +localparam WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*AUDIO_DW*4); +localparam ERROR_BASE = 10000; +localparam [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*AUDIO_DW*4)) - (WHOLE_CYCLES * ERROR_BASE); + +always @(posedge clk_sys) begin + reg [31:0] count_q; + reg [31:0] error_q; + reg [7:0] bit_cnt; + + reg [AUDIO_DW-1:0] left; + reg [AUDIO_DW-1:0] right; + + reg msclk; + reg ce; + + if (reset) begin + count_q <= 0; + error_q <= 0; + ce <= 0; + bit_cnt <= 1; + lrclk <= 1; + sclk <= 1; + msclk <= 1; + end + else + begin + if(count_q == WHOLE_CYCLES-1) begin + if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin + error_q <= error_q + ERRORS_PER_BIT[31:0]; + count_q <= 0; + end else begin + error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE; + count_q <= count_q + 1; + end + end else if(count_q == WHOLE_CYCLES) begin + count_q <= 0; + end else begin + count_q <= count_q + 1; + end + + sclk <= msclk; + if(!count_q) begin + ce <= ~ce; + if(~half_rate || ce) begin + msclk <= ~msclk; + if(msclk) begin + if(bit_cnt >= AUDIO_DW) begin + bit_cnt <= 1; + lrclk <= ~lrclk; + if(lrclk) begin + left <= left_chan; + right <= right_chan; + end + end + else begin + bit_cnt <= bit_cnt + 1'd1; + end + sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt]; + end + end + end + end +end + +endmodule diff --git a/sys/ip/avalon_combiner.v b/sys/ip/avalon_combiner.v new file mode 100644 index 0000000..164906c --- /dev/null +++ b/sys/ip/avalon_combiner.v @@ -0,0 +1,60 @@ +// avalon_combiner.v + +`timescale 1 ps / 1 ps +module avalon_combiner +( + input wire clk, // clock.clk + input wire rst, // reset.reset + + output wire [6:0] mixer_address, // ctl_mixer.address + output wire [3:0] mixer_byteenable, // .byteenable + output wire mixer_write, // .write + output wire [31:0] mixer_writedata, // .writedata + input wire mixer_waitrequest, // .waitrequest + + output wire [6:0] scaler_address, // ctl_scaler.address + output wire [3:0] scaler_byteenable, // .byteenable + input wire scaler_waitrequest, // .waitrequest + output wire scaler_write, // .write + output wire [31:0] scaler_writedata, // .writedata + + output wire [7:0] video_address, // ctl_video.address + output wire [3:0] video_byteenable, // .byteenable + input wire video_waitrequest, // .waitrequest + output wire video_write, // .write + output wire [31:0] video_writedata, // .writedata + + output wire clock, // control.clock + output wire reset, // .reset + input wire [8:0] address, // .address + input wire write, // .write + input wire [31:0] writedata, // .writedata + output wire waitrequest // .waitrequest +); + +assign clock = clk; +assign reset = rst; + +assign mixer_address = address[6:0]; +assign scaler_address = address[6:0]; +assign video_address = address[7:0]; + +assign mixer_byteenable = 4'b1111; +assign scaler_byteenable = 4'b1111; +assign video_byteenable = 4'b1111; + +wire en_scaler = (address[8:7] == 0); +wire en_mixer = (address[8:7] == 1); +wire en_video = address[8]; + +assign mixer_write = en_mixer & write; +assign scaler_write = en_scaler & write; +assign video_write = en_video & write; + +assign mixer_writedata = writedata; +assign scaler_writedata = writedata; +assign video_writedata = writedata; + +assign waitrequest = (en_mixer & mixer_waitrequest) | (en_scaler & scaler_waitrequest) | (en_video & video_waitrequest); + +endmodule diff --git a/sys/ip/avalon_combiner_hw.tcl b/sys/ip/avalon_combiner_hw.tcl new file mode 100644 index 0000000..10e491f --- /dev/null +++ b/sys/ip/avalon_combiner_hw.tcl @@ -0,0 +1,204 @@ +# TCL File Generated by Component Editor 16.1 +# Sat Mar 25 22:55:53 CST 2017 +# DO NOT MODIFY + + +# +# avalon_combiner "avalon_combiner" v1.0 +# 2017.03.25.22:55:53 +# +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module avalon_combiner +# +set_module_property DESCRIPTION "" +set_module_property NAME avalon_combiner +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR sorgelig +set_module_property DISPLAY_NAME avalon_combiner +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL avalon_combiner +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true +add_fileset_file avalon_combiner.v VERILOG PATH avalon_combiner.v TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset +# +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +set_interface_property reset ENABLED true +set_interface_property reset EXPORT_OF "" +set_interface_property reset PORT_NAME_MAP "" +set_interface_property reset CMSIS_SVD_VARIABLES "" +set_interface_property reset SVD_ADDRESS_GROUP "" + +add_interface_port reset rst reset Input 1 + + +# +# connection point ctl_mixer +# +add_interface ctl_mixer avalon start +set_interface_property ctl_mixer addressUnits WORDS +set_interface_property ctl_mixer associatedClock clock +set_interface_property ctl_mixer associatedReset reset +set_interface_property ctl_mixer bitsPerSymbol 8 +set_interface_property ctl_mixer burstOnBurstBoundariesOnly false +set_interface_property ctl_mixer burstcountUnits WORDS +set_interface_property ctl_mixer doStreamReads false +set_interface_property ctl_mixer doStreamWrites false +set_interface_property ctl_mixer holdTime 0 +set_interface_property ctl_mixer linewrapBursts false +set_interface_property ctl_mixer maximumPendingReadTransactions 0 +set_interface_property ctl_mixer maximumPendingWriteTransactions 0 +set_interface_property ctl_mixer readLatency 0 +set_interface_property ctl_mixer readWaitTime 1 +set_interface_property ctl_mixer setupTime 0 +set_interface_property ctl_mixer timingUnits Cycles +set_interface_property ctl_mixer writeWaitTime 0 +set_interface_property ctl_mixer ENABLED true +set_interface_property ctl_mixer EXPORT_OF "" +set_interface_property ctl_mixer PORT_NAME_MAP "" +set_interface_property ctl_mixer CMSIS_SVD_VARIABLES "" +set_interface_property ctl_mixer SVD_ADDRESS_GROUP "" + +add_interface_port ctl_mixer mixer_address address Output 7 +add_interface_port ctl_mixer mixer_byteenable byteenable Output 4 +add_interface_port ctl_mixer mixer_write write Output 1 +add_interface_port ctl_mixer mixer_writedata writedata Output 32 +add_interface_port ctl_mixer mixer_waitrequest waitrequest Input 1 + + +# +# connection point ctl_scaler +# +add_interface ctl_scaler avalon start +set_interface_property ctl_scaler addressUnits WORDS +set_interface_property ctl_scaler associatedClock clock +set_interface_property ctl_scaler associatedReset reset +set_interface_property ctl_scaler bitsPerSymbol 8 +set_interface_property ctl_scaler burstOnBurstBoundariesOnly false +set_interface_property ctl_scaler burstcountUnits WORDS +set_interface_property ctl_scaler doStreamReads false +set_interface_property ctl_scaler doStreamWrites false +set_interface_property ctl_scaler holdTime 0 +set_interface_property ctl_scaler linewrapBursts false +set_interface_property ctl_scaler maximumPendingReadTransactions 0 +set_interface_property ctl_scaler maximumPendingWriteTransactions 0 +set_interface_property ctl_scaler readLatency 0 +set_interface_property ctl_scaler readWaitTime 1 +set_interface_property ctl_scaler setupTime 0 +set_interface_property ctl_scaler timingUnits Cycles +set_interface_property ctl_scaler writeWaitTime 0 +set_interface_property ctl_scaler ENABLED true +set_interface_property ctl_scaler EXPORT_OF "" +set_interface_property ctl_scaler PORT_NAME_MAP "" +set_interface_property ctl_scaler CMSIS_SVD_VARIABLES "" +set_interface_property ctl_scaler SVD_ADDRESS_GROUP "" + +add_interface_port ctl_scaler scaler_address address Output 7 +add_interface_port ctl_scaler scaler_byteenable byteenable Output 4 +add_interface_port ctl_scaler scaler_waitrequest waitrequest Input 1 +add_interface_port ctl_scaler scaler_write write Output 1 +add_interface_port ctl_scaler scaler_writedata writedata Output 32 + + +# +# connection point ctl_video +# +add_interface ctl_video avalon start +set_interface_property ctl_video addressUnits WORDS +set_interface_property ctl_video associatedClock clock +set_interface_property ctl_video associatedReset reset +set_interface_property ctl_video bitsPerSymbol 8 +set_interface_property ctl_video burstOnBurstBoundariesOnly false +set_interface_property ctl_video burstcountUnits WORDS +set_interface_property ctl_video doStreamReads false +set_interface_property ctl_video doStreamWrites false +set_interface_property ctl_video holdTime 0 +set_interface_property ctl_video linewrapBursts false +set_interface_property ctl_video maximumPendingReadTransactions 0 +set_interface_property ctl_video maximumPendingWriteTransactions 0 +set_interface_property ctl_video readLatency 0 +set_interface_property ctl_video readWaitTime 1 +set_interface_property ctl_video setupTime 0 +set_interface_property ctl_video timingUnits Cycles +set_interface_property ctl_video writeWaitTime 0 +set_interface_property ctl_video ENABLED true +set_interface_property ctl_video EXPORT_OF "" +set_interface_property ctl_video PORT_NAME_MAP "" +set_interface_property ctl_video CMSIS_SVD_VARIABLES "" +set_interface_property ctl_video SVD_ADDRESS_GROUP "" + +add_interface_port ctl_video video_address address Output 8 +add_interface_port ctl_video video_byteenable byteenable Output 4 +add_interface_port ctl_video video_waitrequest waitrequest Input 1 +add_interface_port ctl_video video_write write Output 1 +add_interface_port ctl_video video_writedata writedata Output 32 + + +# +# connection point control +# +add_interface control conduit end +set_interface_property control associatedClock clock +set_interface_property control associatedReset reset +set_interface_property control ENABLED true +set_interface_property control EXPORT_OF "" +set_interface_property control PORT_NAME_MAP "" +set_interface_property control CMSIS_SVD_VARIABLES "" +set_interface_property control SVD_ADDRESS_GROUP "" + +add_interface_port control address address Input 9 +add_interface_port control write write Input 1 +add_interface_port control writedata writedata Input 32 +add_interface_port control waitrequest waitrequest Output 1 +add_interface_port control clock clock Output 1 +add_interface_port control reset reset Output 1 + diff --git a/sys/ip/de10_hps_hw.tcl b/sys/ip/de10_hps_hw.tcl new file mode 100644 index 0000000..491400a --- /dev/null +++ b/sys/ip/de10_hps_hw.tcl @@ -0,0 +1,3706 @@ +# (C) 2001-2017 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License Subscription +# Agreement, Intel MegaCore Function License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Intel and sold by +# Intel or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +# This IP is modified standard Altera HPS IP. +# Direct DDR3 SDRAM access has been removed since it won't work together with HPS DDR3 SDRAM access. +# FPGA access the memory through MPFE (FPGA2SDRAM bridge). +# By removing direct DDR3 SDRAM access synthesis time has been reduced by 3 times! + + +package require -exact qsys 12.0 +package require -exact altera_terp 1.0 +package require quartus::advanced_wysiwyg + +set_module_property NAME altera_hps_lite +set_module_property VERSION 16.1 +set_module_property AUTHOR "Altera Corporation/Sorgelig" +set_module_property SUPPORTED_DEVICE_FAMILIES {CYCLONEV ARRIAV} + +set_module_property DISPLAY_NAME "DE10-nano Hard Processor System" +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE false +set_module_property HIDE_FROM_SOPC true +set_module_property HIDE_FROM_QUARTUS true + +add_documentation_link "HPS User Guide for Cyclone V" "http://www.altera.com/literature/hb/cyclone-v/cv_5v4.pdf" +add_documentation_link "HPS User Guide for Arria V" "http://www.altera.com/literature/hb/arria-v/av_5v4.pdf" + +set alt_mem_if_tcl_libs_dir "$env(QUARTUS_ROOTDIR)/../ip/altera/alt_mem_if/alt_mem_if_tcl_packages" +if {[lsearch -exact $auto_path $alt_mem_if_tcl_libs_dir] == -1} { + lappend auto_path $alt_mem_if_tcl_libs_dir +} + +package require alt_mem_if::gui::system_info + +source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/constants.tcl +source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/procedures.tcl +source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/pin_mux.tcl +source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/pin_mux_db.tcl +source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/locations.tcl +source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/util/ui.tcl +source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/clocks.tcl +source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/clock_manager.tcl + +proc add_storage_parameter {name { default_value {} } } { + add_parameter $name string $default_value "" + set_parameter_property $name derived true + set_parameter_property $name visible false +} + +proc add_reset_parameters {} { + set group_name "Resets" + add_display_item "FPGA Interfaces" $group_name "group" "" + + add_parameter S2FCLK_COLDRST_Enable boolean false "" + set_parameter_property S2FCLK_COLDRST_Enable display_name "Enable HPS-to-FPGA cold reset output" + set_parameter_property S2FCLK_COLDRST_Enable group $group_name + + add_parameter S2FCLK_PENDINGRST_Enable boolean false "" + set_parameter_property S2FCLK_PENDINGRST_Enable display_name "Enable HPS warm reset handshake signals" + set_parameter_property S2FCLK_PENDINGRST_Enable group $group_name + + add_parameter F2SCLK_DBGRST_Enable boolean false "" + set_parameter_property F2SCLK_DBGRST_Enable display_name "Enable FPGA-to-HPS debug reset request" + set_parameter_property F2SCLK_DBGRST_Enable group $group_name + + add_parameter F2SCLK_WARMRST_Enable boolean false "" + set_parameter_property F2SCLK_WARMRST_Enable display_name "Enable FPGA-to-HPS warm reset request" + set_parameter_property F2SCLK_WARMRST_Enable group $group_name + + add_parameter F2SCLK_COLDRST_Enable boolean false "" + set_parameter_property F2SCLK_COLDRST_Enable display_name "Enable FPGA-to-HPS cold reset request" + set_parameter_property F2SCLK_COLDRST_Enable group $group_name + +} + +proc list_h2f_interrupt_groups {} { + return { + "CAN" "CLOCKPERIPHERAL" "CTI" + "DMA" "EMAC" "FPGAMANAGER" + "GPIO" "I2CEMAC" "I2CPERIPHERAL" + "L4TIMER" "NAND" "OSCTIMER" + "QSPI" "SDMMC" "SPIMASTER" + "SPISLAVE" "UART" "USB" + "WATCHDOG" + } +} + +proc get_h2f_interrupt_descriptions {data_ref} { + upvar 1 $data_ref data + array set data { + "DMA" "Enable DMA interrupts" + "EMAC" "Enable EMAC interrupts (for EMAC0 and EMAC1)" + "USB" "Enable USB interrupts" + "CAN" "Enable CAN interrupts" + "SDMMC" "Enable SD/MMC interrupt" + "NAND" "Enable NAND interrupt" + "QSPI" "Enable Quad SPI interrupt" + "SPIMASTER" "Enable SPI master interrupts" + "SPISLAVE" "Enable SPI slave interrupts" + "I2CPERIPHERAL" "Enable I2C peripheral interrupts (for I2C0 and I2C1)" + "I2CEMAC" "Enable I2C-EMAC interrupts (for I2C2 and I2C3)" + "UART" "Enable UART interrupts" + "GPIO" "Enable GPIO interrupts" + "L4TIMER" "Enable L4 timer interrupts" + "OSCTIMER" "Enable OSC timer interrupts" + "WATCHDOG" "Enable watchdog interrupts" + "CLOCKPERIPHERAL" "Enable clock peripheral interrupts" + "FPGAMANAGER" "Enable FPGA manager interrupt" + "CTI" "Enable CTI interrupts" + } +} + +proc load_h2f_interrupt_table {functions_by_group_ref + width_by_function_ref + inverted_by_function_ref} { + upvar 1 $functions_by_group_ref functions_by_group + upvar 1 $width_by_function_ref width_by_function + upvar 1 $inverted_by_function_ref inverted_by_function + array set functions_by_group { + "DMA" {"dma" "dma_abort" } + "EMAC" {"emac0" "emac1" } + "USB" {"usb0" "usb1" } + "CAN" {"can0" "can1" } + "SDMMC" {"sdmmc" } + "NAND" {"nand" } + "QSPI" {"qspi" } + "SPIMASTER" {"spi0" "spi1" } + "SPISLAVE" {"spi2" "spi3" } + "I2CPERIPHERAL" {"i2c0" "i2c1" } + "I2CEMAC" {"i2c_emac0" "i2c_emac1" } + "UART" {"uart0" "uart1" } + "GPIO" {"gpio0" "gpio1" "gpio2"} + "L4TIMER" {"l4sp0" "l4sp1" } + "OSCTIMER" {"osc0" "osc1" } + "WATCHDOG" {"wdog0" "wdog1" } + "CLOCKPERIPHERAL" {"clkmgr" "mpuwakeup" } + "FPGAMANAGER" {"fpga_man" } + "CTI" {"cti" } + } + array set width_by_function { + "dma" 8 + "cti" 2 + } + array set inverted_by_function { + "cti" 1 + } +} + +proc add_interrupt_parameters {} { + set top_group_name "Interrupts" + add_display_item "FPGA Interfaces" $top_group_name "group" "" + + # add_display_item $group_name "f2h_interrupts_label" "text" "FPGA-to-HPS" + add_parameter F2SINTERRUPT_Enable boolean false + set_parameter_property F2SINTERRUPT_Enable enabled true + set_parameter_property F2SINTERRUPT_Enable display_name "Enable FPGA-to-HPS Interrupts" + set_parameter_property F2SINTERRUPT_Enable group $top_group_name + + set inner_group_name "HPS-to-FPGA" + add_display_item $top_group_name $inner_group_name "group" "" + get_h2f_interrupt_descriptions descriptions_by_group + set interrupt_groups [list_h2f_interrupt_groups] + foreach interrupt_group $interrupt_groups { + set parameter "S2FINTERRUPT_${interrupt_group}_Enable" + add_parameter $parameter boolean false + set_parameter_property $parameter enabled true + set_parameter_property $parameter display_name $descriptions_by_group($interrupt_group) + set_parameter_property $parameter group $inner_group_name + } +} + +proc add_dma_parameters {} { + set group_name "DMA Peripheral Request" + add_display_item "FPGA Interfaces" $group_name "group" "" + add_display_item $group_name "DMA Table" "group" "table" + + add_parameter DMA_PeriphId_DERIVED string_list {0 1 2 3 4 5 6 7} + set_parameter_property DMA_PeriphId_DERIVED display_name "Peripheral Request ID" + set_parameter_property DMA_PeriphId_DERIVED derived true + set_parameter_property DMA_PeriphId_DERIVED display_hint "FIXED_SIZE" + set_parameter_property DMA_PeriphId_DERIVED group "DMA Table" + + add_parameter DMA_Enable string_list {"No" "No" "No" "No" "No" "No" "No" "No"} + set_parameter_property DMA_Enable allowed_ranges {"Yes" "No"} + set_parameter_property DMA_Enable display_name "Enabled" + set_parameter_property DMA_Enable display_hint "FIXED_SIZE" + set_parameter_property DMA_Enable group "DMA Table" +} + +proc range_from_zero {end} { + set result [list] + for {set i 0} {$i <= $end} {incr i} { + lappend result $i + } + return $result +} + +proc create_generic_parameters {} { + + ::alt_mem_if::util::hwtcl_utils::_add_parameter SYS_INFO_DEVICE_FAMILY STRING "" + set_parameter_property SYS_INFO_DEVICE_FAMILY SYSTEM_INFO DEVICE_FAMILY + set_parameter_property SYS_INFO_DEVICE_FAMILY VISIBLE FALSE + + ::alt_mem_if::util::hwtcl_utils::_add_parameter DEVICE_FAMILY STRING "" + set_parameter_property DEVICE_FAMILY DERIVED true + set_parameter_property DEVICE_FAMILY VISIBLE FALSE + + return 1 +} + +create_generic_parameters + +add_display_item "" "FPGA Interfaces" "group" "tab" +add_display_item "" "Peripheral Pins" "group" "tab" +add_display_item "" "HPS Clocks" "group" "tab" +add_clock_tab "HPS Clocks" + +add_display_item "FPGA Interfaces" "General" "group" "" + +add_parameter MPU_EVENTS_Enable boolean true +set_parameter_property MPU_EVENTS_Enable display_name "Enable MPU standby and event signals" +set_parameter_property MPU_EVENTS_Enable description "Enables elaboration of the mpu_events interface." +set_parameter_property MPU_EVENTS_Enable group "General" + +add_parameter GP_Enable boolean false +set_parameter_property GP_Enable display_name "Enable general purpose signals" +set_parameter_property GP_Enable description "Enables elaboration of interface h2f_gp." +set_parameter_property GP_Enable group "General" + +add_parameter DEBUGAPB_Enable boolean false +set_parameter_property DEBUGAPB_Enable display_name "Enable Debug APB interface" +set_parameter_property DEBUGAPB_Enable description "Enables elaboration of Debug APB interfaces." +set_parameter_property DEBUGAPB_Enable group "General" + +add_parameter STM_Enable boolean false +set_parameter_property STM_Enable display_name "Enable System Trace Macrocell hardware events" +set_parameter_property STM_Enable description "Enables elaboration of interface stm_hwevents." +set_parameter_property STM_Enable group "General" + +add_parameter CTI_Enable boolean false +set_parameter_property CTI_Enable display_name "Enable FPGA Cross Trigger Interface" +set_parameter_property CTI_Enable description "Enables elaboration of interface cti_trigger, cti_clk_in." +set_parameter_property CTI_Enable group "General" + +add_parameter TPIUFPGA_Enable boolean false +set_parameter_property TPIUFPGA_Enable display_name "Enable FPGA Trace Port Interface Unit" +set_parameter_property TPIUFPGA_Enable description "Enables elaboration of TPIU FPGA interfaces." +set_parameter_property TPIUFPGA_Enable group "General" + +add_parameter TPIUFPGA_alt boolean false +set_parameter_property TPIUFPGA_alt display_name "Enable FPGA Trace Port Alternate FPGA Interface" +set_parameter_property TPIUFPGA_alt description "When the trace port is enabled, it creates an interface compatible with the Arria 10 Trace Interface. (This just moves the clock_in port into the same conduit)" +set_parameter_property TPIUFPGA_alt group "General" +set_parameter_property TPIUFPGA_alt enabled false + + +add_parameter BOOTFROMFPGA_Enable boolean false +set_parameter_property BOOTFROMFPGA_Enable enabled true +set_parameter_property BOOTFROMFPGA_Enable display_name "Enable boot from fpga signals" +set_parameter_property BOOTFROMFPGA_Enable description "Enables elaboration of interface boot_from_fpga." +set_parameter_property BOOTFROMFPGA_Enable group "General" + +add_parameter TEST_Enable boolean false +set_parameter_property TEST_Enable enabled true +set_parameter_property TEST_Enable display_name "Enable Test Interface" +set_parameter_property TEST_Enable group "General" + +add_parameter HLGPI_Enable boolean false +set_parameter_property HLGPI_Enable enabled true +set_parameter_property HLGPI_Enable display_name "Enable HLGPI Interface" +set_parameter_property HLGPI_Enable group "General" + +add_display_item "FPGA Interfaces" "Boot and Clock Selection" "group" "" +add_parameter BSEL_EN boolean false +set_parameter_property BSEL_EN enabled true +set_parameter_property BSEL_EN display_name "Enable boot selection from FPGA" +set_parameter_property BSEL_EN group "Boot and Clock Selection" +set_parameter_property BSEL_EN visible false +set_parameter_property BSEL_EN enabled false + +add_parameter BSEL integer 1 +set_parameter_property BSEL allowed_ranges {"1:FPGA" "2:NAND Flash (1.8v)" "3:NAND Flash (3.0v)" "4:SD/MMC External Transceiver (1.8v)" "5:SD/MMC Internal Transceiver (3.0v)" "6:Quad SPI Flash (1.8v)" "7:Quad SPI Flash (3.0v)"} +set_parameter_property BSEL display_name "Boot selection from FPGA" +set_parameter_property BSEL group "Boot and Clock Selection" +set_parameter_property BSEL visible false +set_parameter_property BSEL enabled false + +add_parameter CSEL_EN boolean false +set_parameter_property CSEL_EN enabled true +set_parameter_property CSEL_EN display_name "Enable clock selection from FPGA" +set_parameter_property CSEL_EN group "Boot and Clock Selection" +set_parameter_property CSEL_EN visible false +set_parameter_property CSEL_EN enabled false + +add_parameter CSEL integer 0 +set_parameter_property CSEL allowed_ranges {"0:CSEL_0" "1:CSEL_1" "2:CSEL_2" "3:CSEL_3"} +set_parameter_property CSEL display_name "Clock selection from FPGA" +set_parameter_property CSEL group "Boot and Clock Selection" +set_parameter_property CSEL visible false +set_parameter_property CSEL enabled false + +add_display_item "FPGA Interfaces" "AXI Bridges" "group" "" +add_parameter F2S_Width integer 2 +set_parameter_property F2S_Width allowed_ranges {"0:Unused" "1:32-bit" "2:64-bit" "3:128-bit"} +set_parameter_property F2S_Width display_name "FPGA-to-HPS interface width" +set_parameter_property F2S_Width hdl_parameter true +set_parameter_property F2S_Width group "AXI Bridges" + +add_parameter S2F_Width integer 2 +set_parameter_property S2F_Width allowed_ranges {"0:Unused" "1:32-bit" "2:64-bit" "3:128-bit"} +set_parameter_property S2F_Width display_name "HPS-to-FPGA interface width" +set_parameter_property S2F_Width hdl_parameter true +set_parameter_property S2F_Width group "AXI Bridges" + +add_parameter LWH2F_Enable string true +set_parameter_property LWH2F_Enable display_name "Lightweight HPS-to-FPGA interface width" +set_parameter_property LWH2F_Enable description "The lightweight HPS-to-FPGA bridge provides a secondary, fixed-width, smaller address space, lower-performance master interface to the FPGA fabric. Use the lightweight HPS-to-FPGA bridge for high-latency, low-bandwidth traffic, such as memory-mapped register accesses of FPGA peripherals. This approach diverts traffic from the high-performance HPS-to-FPGA bridge, which can improve overall performance." +set_parameter_property LWH2F_Enable allowed_ranges {"true:32-bit" "false:Unused"} +set_parameter_property LWH2F_Enable group "AXI Bridges" + + +set group_name "FPGA-to-HPS SDRAM Interface" +add_display_item "FPGA Interfaces" $group_name "group" "" +add_display_item $group_name "f2sdram_label" "text" "Click the '+' and '-' buttons to add and remove FPGA-to-HPS SDRAM ports." +set table_name "F2SDRAM Settings" +add_display_item $group_name $table_name "group" "table" + +add_parameter F2SDRAM_Name_DERIVED string_list {"f2h_sdram0"} +set_parameter_property F2SDRAM_Name_DERIVED derived true +set_parameter_property F2SDRAM_Name_DERIVED display_name "Name" +set_parameter_property F2SDRAM_Name_DERIVED group $table_name + +add_parameter F2SDRAM_Type string_list [list [F2HSDRAM_AXI3]] +set_parameter_property F2SDRAM_Type allowed_ranges [list [F2HSDRAM_AXI3] [F2HSDRAM_AVM] [F2HSDRAM_AVM_WRITEONLY] [F2HSDRAM_AVM_READONLY]] +set_parameter_property F2SDRAM_Type display_name "Type" +set_parameter_property F2SDRAM_Type group $table_name + +add_parameter F2SDRAM_Width integer_list {"64"} +set_parameter_property F2SDRAM_Width allowed_ranges "32,64,128,256" +set_parameter_property F2SDRAM_Width display_name "Width" +set_parameter_property F2SDRAM_Width group $table_name +set_parameter_update_callback F2SDRAM_Width on_altered_f2sdram_width +# TODO: f2sdram derived parameters for resource counts in the table +# TODO: f2sdram derived parameters for remaining resources, not a part of the table + +add_storage_parameter F2SDRAM_Width_Last_Size 1 +add_storage_parameter F2SDRAM_CMD_PORT_USED 0 +add_storage_parameter F2SDRAM_WR_PORT_USED 0 +add_storage_parameter F2SDRAM_RD_PORT_USED 0 +add_storage_parameter F2SDRAM_RST_PORT_USED 0 +set_parameter_property F2SDRAM_Width_Last_Size group $group_name +set_parameter_property F2SDRAM_CMD_PORT_USED group $group_name +set_parameter_property F2SDRAM_WR_PORT_USED group $group_name +set_parameter_property F2SDRAM_RD_PORT_USED group $group_name +set_parameter_property F2SDRAM_RST_PORT_USED group $group_name + +#Parameter to export Bonding_out signal from fpga2sdram Atom +add_parameter BONDING_OUT_ENABLED boolean false +set_parameter_property BONDING_OUT_ENABLED display_name "Enable BONDING-OUT signals" +set_parameter_property BONDING_OUT_ENABLED group $group_name +set_parameter_property BONDING_OUT_ENABLED enabled false +set_parameter_property BONDING_OUT_ENABLED visible false + + +proc on_altered_f2sdram_width { param } { + set old_size [get_parameter_value F2SDRAM_Width_Last_Size] + set current_value [get_parameter_value F2SDRAM_Width] + set current_size [llength $current_value] + + if {$current_size == $old_size + 1} { ;# look for case of newly added row + set last_element_index [expr {$current_size - 1}] + set new_value [lreplace $current_value $last_element_index $last_element_index "64"] + set_parameter_value F2SDRAM_Width $new_value + } +} + +add_reset_parameters + +add_dma_parameters + +add_interrupt_parameters + + set group_name "EMAC ptp interface" + add_display_item "FPGA Interfaces" $group_name "group" "" + + add_parameter EMAC0_PTP boolean false + set_parameter_property EMAC0_PTP display_name "Enable EMAC0 Precision Time Protocol (PTP) FPGA Interface" + set_parameter_property EMAC0_PTP hdl_parameter false + set_parameter_property EMAC0_PTP enabled false + set_parameter_property EMAC0_PTP group $group_name + set_parameter_property EMAC0_PTP description "When the EMAC is connected to the HPS IO via the Pinmux, the IEEE 1588 Precision Time Protocol (PTP) interface can be accessed through the FPGA. When the EMAC connects to the FPGA, the PTP signals are always available." + + add_parameter EMAC1_PTP boolean false + set_parameter_property EMAC1_PTP display_name "Enable EMAC1 Precision Time Protocol (PTP) FPGA Interface" + set_parameter_property EMAC1_PTP hdl_parameter false + set_parameter_property EMAC1_PTP enabled false + set_parameter_property EMAC1_PTP group $group_name + set_parameter_property EMAC1_PTP description "When the EMAC is connected to the HPS IO via the Pinmux, the IEEE 1588 Precision Time Protocol (PTP) interface can be accessed through the FPGA. When the EMAC connects to the FPGA, the PTP signals are always available." + + +proc make_mode_display_name {peripheral} { + set default_suffix "mode" + array set custom_suffix_by_peripheral { + USB0 "PHY interface mode" + USB1 "PHY interface mode" + } + if {[info exists custom_suffix_by_peripheral($peripheral)]} { + set suffix $custom_suffix_by_peripheral($peripheral) + } else { + set suffix $default_suffix + } + + set display_name "${peripheral} ${suffix}" + return $display_name +} + +proc add_peripheral_pin_muxing_parameters {} { + set TOP_LEVEL_GROUP_NAME "Peripheral Pins" + + + foreach group_name [list_group_names] { + add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" + + foreach peripheral_name [peripherals_in_group $group_name] { + set pin_muxing_param_name "${peripheral_name}_PinMuxing" + set mode_param_name "${peripheral_name}_Mode" + add_parameter $pin_muxing_param_name string [UNUSED_MUX_VALUE] + set_parameter_property $pin_muxing_param_name enabled false + set_parameter_property $pin_muxing_param_name display_name "${peripheral_name} pin" + set_parameter_property $pin_muxing_param_name allowed_ranges [UNUSED_MUX_VALUE] + set_parameter_property $pin_muxing_param_name group $group_name + set_parameter_update_callback $pin_muxing_param_name on_altered_peripheral_pin_muxing $peripheral_name + + set mode_display_name [make_mode_display_name $peripheral_name] + add_parameter $mode_param_name string [NA_MODE_VALUE] + set_parameter_property $mode_param_name enabled false + set_parameter_property $mode_param_name display_name $mode_display_name + set_parameter_property $mode_param_name allowed_ranges [NA_MODE_VALUE] + set_parameter_property $mode_param_name group $group_name + + if {[string match "*EMAC*" $peripheral_name]} { + set_parameter_update_callback $mode_param_name on_emac_mode_switch_internal $peripheral_name + } + } + } +} +add_peripheral_pin_muxing_parameters + +proc add_gpio_parameters {} { + set TOP_LEVEL_GROUP_NAME "Peripheral Pins" + set group_name "Peripherals Mux Table" + set table_name "Conflict Table" + + add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" + #add_display_item $group_name $table_name "group" "table" + + add_parameter Customer_Pin_Name_DERIVED string_list {} + set_parameter_property Customer_Pin_Name_DERIVED display_name "Pin Name" + set_parameter_property Customer_Pin_Name_DERIVED derived true + set_parameter_property Customer_Pin_Name_DERIVED display_hint "FIXED_SIZE" + set_parameter_property Customer_Pin_Name_DERIVED visible false + # set_parameter_property Customer_Pin_Name_DERIVED group $table_name + + add_parameter GPIO_Conflict_DERIVED string_list {} + set_parameter_property GPIO_Conflict_DERIVED display_name "Used by" + set_parameter_property GPIO_Conflict_DERIVED derived true + set_parameter_property GPIO_Conflict_DERIVED display_hint "FIXED_SIZE" + set_parameter_property GPIO_Conflict_DERIVED visible false + #set_parameter_property GPIO_Conflict_DERIVED group $table_name + + add_parameter GPIO_Name_DERIVED string_list {} + set_parameter_property GPIO_Name_DERIVED display_name "GPIO" + set_parameter_property GPIO_Name_DERIVED derived true + set_parameter_property GPIO_Name_DERIVED display_hint "FIXED_SIZE" + set_parameter_property GPIO_Name_DERIVED visible false + #set_parameter_property GPIO_Name_DERIVED group $table_name + + # TODO: change? + set max_possible_gpio_options 100 + set enable_list [list] + for {set i 0} {$i < $max_possible_gpio_options} {incr i} { + lappend enable_list "No" + } + + add_parameter GPIO_Enable string_list $enable_list + set_parameter_property GPIO_Enable allowed_ranges {"Yes" "No"} + set_parameter_property GPIO_Enable display_name "GPIO Enabled" + set_parameter_property GPIO_Enable visible false + # set_parameter_property GPIO_Enable group $table_name + + add_parameter LOANIO_Name_DERIVED string_list {} + set_parameter_property LOANIO_Name_DERIVED display_name "Loan I/O" + set_parameter_property LOANIO_Name_DERIVED derived true + set_parameter_property LOANIO_Name_DERIVED display_hint "FIXED_SIZE" + set_parameter_property LOANIO_Name_DERIVED visible false + + add_parameter GPIO_Pin_Used_DERIVED boolean false + set_parameter_property GPIO_Pin_Used_DERIVED display_name "GPIO Pin Used" + set_parameter_property GPIO_Pin_Used_DERIVED derived true + set_parameter_property GPIO_Pin_Used_DERIVED display_hint "GPIO Pin Used" + set_parameter_property GPIO_Pin_Used_DERIVED visible false + + add_parameter LOANIO_Enable string_list $enable_list + set_parameter_property LOANIO_Enable allowed_ranges {"Yes" "No"} + set_parameter_property LOANIO_Enable display_name "Loan I/O Enabled" + set_parameter_property LOANIO_Enable visible false + #set_parameter_property LOANIO_Enable group $table_name + + + +} +add_gpio_parameters + +proc add_reset_parameters {} { + set group_name "Resets" + add_display_item "FPGA Interfaces" $group_name "group" "" + + add_parameter S2FCLK_COLDRST_Enable boolean false "" + set_parameter_property S2FCLK_COLDRST_Enable display_name "Enable HPS-to-FPGA cold reset output" + set_parameter_property S2FCLK_COLDRST_Enable group $group_name + + add_parameter S2FCLK_PENDINGRST_Enable boolean false "" + set_parameter_property S2FCLK_PENDINGRST_Enable display_name "Enable HPS warm reset handshake signals" + set_parameter_property S2FCLK_PENDINGRST_Enable group $group_name + + add_parameter F2SCLK_DBGRST_Enable boolean false "" + set_parameter_property F2SCLK_DBGRST_Enable display_name "Enable FPGA-to-HPS debug reset request" + set_parameter_property F2SCLK_DBGRST_Enable group $group_name + + add_parameter F2SCLK_WARMRST_Enable boolean false "" + set_parameter_property F2SCLK_WARMRST_Enable display_name "Enable FPGA-to-HPS warm reset request" + set_parameter_property F2SCLK_WARMRST_Enable group $group_name + + add_parameter F2SCLK_COLDRST_Enable boolean false "" + set_parameter_property F2SCLK_COLDRST_Enable display_name "Enable FPGA-to-HPS cold reset request" + set_parameter_property F2SCLK_COLDRST_Enable group $group_name + +} + +proc add_java_gui_parameters {} { + set TOP_LEVEL_GROUP_NAME "Peripheral Pins" + set group_name "Peripherals Mux Table" + + add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" + # add_display_item $group_name the_widget "group" "" + + add_parameter JAVA_CONFLICT_PIN string_list {} + set_parameter_property JAVA_CONFLICT_PIN derived true + set_parameter_property JAVA_CONFLICT_PIN visible false + + + add_parameter JAVA_GUI_PIN_LIST string_list {} + set_parameter_property JAVA_GUI_PIN_LIST derived true + set_parameter_property JAVA_GUI_PIN_LIST visible false + + set peripherals [list_peripheral_names] + set widget_parameter [list \ + Customer_Pin_Name_DERIVED Customer_Pin_Name_DERIVED \ + GPIO_Name_DERIVED GPIO_Name_DERIVED \ + LOANIO_Name_DERIVED LOANIO_Name_DERIVED \ + LOANIO_Enable LOANIO_Enable \ + GPIO_Enable GPIO_Enable \ + JAVA_CONFLICT_PIN GUI_Conflict_Pins_List \ + JAVA_GUI_PIN_LIST GUI_GPIO_Pins_List] + + foreach peripheral_name $peripherals { + add_parameter "JAVA_${peripheral_name}_DATA" string "" + set_parameter_property "JAVA_${peripheral_name}_DATA" derived true + set_parameter_property "JAVA_${peripheral_name}_DATA" visible false + + lappend widget_parameter "JAVA_${peripheral_name}_DATA" + lappend widget_parameter "${peripheral_name}_pin_muxing" + lappend widget_parameter "${peripheral_name}_PinMuxing" + lappend widget_parameter "${peripheral_name}_PinMuxing" + lappend widget_parameter "${peripheral_name}_Mode" + lappend widget_parameter "${peripheral_name}_Mode" + } + + add_display_item $group_name the_widget "group" + set_display_item_property the_widget widget [list ../widget/pin_mux_widget.jar Altera_hps_widget] + set_display_item_property the_widget widget_parameter_map $widget_parameter +} + +add_java_gui_parameters + +############################################## +# Clocks! +# +# All clock enable parameters go here. +# Clock frequency parameters also go here. All +# the parameters need to be declared regardless +# of whether the clock will be exercised. +# +# Validation logic will enable/show frequency +# parameters based on whether the actual clock +# is being elaborated. +# +# There are four categories of clocks in this +# component: inputs on SoC I/O +# outputs on SoC I/O +# inputs on FPGA pins +# outputs on FPGA pins +# +# Inputs on SoC I/O have user-input parameters +# so the data can be consumed by downstream +# embedded software tools. +# Outputs on SoC I/O need not have frequency +# information recorded. +# Inputs on FPGA pins have system info parameters +# so the data can be consumed by downstream +# embedded software tools. +# Outputs on FPGA pins have user input parameters +# to be consumed by Quartus via SDC. +# +############################################## +proc add_clock_parameters {} { + set TOP_LEVEL_GROUP_NAME "Input Clocks" + + set group_name "User Clocks" + add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" + + # fake group + set group_name "FPGA Interface Clocks" + add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" + + foreach interface { + f2h_axi_clock h2f_axi_clock h2f_lw_axi_clock + f2h_sdram0_clock f2h_sdram1_clock f2h_sdram2_clock + f2h_sdram3_clock f2h_sdram4_clock f2h_sdram5_clock + h2f_cti_clock h2f_tpiu_clock_in h2f_debug_apb_clock + } { + set parameter "[string toupper ${interface}]_FREQ" + add_parameter $parameter integer 100 "" + set_parameter_property $parameter display_name "${interface} clock frequency" + set_parameter_property $parameter system_info_type "CLOCK_RATE" + set_parameter_property $parameter system_info_arg $interface + set_parameter_property $parameter visible false + set_parameter_property $parameter group $group_name + } + + set peripherals [list_peripheral_names] + + # TODO: Remove the following for 12.0 + set group_name "Peripheral FPGA Clocks" + add_display_item $TOP_LEVEL_GROUP_NAME $group_name "group" "" + + # Add parameter explicitly for cross-emac ptp since it doesn't belong to a single peripheral + set parameter [form_peripheral_fpga_input_clock_frequency_parameter emac_ptp_ref_clock] + add_parameter $parameter integer 100 "" + set_parameter_property $parameter display_name "EMAC emac_ptp_ref_clock clock frequency" + set_parameter_property $parameter group $group_name + set_parameter_property $parameter system_info_type "CLOCK_RATE" + set_parameter_property $parameter system_info_arg emac_ptp_ref_clock + set_parameter_property $parameter visible false + + foreach peripheral $peripherals { + set clocks [get_peripheral_fpga_input_clocks $peripheral] + foreach clock $clocks { + set parameter [form_peripheral_fpga_input_clock_frequency_parameter $clock] + add_parameter $parameter integer 100 "" + set_parameter_property $parameter display_name "${peripheral} ${clock} clock frequency" + set_parameter_property $parameter group $group_name + set_parameter_property $parameter system_info_type "CLOCK_RATE" + set_parameter_property $parameter system_info_arg $clock + set_parameter_property $parameter visible false + } + + set clocks [get_peripheral_fpga_output_clocks $peripheral] + foreach clock $clocks { + set parameter [form_peripheral_fpga_output_clock_frequency_parameter $clock] + if { [string match "*emac?_md*" $clock]} { + add_parameter $parameter float 2.5 "" + } elseif { [string match "*emac?_gtx_clk*" $clock] } { + add_parameter $parameter integer 125 "" + } else { + add_parameter $parameter integer 100 "" + if { [string compare $peripheral "SDIO" ] == 0 } { + set_parameter_property $parameter visible false + } + } + set_parameter_property $parameter display_name "${peripheral} ${clock} clock frequency" + set_parameter_property $parameter group $group_name + set_parameter_property $parameter units Megahertz + set_parameter_property $parameter allowedRanges {1:1000} + } + + } +} +add_clock_parameters + +add_parameter hps_device_family string "" "" +set_parameter_property hps_device_family derived true +set_parameter_property hps_device_family visible false + +add_parameter device_name string "" "" +set_parameter_property device_name system_info {DEVICE} +set_parameter_property device_name visible false + +add_parameter quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces boolean "" "" +set_parameter_property quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces system_info_type quartus_ini +set_parameter_property quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces system_info_arg hps_ip_enable_all_peripheral_fpga_interfaces +set_parameter_property quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces visible false + +add_parameter quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface boolean "" "" +set_parameter_property quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface system_info_type quartus_ini +set_parameter_property quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface system_info_arg hps_ip_enable_emac0_peripheral_fpga_interface +set_parameter_property quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface visible false + +add_parameter quartus_ini_hps_ip_enable_test_interface boolean "" "" +set_parameter_property quartus_ini_hps_ip_enable_test_interface system_info_type quartus_ini +set_parameter_property quartus_ini_hps_ip_enable_test_interface system_info_arg hps_ip_enable_test_interface +set_parameter_property quartus_ini_hps_ip_enable_test_interface visible false + +add_parameter quartus_ini_hps_ip_fast_f2sdram_sim_model boolean "" "" +set_parameter_property quartus_ini_hps_ip_fast_f2sdram_sim_model system_info_type quartus_ini +set_parameter_property quartus_ini_hps_ip_fast_f2sdram_sim_model system_info_arg hps_ip_fast_f2sdram_sim_model +set_parameter_property quartus_ini_hps_ip_fast_f2sdram_sim_model visible false + +add_parameter quartus_ini_hps_ip_suppress_sdram_synth boolean "" "" +set_parameter_property quartus_ini_hps_ip_suppress_sdram_synth system_info_type quartus_ini +set_parameter_property quartus_ini_hps_ip_suppress_sdram_synth system_info_arg hps_ip_suppress_sdram_synth +set_parameter_property quartus_ini_hps_ip_suppress_sdram_synth visible false + +add_parameter quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces boolean "" "" +set_parameter_property quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces system_info_type quartus_ini +set_parameter_property quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces system_info_arg hps_ip_enable_low_speed_serial_fpga_interfaces +set_parameter_property quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces visible false + +add_parameter quartus_ini_hps_ip_enable_bsel_csel boolean "" "" +set_parameter_property quartus_ini_hps_ip_enable_bsel_csel system_info_type quartus_ini +set_parameter_property quartus_ini_hps_ip_enable_bsel_csel system_info_arg hps_ip_enable_bsel_csel +set_parameter_property quartus_ini_hps_ip_enable_bsel_csel visible false + +add_parameter quartus_ini_hps_ip_f2sdram_bonding_out boolean "" "" +set_parameter_property quartus_ini_hps_ip_f2sdram_bonding_out system_info_type quartus_ini +set_parameter_property quartus_ini_hps_ip_f2sdram_bonding_out system_info_arg hps_ip_enable_f2sdram_bonding_out +set_parameter_property quartus_ini_hps_ip_f2sdram_bonding_out visible false + + +add_parameter quartus_ini_hps_emif_pll boolean "" "" +set_parameter_property quartus_ini_hps_emif_pll system_info_type quartus_ini +set_parameter_property quartus_ini_hps_emif_pll system_info_arg hps_emif_pll +set_parameter_property quartus_ini_hps_emif_pll visible false + + +proc load_test_iface_definition {} { + set csv_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/test_iface.csv + + set data [list] + set count 0 + csv_foreach_row $csv_file cols { + incr count + if {$count == 1} { + continue + } + + lassign_trimmed $cols port width dir + lappend data $port $width $dir + } + return $data +} +add_storage_parameter test_iface_definition [load_test_iface_definition] + +# order of interfaces per peripheral should be kept +# order of ports per interface should be kept +proc load_periph_ifaces_db {} { + set interfaces_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_peripheral_interfaces.csv + set peripherals_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_peripheral_atoms.csv + set ports_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_interface_ports.csv + set pins_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_port_pins.csv + set bfm_types_file $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_hps/fpga_bfm_types.csv + + # peripherals and interfaces + set peripherals([ORDERED_NAMES]) [list] + funset interface_ports + set count 0 + set PERIPHERAL_INTERFACES_PROPERTIES_COLUMNS_START 4 + csv_foreach_row $interfaces_file cols { + incr count + # skip header + if {$count == 1} { + set ordered_names [list] + set length [llength $cols] + for {set col $PERIPHERAL_INTERFACES_PROPERTIES_COLUMNS_START} {$col < $length} {incr col} { + set col_value [lindex $cols $col] + if {$col_value != ""} { + set property_to_col($col_value) $col + lappend ordered_names $col_value + } + } + set property_to_col([ORDERED_NAMES]) $ordered_names + continue + } + + set peripheral_name [string trim [lindex $cols 0]] + set interface_name [string trim [lindex $cols 1]] + set type [string trim [lindex $cols 2]] + set dir [string trim [lindex $cols 3]] + + funset peripheral + if {[info exists peripherals($peripheral_name)]} { + array set peripheral $peripherals($peripheral_name) + } else { + funset interfaces + set interfaces([ORDERED_NAMES]) [list] + set peripheral(interfaces) [array get interfaces] + set ordered_names $peripherals([ORDERED_NAMES]) + lappend ordered_names $peripheral_name + set peripherals([ORDERED_NAMES]) $ordered_names + } + funset interfaces + array set interfaces $peripheral(interfaces) + set ordered_names $interfaces([ORDERED_NAMES]) + lappend ordered_names $interface_name + set interfaces([ORDERED_NAMES]) $ordered_names + funset interface + set interface(type) $type + set interface(direction) $dir + funset properties + foreach property $property_to_col([ORDERED_NAMES]) { + set col $property_to_col($property) + set property_value [lindex $cols $col] + + if {$property_value != ""} { + # Add Meta Property + if { [string compare [string index ${property} 0] "@" ] == 0 } { + set interface(${property}) ${property_value} + } else { + set properties($property) $property_value + } + } + } + + set interface(properties) [array get properties] + + set interfaces($interface_name) [array get interface] + set peripheral(interfaces) [array get interfaces] + set peripherals($peripheral_name) [array get peripheral] + + funset ports + set ports([ORDERED_NAMES]) [list] + set interface_ports($interface_name) [array get ports] + } + set count 0 + csv_foreach_row $peripherals_file cols { ;# peripheral atom and location table + incr count + + # skip header + if {$count == 1} { + continue + } + + set peripheral_name [string trim [lindex $cols 0]] + set atom_name [string trim [lindex $cols 1]] + + funset peripheral + if {[info exists peripherals($peripheral_name)]} { + array set peripheral $peripherals($peripheral_name) + } else { + # Assume that if a peripheral hasn't be recognized until now, we won't be using it + continue + } + set peripheral(atom_name) $atom_name + set peripherals($peripheral_name) [array get peripheral] + } + add_parameter DB_periph_ifaces string [array get peripherals] "" + set_parameter_property DB_periph_ifaces derived true + set_parameter_property DB_periph_ifaces visible false + + set p [array get peripherals] + send_message debug "DB_periph_ifaces: ${p}" + + # ports + array set ports_to_pins {} + # # prepopulate interface_ports with names of interfaces that are known + # foreach {peripheral_name peripheral_string} [array get peripherals] { + # array set peripheral_array $peripheral_string + # foreach interface_name [array names peripheral_array] { + # set interface_ports($interface_name) {} + # } + # } + set count 0 + csv_foreach_row $ports_file cols { + incr count + + # skip header + if {$count == 1} continue + + set interface_name [string trim [lindex $cols 0]] + set port_name [string trim [lindex $cols 1]] + set role [string trim [lindex $cols 2]] + set dir [string trim [lindex $cols 3]] + set atom_signal_name [string trim [lindex $cols 4]] + + funset interface + array set interface $interface_ports($interface_name) + set ordered_names $interface([ORDERED_NAMES]) + lappend ordered_names $port_name + set interface([ORDERED_NAMES]) $ordered_names + + funset port + set port(role) $role + set port(direction) $dir + set port(atom_signal_name) $atom_signal_name + set interface($port_name) [array get port] + set interface_ports($interface_name) [array get interface] + + set ports_to_pins($port_name) {} + } + add_parameter DB_iface_ports string [array get interface_ports] "" + set_parameter_property DB_iface_ports derived true + set_parameter_property DB_iface_ports visible false + + set p [array get interface_ports] + send_message debug "DB_iface_ports: ${p}" + + # peripheral signals to ports + set count 0 + csv_foreach_row $pins_file cols { + incr count + + # skip header + if {$count == 1} continue + + set peripheral_name [string trim [lindex $cols 0]] + set pin_name [string trim [lindex $cols 1]] + set port_name [string trim [lindex $cols 2]] + + set is_multibit_signal [regexp {^([a-zA-Z0-9_]+)\[([0-9]+)\]} $port_name match real_name bit] + if {$is_multibit_signal == 0} { + set bit 0 + } else { + set port_name $real_name + } + + if {[info exists ports_to_pins($port_name)] == 0} { + send_message error "Peripheral ${peripheral_name} signal ${pin_name} is defined but corresponding FPGA signal ${port_name}\[${bit}\] is not" + } else { + funset port + array set port $ports_to_pins($port_name) + + if {[info exists port($bit)]} { + # collision! + send_message error "Signal ${port_name}\[${bit}\] is having original assignment ${peripheral_name}.${port($bit)} replaced with ${peripheral_name}.${pin_name}" + } + set port($bit) $pin_name + set ports_to_pins($port_name) [array get port] + } + } + add_parameter DB_port_pins string [array get ports_to_pins] "" + set_parameter_property DB_port_pins derived true + set_parameter_property DB_port_pins visible false + + set p [array get ports_to_pins] + send_message debug "DB_port_pins: ${p}" + + # bfm types + set count 0 + funset bfm_types + csv_foreach_row $bfm_types_file cols { + incr count + + # skip header + if {$count == 1} continue + + set bfm_type_name [string trim [lindex $cols 0]] + set property_name [string trim [lindex $cols 1]] + set value [string trim [lindex $cols 2]] + + if {[info exists bfm_types($bfm_type_name)] == 0} { + set bfm_types($bfm_type_name) {} + } + funset bfm_type + array set bfm_type $bfm_types($bfm_type_name) + set bfm_type($property_name) $value + set bfm_types($bfm_type_name) [array get bfm_type] + } + add_parameter DB_bfm_types string [array get bfm_types] "" + set_parameter_property DB_bfm_types derived true + set_parameter_property DB_bfm_types visible false + # TODO: what to do so that mode information on a peripheral.pin basis can be used for elaboration??? +} + +# only run during class creation +load_periph_ifaces_db + +####################### +##### Composition ##### +####################### + +namespace eval ::fpga_interfaces { + source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_interface_generator/api.tcl +} + +namespace eval ::hps_io { + namespace eval internal { + source $env(QUARTUS_ROOTDIR)/../ip/altera/hps/altera_interface_generator/api.tcl + } + variable pins + + proc add_peripheral {peripheral_name atom_name location} { + internal::add_module_instance $peripheral_name $atom_name $location + } + + # oe used in tristate output and inout + # out used in output and inout + # in used in input and inout + proc add_pin {peripheral_name pin_name dir location in_port out_port oe_port} { + variable pins + lappend pins [list $peripheral_name $pin_name $dir $location $in_port $out_port $oe_port] + } + + proc process_pins {} { + variable pins + + set interface_name "hps_io" + set hps_io_interface_created 0 + funset ports_used ;# set of inst/ports used + funset port_wire ;# map of ports to aliased wires + foreach pin $pins { ;# Check for multiple uses of the same port and create wires for those cases + lassign $pin peripheral_name pin_name dir location in_port out_port oe_port + + # check to see if port is used multiple times + foreach port_part [list $in_port $out_port $oe_port] { + if {$port_part != "" && [info exists ports_used($port_part)]} { + # Assume only outputs will be used multiple times. Inputs would be an error + if {[info exists port_wire($port_part)] == 0} { + set port_wire($port_part) [internal::allocate_wire] + # Drive new wire with port + internal::set_wire_port_fragments $port_wire($port_part) driven_by $port_part + } + } + set ports_used($port_part) 1 + } + } + + set qip [list] + foreach pin $pins { + lassign $pin peripheral_name pin_name dir location in_port out_port oe_port + foreach port_part_ref {in_port out_port oe_port} { ;# Replace ports with wires if needed + set port_part [set $port_part_ref] + if {[info exists port_wire($port_part)]} { + set $port_part_ref [internal::wire_tofragment $port_wire($port_part)] + } + } + + # Hook things up + set instance_name [string tolower $peripheral_name] ;# is this necessary??? + if {$hps_io_interface_created == 0} { + set hps_io_interface_created 1 + internal::add_interface $interface_name conduit input + } + set export_signal_name "hps_io_${instance_name}_${pin_name}" + internal::add_interface_port $interface_name $export_signal_name $export_signal_name $dir 1 + if {[string compare $dir "input"] == 0} { + internal::set_port_fragments $interface_name $export_signal_name $in_port + internal::add_raw_sdc_constraint "set_false_path -from \[get_ports ${interface_name}_${export_signal_name}\] -to *" + } elseif {[string compare $dir "output"] == 0} { + if {[string compare $oe_port "" ] == 0} { + internal::set_port_fragments $interface_name $export_signal_name $out_port + internal::add_raw_sdc_constraint "set_false_path -from * -to \[get_ports ${interface_name}_${export_signal_name}\]" + } else { + internal::set_port_tristate_output $interface_name $export_signal_name $out_port $oe_port + internal::add_raw_sdc_constraint "set_false_path -from * -to \[get_ports ${interface_name}_${export_signal_name}\]" + } + } else { + internal::set_port_fragments $interface_name $export_signal_name $in_port + internal::set_port_tristate_output $interface_name $export_signal_name $out_port $oe_port + internal::add_raw_sdc_constraint "set_false_path -from \[get_ports ${interface_name}_${export_signal_name}\] -to *" + internal::add_raw_sdc_constraint "set_false_path -from * -to \[get_ports ${interface_name}_${export_signal_name}\]" + } + set path_to_pin "hps_io|border|${export_signal_name}\[0\]" + set location_assignment "set_instance_assignment -name HPS_LOCATION ${location} -entity %entityName% -to ${path_to_pin}" + lappend qip $location_assignment + } + set_qip_strings $qip + } + + proc init {} { + internal::init + variable pins [list] + } + + proc serialize {var_name} { + upvar 1 $var_name data + process_pins + internal::serialize data + } +} + +set_module_property composition_callback compose + +proc compose {} { + # synchronize device families between the EMIF and HPS parameter sets + set_parameter_value hps_device_family [get_parameter_value SYS_INFO_DEVICE_FAMILY] + fpga_interfaces::init + fpga_interfaces::set_bfm_types [array get DB_bfm_types] + + hps_io::init + validate + elab 0 + + update_hps_to_fpga_clock_frequency_parameters + + + fpga_interfaces::serialize fpga_interfaces_data + + add_instance fpga_interfaces altera_interface_generator + set_instance_parameter_value fpga_interfaces interfaceDefinition [array get fpga_interfaces_data] + + expose_border fpga_interfaces $fpga_interfaces_data(interfaces) + + declare_cmsis_svd $fpga_interfaces_data(interfaces) + + clear_array temp_array +} + +proc logicalview_dtg {} { + + set hard_peripheral_logical_view_dir $::env(QUARTUS_ROOTDIR)/../ip/altera/hps/hard_peripheral_logical_view + + source "$hard_peripheral_logical_view_dir/common/hps_utils.tcl" + + source "$hard_peripheral_logical_view_dir/hps_periphs/hps_periphs.tcl" + + set f2h_present [ expr [ get_parameter_value F2S_Width ] != 0] + set h2f_present [ expr [ get_parameter_value S2F_Width ] != 0] + set F2S_Width [ get_parameter_value F2S_Width ] + set S2F_Width [ get_parameter_value S2F_Width ] + set h2f_lw_present [ expr [ string compare [ get_parameter_value LWH2F_Enable ] "true" ] == 0 ] + set LWH2F_Enable [ get_parameter_value LWH2F_Enable ] + set device_family [get_parameter_value SYS_INFO_DEVICE_FAMILY] + + # Need to add whole bunch of device tree generation parameters here (dtg) + # Getting whether is it single or dual core by checking the device family. List of single core: + # Cyclone V SE + regsub "^.* V" $device_family "" se_family + regsub " " $se_family "" se_family + + set number_of_a9 0 + if { [string toupper $se_family] == "SE"} { + set number_of_a9 1 + } else { + set number_of_a9 2 + } + + set F2SDRAM_Width [get_parameter_value F2SDRAM_Width] + set F2SDRAM_Type [get_parameter_value F2SDRAM_Type] + set quartus_ini_hps_ip_f2sdram_bonding_out [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] + set BONDING_OUT_ENABLED [get_parameter_value BONDING_OUT_ENABLED] + add_instance clk_0 hps_clk_src + hps_utils_add_instance_clk_reset clk_0 bridges hps_bridge_avalon + set_instance_parameter_value bridges F2S_Width $F2S_Width + set_instance_parameter_value bridges S2F_Width $S2F_Width + set_instance_parameter_value bridges BONDING_OUT_ENABLED $BONDING_OUT_ENABLED + set_instance_parameter_value bridges LWH2F_Enable $LWH2F_Enable + set_instance_parameter_value bridges quartus_ini_hps_ip_f2sdram_bonding_out $quartus_ini_hps_ip_f2sdram_bonding_out + add_interface h2f_reset reset output + set_interface_property h2f_reset EXPORT_OF bridges.h2f_reset + set_interface_property h2f_reset PORT_NAME_MAP "h2f_rst_n h2f_rst_n" + + set rows [llength $F2SDRAM_Width] + set type_list $F2SDRAM_Type + set append_type_list "" + set append_type_width "" + set total_command_port 0 + set total_write_port 0 + set total_read_port 0 + if {$rows > 0} { + for {set i 0} {${i} < $rows} {incr i} { + set type_choice [lindex $type_list $i] + set type_width [lindex $F2SDRAM_Width $i] + if { [string compare $type_choice [F2HSDRAM_AVM]] == 0 } { + set type_id 1 + set total_command_port [expr $total_command_port + 1] + if {$type_width == 128} { + set total_write_port [expr $total_write_port + 2] + set total_read_port [expr $total_read_port + 2] + } elseif {$type_width == 256 } { + set total_write_port [expr $total_write_port + 4] + set total_read_port [expr $total_read_port + 4] + } else { + set total_write_port [expr $total_write_port + 1] + set total_read_port [expr $total_read_port + 1] + } + } elseif { [string compare $type_choice [F2HSDRAM_AVM_WRITEONLY]] == 0 } { + set type_id 2 + set total_command_port [expr $total_command_port + 1] + if {$type_width == 128} { + set total_write_port [expr $total_write_port + 2] + } elseif {$type_width == 256 } { + set total_write_port [expr $total_write_port + 4] + } else { + set total_write_port [expr $total_write_port + 1] + } + } elseif { [string compare $type_choice [F2HSDRAM_AVM_READONLY]] == 0 } { + set type_id 3 + set total_command_port [expr $total_command_port + 1] + if {$type_width == 128} { + set total_read_port [expr $total_read_port + 2] + } elseif {$type_width == 256 } { + set total_read_port [expr $total_read_port + 4] + } else { + set total_read_port [expr $total_read_port + 1] + } + } else { + set type_id 0 + if { [ expr $total_command_port % 2 ] } { + incr total_command_port 1 + } + set total_command_port [expr $total_command_port + 2] + if {$type_width == 128} { + set total_write_port [expr $total_write_port + 2] + set total_read_port [expr $total_read_port + 2] + } elseif {$type_width == 256 } { + set total_write_port [expr $total_write_port + 4] + set total_read_port [expr $total_read_port + 4] + } else { + set total_write_port [expr $total_write_port + 1] + set total_read_port [expr $total_read_port + 1] + } + } + + if {$total_command_port > 6} { + if {$type_id == 0} { + send_message error "No command ports available to allocate AXI Interface f2h_sdram${i}" + } else { + send_message error "No command ports available to allocate Avalon-MM Interface f2h_sdram${i}" + } + } + if {$total_read_port > 4} { + if {$type_id == 0} { + send_message error "No read ports available to allocate AXI Interface f2h_sdram${i}" + } else { + send_message error "No read ports available to allocate Avalon-MM Interface f2h_sdram${i}" + } + } + if {$total_write_port > 4} { + if {$type_id == 0} { + send_message error "No write ports available to allocate AXI Interface f2h_sdram${i}" + } else { + send_message error "No write ports available to allocate Avalon-MM Interface f2h_sdram${i}" + } + } + if {$total_command_port < 7 && $total_write_port < 5 && $total_read_port < 5} { + lappend append_type_list $type_id + lappend append_type_width $type_width + } + } + } + set_instance_parameter_value bridges F2SDRAM_Type $append_type_list + set_instance_parameter_value bridges F2SDRAM_Width $append_type_width + set total_command_port 0 + set total_write_port 0 + set total_read_port 0 + set bonding_out_signal [expr { [string compare [get_parameter_value BONDING_OUT_ENABLED] "true"] == 0} && {[string compare [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] "true"] == 0}] + + if {$rows > 0} { + for {set i 0} {${i} < $rows} {incr i} { + + set type_choice [lindex $type_list $i] + set type_width [lindex $F2SDRAM_Width $i] + + if { [string compare $type_choice [F2HSDRAM_AVM]] == 0 } { + set type "avalon" + set total_command_port [expr $total_command_port + 1] + if {$type_width == 128} { + set total_write_port [expr $total_write_port + 2] + set total_read_port [expr $total_read_port + 2] + } elseif {$type_width == 256 } { + set total_write_port [expr $total_write_port + 4] + set total_read_port [expr $total_read_port + 4] + } else { + set total_write_port [expr $total_write_port + 1] + set total_read_port [expr $total_read_port + 1] + } + set sdram_data "f2h_sdram${i}_ADDRESS f2h_sdram${i}_ADDRESS f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_READDATA f2h_sdram${i}_READDATA f2h_sdram${i}_READDATAVALID f2h_sdram${i}_READDATAVALID f2h_sdram${i}_READ f2h_sdram${i}_READ f2h_sdram${i}_WRITEDATA f2h_sdram${i}_WRITEDATA f2h_sdram${i}_BYTEENABLE f2h_sdram${i}_BYTEENABLE f2h_sdram${i}_WRITE f2h_sdram${i}_WRITE" + } elseif { [string compare $type_choice [F2HSDRAM_AVM_WRITEONLY]] == 0 } { + set type "avalon" + set total_command_port [expr $total_command_port + 1] + if {$type_width == 128} { + set total_write_port [expr $total_write_port + 2] + } elseif {$type_width == 256 } { + set total_write_port [expr $total_write_port + 4] + } else { + set total_write_port [expr $total_write_port + 1] + } + set sdram_data "f2h_sdram${i}_ADDRESS f2h_sdram${i}_ADDRESS f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_WRITEDATA f2h_sdram${i}_WRITEDATA f2h_sdram${i}_BYTEENABLE f2h_sdram${i}_BYTEENABLE f2h_sdram${i}_WRITE f2h_sdram${i}_WRITE" + } elseif { [string compare $type_choice [F2HSDRAM_AVM_READONLY]] == 0 } { + set type "avalon" + set total_command_port [expr $total_command_port + 1] + if {$type_width == 128} { + set total_read_port [expr $total_read_port + 2] + } elseif {$type_width == 256 } { + set total_read_port [expr $total_read_port + 4] + } else { + set total_read_port [expr $total_read_port + 1] + } + set sdram_data "f2h_sdram${i}_ADDRESS f2h_sdram${i}_ADDRESS f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_BURSTCOUNT f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_WAITREQUEST f2h_sdram${i}_READDATA f2h_sdram${i}_READDATA f2h_sdram${i}_READDATAVALID f2h_sdram${i}_READDATAVALID f2h_sdram${i}_READ f2h_sdram${i}_READ" + } else { + set type "axi" + if { [ expr $total_command_port % 2 ] } { + incr total_command_port 1 + } + set total_command_port [expr $total_command_port + 2] + if {$type_width == 128} { + set total_write_port [expr $total_write_port + 2] + set total_read_port [expr $total_read_port + 2] + } elseif {$type_width == 256 } { + set total_write_port [expr $total_write_port + 4] + set total_read_port [expr $total_read_port + 4] + } else { + set total_write_port [expr $total_write_port + 1] + set total_read_port [expr $total_read_port + 1] + } + set sdram_data "f2h_sdram${i}_ARADDR f2h_sdram${i}_ARADDR f2h_sdram${i}_ARLEN f2h_sdram${i}_ARLEN f2h_sdram${i}_ARID f2h_sdram${i}_ARID f2h_sdram${i}_ARSIZE f2h_sdram${i}_ARSIZE f2h_sdram${i}_ARBURST f2h_sdram${i}_ARBURST f2h_sdram${i}_ARLOCK f2h_sdram${i}_ARLOCK f2h_sdram${i}_ARPROT f2h_sdram${i}_ARPROT f2h_sdram${i}_ARVALID f2h_sdram${i}_ARVALID f2h_sdram${i}_ARCACHE f2h_sdram${i}_ARCACHE f2h_sdram${i}_AWADDR f2h_sdram${i}_AWADDR f2h_sdram${i}_AWLEN f2h_sdram${i}_AWLEN f2h_sdram${i}_AWID f2h_sdram${i}_AWID f2h_sdram${i}_AWSIZE f2h_sdram${i}_AWSIZE f2h_sdram${i}_AWBURST f2h_sdram${i}_AWBURST f2h_sdram${i}_AWLOCK f2h_sdram${i}_AWLOCK f2h_sdram${i}_AWPROT f2h_sdram${i}_AWPROT f2h_sdram${i}_AWVALID f2h_sdram${i}_AWVALID f2h_sdram${i}_AWCACHE f2h_sdram${i}_AWCACHE f2h_sdram${i}_BRESP f2h_sdram${i}_BRESP f2h_sdram${i}_BID f2h_sdram${i}_BID f2h_sdram${i}_BVALID f2h_sdram${i}_BVALID f2h_sdram${i}_BREADY f2h_sdram${i}_BREADY f2h_sdram${i}_ARREADY f2h_sdram${i}_ARREADY f2h_sdram${i}_AWREADY f2h_sdram${i}_AWREADY f2h_sdram${i}_RREADY f2h_sdram${i}_RREADY f2h_sdram${i}_RDATA f2h_sdram${i}_RDATA f2h_sdram${i}_RRESP f2h_sdram${i}_RRESP f2h_sdram${i}_RLAST f2h_sdram${i}_RLAST f2h_sdram${i}_RID f2h_sdram${i}_RID f2h_sdram${i}_RVALID f2h_sdram${i}_RVALID f2h_sdram${i}_WLAST f2h_sdram${i}_WLAST f2h_sdram${i}_WVALID f2h_sdram${i}_WVALID f2h_sdram${i}_WDATA f2h_sdram${i}_WDATA f2h_sdram${i}_WSTRB f2h_sdram${i}_WSTRB f2h_sdram${i}_WREADY f2h_sdram${i}_WREADY f2h_sdram${i}_WID f2h_sdram${i}_WID" + } + + if {$total_command_port > 6 || $total_write_port > 4 || $total_read_port > 4} { + break + } + add_interface f2h_sdram${i}_clock clock Input + set_interface_property f2h_sdram${i}_clock EXPORT_OF bridges.f2h_sdram${i}_clock + set_interface_property f2h_sdram${i}_clock PORT_NAME_MAP "f2h_sdram${i}_clk f2h_sdram${i}_clk" + add_interface f2h_sdram${i}_data $type slave + set_interface_property f2h_sdram${i}_data EXPORT_OF bridges.f2h_sdram${i}_data + set_interface_property f2h_sdram${i}_data PORT_NAME_MAP "$sdram_data" + } + + if $bonding_out_signal { + set bon_out_signal "f2h_sdram_BONOUT_1 f2h_sdram_BONOUT_1 f2h_sdram_BONOUT_2 f2h_sdram_BONOUT_2" + add_interface f2h_sdram_bon_out conduit Output + set_interface_property f2h_sdram_bon_out EXPORT_OF bridges.f2h_sdram_bon_out + set_interface_property f2h_sdram_bon_out PORT_NAME_MAP "$bon_out_signal" + } + + } + + set declared_svd_file 0 + set svd_path [file join $::env(QUARTUS_ROOTDIR) .. ip altera hps altera_hps altera_hps.svd] + if { $h2f_present } { + hps_utils_add_slave_interface arm_a9_0.altera_axi_master bridges.axi_h2f {0xc0000000} + if { $number_of_a9 > 1 } { + hps_utils_add_slave_interface arm_a9_1.altera_axi_master bridges.axi_h2f {0xc0000000} + } + + add_interface h2f_axi_clock clock Input + set_interface_property h2f_axi_clock EXPORT_OF bridges.h2f_axi_clock + set_interface_property h2f_axi_clock PORT_NAME_MAP "h2f_axi_clk h2f_axi_clk" + + add_interface h2f_axi_master axi master + set_interface_property h2f_axi_master EXPORT_OF bridges.h2f + set_interface_property h2f_axi_master PORT_NAME_MAP "h2f_AWID h2f_AWID h2f_AWADDR h2f_AWADDR h2f_AWLEN h2f_AWLEN h2f_AWSIZE h2f_AWSIZE h2f_AWBURST h2f_AWBURST h2f_AWLOCK h2f_AWLOCK h2f_AWCACHE h2f_AWCACHE h2f_AWPROT h2f_AWPROT h2f_AWVALID h2f_AWVALID h2f_AWREADY h2f_AWREADY h2f_WID h2f_WID h2f_WDATA h2f_WDATA h2f_WSTRB h2f_WSTRB h2f_WLAST h2f_WLAST h2f_WVALID h2f_WVALID h2f_WREADY h2f_WREADY h2f_BID h2f_BID h2f_BRESP h2f_BRESP h2f_BVALID h2f_BVALID h2f_BREADY h2f_BREADY h2f_ARID h2f_ARID h2f_ARADDR h2f_ARADDR h2f_ARLEN h2f_ARLEN h2f_ARSIZE h2f_ARSIZE h2f_ARBURST h2f_ARBURST h2f_ARLOCK h2f_ARLOCK h2f_ARCACHE h2f_ARCACHE h2f_ARPROT h2f_ARPROT h2f_ARVALID h2f_ARVALID h2f_ARREADY h2f_ARREADY h2f_RID h2f_RID h2f_RDATA h2f_RDATA h2f_RRESP h2f_RRESP h2f_RLAST h2f_RLAST h2f_RVALID h2f_RVALID h2f_RREADY h2f_RREADY" + set_interface_property h2f_axi_master SVD_ADDRESS_GROUP "hps" + set_interface_property h2f_axi_master SVD_ADDRESS_OFFSET 0xC0000000 + if {!$declared_svd_file} { + set_interface_property h2f_axi_master CMSIS_SVD_FILE $svd_path + set declared_svd_file 1 + } + } + + if { $f2h_present } { + add_interface f2h_axi_clock clock Input + set_interface_property f2h_axi_clock EXPORT_OF bridges.f2h_axi_clock + set_interface_property f2h_axi_clock PORT_NAME_MAP "f2h_axi_clk f2h_axi_clk" + + add_interface f2h_axi_slave axi slave + set_interface_property f2h_axi_slave EXPORT_OF bridges.f2h + set_interface_property f2h_axi_slave PORT_NAME_MAP "f2h_AWID f2h_AWID f2h_AWADDR f2h_AWADDR f2h_AWLEN f2h_AWLEN f2h_AWSIZE f2h_AWSIZE f2h_AWBURST f2h_AWBURST f2h_AWLOCK f2h_AWLOCK f2h_AWCACHE f2h_AWCACHE f2h_AWPROT f2h_AWPROT f2h_AWVALID f2h_AWVALID f2h_AWREADY f2h_AWREADY f2h_AWUSER f2h_AWUSER f2h_WID f2h_WID f2h_WDATA f2h_WDATA f2h_WSTRB f2h_WSTRB f2h_WLAST f2h_WLAST f2h_WVALID f2h_WVALID f2h_WREADY f2h_WREADY f2h_BID f2h_BID f2h_BRESP f2h_BRESP f2h_BVALID f2h_BVALID f2h_BREADY f2h_BREADY f2h_ARID f2h_ARID f2h_ARADDR f2h_ARADDR f2h_ARLEN f2h_ARLEN f2h_ARSIZE f2h_ARSIZE f2h_ARBURST f2h_ARBURST f2h_ARLOCK f2h_ARLOCK f2h_ARCACHE f2h_ARCACHE f2h_ARPROT f2h_ARPROT f2h_ARVALID f2h_ARVALID f2h_ARREADY f2h_ARREADY f2h_ARUSER f2h_ARUSER f2h_RID f2h_RID f2h_RDATA f2h_RDATA f2h_RRESP f2h_RRESP f2h_RLAST f2h_RLAST f2h_RVALID f2h_RVALID f2h_RREADY f2h_RREADY" + } + + if { $h2f_lw_present } { + hps_utils_add_slave_interface arm_a9_0.altera_axi_master bridges.axi_h2f_lw {0xff200000} + if { $number_of_a9 > 1 } { + hps_utils_add_slave_interface arm_a9_1.altera_axi_master bridges.axi_h2f_lw {0xff200000} + } + + add_interface h2f_lw_axi_clock clock Input + set_interface_property h2f_lw_axi_clock EXPORT_OF bridges.h2f_lw_axi_clock + set_interface_property h2f_lw_axi_clock PORT_NAME_MAP "h2f_lw_axi_clk h2f_lw_axi_clk" + + add_interface h2f_lw_axi_master axi start + set_interface_property h2f_lw_axi_master EXPORT_OF bridges.h2f_lw + set_interface_property h2f_lw_axi_master PORT_NAME_MAP "h2f_lw_AWID h2f_lw_AWID h2f_lw_AWADDR h2f_lw_AWADDR h2f_lw_AWLEN h2f_lw_AWLEN h2f_lw_AWSIZE h2f_lw_AWSIZE h2f_lw_AWBURST h2f_lw_AWBURST h2f_lw_AWLOCK h2f_lw_AWLOCK h2f_lw_AWCACHE h2f_lw_AWCACHE h2f_lw_AWPROT h2f_lw_AWPROT h2f_lw_AWVALID h2f_lw_AWVALID h2f_lw_AWREADY h2f_lw_AWREADY h2f_lw_WID h2f_lw_WID h2f_lw_WDATA h2f_lw_WDATA h2f_lw_WSTRB h2f_lw_WSTRB h2f_lw_WLAST h2f_lw_WLAST h2f_lw_WVALID h2f_lw_WVALID h2f_lw_WREADY h2f_lw_WREADY h2f_lw_BID h2f_lw_BID h2f_lw_BRESP h2f_lw_BRESP h2f_lw_BVALID h2f_lw_BVALID h2f_lw_BREADY h2f_lw_BREADY h2f_lw_ARID h2f_lw_ARID h2f_lw_ARADDR h2f_lw_ARADDR h2f_lw_ARLEN h2f_lw_ARLEN h2f_lw_ARSIZE h2f_lw_ARSIZE h2f_lw_ARBURST h2f_lw_ARBURST h2f_lw_ARLOCK h2f_lw_ARLOCK h2f_lw_ARCACHE h2f_lw_ARCACHE h2f_lw_ARPROT h2f_lw_ARPROT h2f_lw_ARVALID h2f_lw_ARVALID h2f_lw_ARREADY h2f_lw_ARREADY h2f_lw_RID h2f_lw_RID h2f_lw_RDATA h2f_lw_RDATA h2f_lw_RRESP h2f_lw_RRESP h2f_lw_RLAST h2f_lw_RLAST h2f_lw_RVALID h2f_lw_RVALID h2f_lw_RREADY h2f_lw_RREADY" + set_interface_property h2f_lw_axi_master SVD_ADDRESS_GROUP "hps" + set_interface_property h2f_lw_axi_master SVD_ADDRESS_OFFSET 0xFF200000 + if {!$declared_svd_file} { + set_interface_property h2f_lw_axi_master CMSIS_SVD_FILE $svd_path + set declared_svd_file 1 + } + } + + if {!$declared_svd_file} { + set_module_assignment "cmsis.svd.file" $svd_path + set_module_assignment "cmsis.svd.suffix" "hps" + } + + clocks_logicalview_dtg + + if { $number_of_a9 > 0 } { + hps_utils_add_instance_clk_reset clk_0 arm_a9_0 arm_a9 + } + + if { $number_of_a9 > 1 } { + hps_utils_add_instance_clk_reset clk_0 arm_a9_1 arm_a9 + } + + + hps_instantiate_arm_gic_0 $number_of_a9 + + hps_instantiate_L2 $number_of_a9 + + hps_instantiate_dma $number_of_a9 + + hps_instantiate_sysmgr $number_of_a9 + + hps_instantiate_clkmgr $number_of_a9 + + hps_instantiate_rstmgr $number_of_a9 + + hps_instantiate_fpgamgr $number_of_a9 + + hps_instantiate_uart0 $number_of_a9 "UART0_PinMuxing" [get_parameter_value l4_sp_clk_mhz] + + hps_instantiate_uart1 $number_of_a9 "UART1_PinMuxing" [get_parameter_value l4_sp_clk_mhz] + + hps_instantiate_timer0 $number_of_a9 + + hps_instantiate_timer1 $number_of_a9 + + hps_instantiate_timer2 $number_of_a9 + + hps_instantiate_timer3 $number_of_a9 + + hps_instantiate_wd_timer0 $number_of_a9 + + hps_instantiate_wd_timer1 $number_of_a9 + + hps_instantiate_gpio0 $number_of_a9 + + hps_instantiate_gpio1 $number_of_a9 + + hps_instantiate_gpio2 $number_of_a9 + + hps_instantiate_i2c0 $number_of_a9 "I2C0_PinMuxing" + + hps_instantiate_i2c1 $number_of_a9 "I2C1_PinMuxing" + + hps_instantiate_i2c2 $number_of_a9 "I2C2_PinMuxing" + + hps_instantiate_i2c3 $number_of_a9 "I2C3_PinMuxing" + + hps_instantiate_nand0 $number_of_a9 "NAND_PinMuxing" + + hps_instantiate_spim0 $number_of_a9 "SPIM0_PinMuxing" + + hps_instantiate_spim1 $number_of_a9 "SPIM1_PinMuxing" + + hps_instantiate_qspi $number_of_a9 "QSPI_PinMuxing" + + hps_instantiate_sdmmc $number_of_a9 "SDIO_PinMuxing" + + hps_instantiate_usb0 $number_of_a9 "USB0_PinMuxing" + + hps_instantiate_usb1 $number_of_a9 "USB1_PinMuxing" + + hps_instantiate_gmac0 $number_of_a9 "EMAC0_PinMuxing" + + hps_instantiate_gmac1 $number_of_a9 "EMAC1_PinMuxing" + + hps_instantiate_dcan0 $number_of_a9 "CAN0_PinMuxing" + + hps_instantiate_dcan1 $number_of_a9 "CAN1_PinMuxing" + + hps_instantiate_l3regs $number_of_a9 + + hps_instantiate_sdrctl $number_of_a9 + + hps_instantiate_axi_ocram $number_of_a9 + + hps_instantiate_axi_sdram $number_of_a9 + + hps_instantiate_timer $number_of_a9 + + hps_instantiate_scu $number_of_a9 + + add_connection arm_gic_0.arm_gic_ppi timer.interrupt_sender + set_connection_parameter_value arm_gic_0.arm_gic_ppi/timer.interrupt_sender irqNumber 13 + + if { $f2h_present } { + hps_utils_add_slave_interface bridges.axi_f2h arm_gic_0.axi_slave0 {0xfffed000} + hps_utils_add_slave_interface bridges.axi_f2h arm_gic_0.axi_slave1 {0xfffec100} + hps_utils_add_slave_interface bridges.axi_f2h L2.axi_slave0 {0xfffef000} + hps_utils_add_slave_interface bridges.axi_f2h dma.axi_slave0 {0xffe01000} + hps_utils_add_slave_interface bridges.axi_f2h sysmgr.axi_slave0 {0xffd08000} + hps_utils_add_slave_interface bridges.axi_f2h clkmgr.axi_slave0 {0xffd04000} + hps_utils_add_slave_interface bridges.axi_f2h rstmgr.axi_slave0 {0xffd05000} + hps_utils_add_slave_interface bridges.axi_f2h fpgamgr.axi_slave0 {0xff706000} + hps_utils_add_slave_interface bridges.axi_f2h fpgamgr.axi_slave1 {0xffb90000} + hps_utils_add_slave_interface bridges.axi_f2h uart0.axi_slave0 {0xffc02000} + hps_utils_add_slave_interface bridges.axi_f2h uart1.axi_slave0 {0xffc03000} + hps_utils_add_slave_interface bridges.axi_f2h timer0.axi_slave0 {0xffc08000} + hps_utils_add_slave_interface bridges.axi_f2h timer1.axi_slave0 {0xffc09000} + hps_utils_add_slave_interface bridges.axi_f2h timer2.axi_slave0 [hps_timer2_base] + hps_utils_add_slave_interface bridges.axi_f2h timer3.axi_slave0 [hps_timer3_base] + hps_utils_add_slave_interface bridges.axi_f2h gpio0.axi_slave0 {0xff708000} + hps_utils_add_slave_interface bridges.axi_f2h gpio1.axi_slave0 {0xff709000} + hps_utils_add_slave_interface bridges.axi_f2h gpio2.axi_slave0 {0xff70a000} + hps_utils_add_slave_interface bridges.axi_f2h i2c0.axi_slave0 {0xffc04000} + hps_utils_add_slave_interface bridges.axi_f2h i2c1.axi_slave0 {0xffc05000} + hps_utils_add_slave_interface bridges.axi_f2h i2c2.axi_slave0 {0xffc06000} + hps_utils_add_slave_interface bridges.axi_f2h i2c3.axi_slave0 {0xffc07000} + hps_utils_add_slave_interface bridges.axi_f2h nand0.axi_slave0 {0xff900000} + hps_utils_add_slave_interface bridges.axi_f2h nand0.axi_slave1 {0xffb80000} + hps_utils_add_slave_interface bridges.axi_f2h spim0.axi_slave0 [hps_spim0_base] + hps_utils_add_slave_interface bridges.axi_f2h spim1.axi_slave0 [hps_spim1_base] + hps_utils_add_slave_interface bridges.axi_f2h qspi.axi_slave0 {0xff705000} + hps_utils_add_slave_interface bridges.axi_f2h qspi.axi_slave1 {0xffa00000} + hps_utils_add_slave_interface bridges.axi_f2h sdmmc.axi_slave0 {0xff704000} + hps_utils_add_slave_interface bridges.axi_f2h usb0.axi_slave0 {0xffb00000} + hps_utils_add_slave_interface bridges.axi_f2h usb1.axi_slave0 {0xffb40000} + hps_utils_add_slave_interface bridges.axi_f2h gmac0.axi_slave0 {0xff700000} + hps_utils_add_slave_interface bridges.axi_f2h gmac1.axi_slave0 {0xff702000} + hps_utils_add_slave_interface bridges.axi_f2h axi_ocram.axi_slave0 {0xffff0000} + hps_utils_add_slave_interface bridges.axi_f2h axi_sdram.axi_slave0 [hps_sdram_base] + hps_utils_add_slave_interface bridges.axi_f2h timer.axi_slave0 {0xfffec600} + hps_utils_add_slave_interface bridges.axi_f2h dcan0.axi_slave0 [hps_dcan0_base] + hps_utils_add_slave_interface bridges.axi_f2h dcan1.axi_slave0 [hps_dcan1_base] + hps_utils_add_slave_interface bridges.axi_f2h l3regs.axi_slave0 [hps_l3regs_base] + hps_utils_add_slave_interface bridges.axi_f2h sdrctl.axi_slave0 [hps_sdrctl_base] + } + + ##### F2H ##### + if [is_enabled F2SINTERRUPT_Enable] { + set any_interrupt_enabled 1 + set iname "f2h_irq" + set pname "f2h_irq" + add_interface "${iname}0" interrupt receiver + set_interface_property f2h_irq0 EXPORT_OF arm_gic_0.f2h_irq_0_irq_rx_offset_40 + set_interface_property f2h_irq0 PORT_NAME_MAP "f2h_irq_p0 irq_siq_40" + + add_interface "${iname}1" interrupt receiver + set_interface_property f2h_irq1 EXPORT_OF arm_gic_0.f2h_irq_32_irq_rx_offset_72 + set_interface_property f2h_irq1 PORT_NAME_MAP "f2h_irq_p1 irq_siq_72" + } +} + +set_module_property OPAQUE_ADDRESS_MAP false +set_module_property STRUCTURAL_COMPOSITION_CALLBACK compose_logicalview +proc compose_logicalview {} { + # synchronize device families between the EMIF and HPS parameter sets + set_parameter_value hps_device_family [get_parameter_value SYS_INFO_DEVICE_FAMILY] + fpga_interfaces::init + fpga_interfaces::set_bfm_types [array get DB_bfm_types] + + hps_io::init + validate + elab 1 + + update_hps_to_fpga_clock_frequency_parameters + + + fpga_interfaces::serialize fpga_interfaces_data + + add_instance fpga_interfaces altera_interface_generator + set_instance_parameter_value fpga_interfaces interfaceDefinition [array get fpga_interfaces_data] + + expose_border fpga_interfaces $fpga_interfaces_data(interfaces) + + #declare_cmsis_svd $fpga_interfaces_data(interfaces) + + logicalview_dtg +} + +proc declare_cmsis_svd {interfaces_str} { + array set interfaces $interfaces_str + set interface_names $interfaces([ORDERED_NAMES]) + + set h2f_exists 0 + set lwh2f_exists 0 + foreach interface_name $interface_names { + if {[string compare $interface_name "h2f_axi_master"] == 0} { + set h2f_exists 1 + } elseif {[string compare $interface_name "h2f_lw_axi_master"] == 0} { + set lwh2f_exists 1 + } + } + + set svd_path [file join $::env(QUARTUS_ROOTDIR) .. ip altera hps altera_hps altera_hps.svd] + set address_group hps + set declared_svd_file 0 + + if {$h2f_exists} { + if {!$declared_svd_file} { + set_interface_property h2f_axi_master CMSIS_SVD_FILE $svd_path + set declared_svd_file 1 + } + set_interface_property h2f_axi_master SVD_ADDRESS_GROUP $address_group + set_interface_property h2f_axi_master SVD_ADDRESS_OFFSET 0xC0000000 + } + if {$lwh2f_exists} { + if {!$declared_svd_file} { + set_interface_property h2f_lw_axi_master CMSIS_SVD_FILE $svd_path + set declared_svd_file 1 + } + set_interface_property h2f_lw_axi_master SVD_ADDRESS_GROUP $address_group + set_interface_property h2f_lw_axi_master SVD_ADDRESS_OFFSET 0xFF200000 + } + if {!$declared_svd_file} { + set_module_assignment "cmsis.svd.file" $svd_path + set_module_assignment "cmsis.svd.suffix" $address_group + } +} + + +###################### +##### Validation ##### +###################### + +proc validate {} { + set device_family [get_parameter_value hps_device_family] + set device [get_device] + ensure_pin_muxing_data $device_family + update_table_derived_parameters + + validate_F2SDRAM + update_S2F_CLK_mux_options + update_pin_muxing_ui $device_family + + # funset placement_by_pin + validate_pin_muxing $device_family placement_by_pin + update_gpio_ui placement_by_pin + + validate_TEST + + validate_interrupt $device_family + + validate_clocks + +} + +proc validate_TEST {} { + set ini [get_parameter_value quartus_ini_hps_ip_enable_test_interface] + set_parameter_property TEST_Enable visible $ini +} + +proc hide_param { paramName hide} { + +} +proc update_hps_to_fpga_clock_frequency_parameters {} { + set u0 [get_parameter_value S2FCLK_USER0CLK_Enable] + set u1 [get_parameter_value S2FCLK_USER1CLK_Enable] + #set u2 [get_parameter_value S2FCLK_USER2CLK_Enable] + + for { set i 0 } { $i < 2 } { incr i } { + set_parameter_property "S2FCLK_USER${i}CLK_FREQ" enabled [expr "\$u${i}"] + + if { [string compare true [expr "\$u${i}"] ] == 0 } { + fpga_interfaces::set_interface_property "h2f_user${i}_clock" clockRateKnown true + fpga_interfaces::set_interface_property "h2f_user${i}_clock" clockRate [expr [get_parameter_value "S2FCLK_USER${i}CLK_FREQ"] * 1000000 ] + } + } +} + +proc update_table_derived_parameters {} { + update_f2sdram_names + update_dma_peripheral_ids +} + +proc update_f2sdram_names {} { + set num_rows [llength [get_parameter_value F2SDRAM_Width]] + set names [list] + + for {set index 0} {$index < $num_rows} {incr index} { + set name "f2h_sdram${index}" + lappend names $name + } + set_parameter_value F2SDRAM_Name_DERIVED ${names} +} + +proc update_dma_peripheral_ids {} { + set periph_id_list {0 1 2 3 4 5 6 7} + set_parameter_value DMA_PeriphId_DERIVED $periph_id_list +} + +proc is_enabled {parameter} { + if { [string compare [get_parameter_value $parameter] "true" ] == 0 } { + return 1 + } else { + return 0 + } +} + +proc validate_F2SDRAM {} { + set type_list [get_parameter_value F2SDRAM_Type] + set width_list [get_parameter_value F2SDRAM_Width] + set rows [llength $width_list] + + set command_ports_bit 0 + set read_ports_bit 0 + set write_ports_bit 0 + + set command_ports_mask 0 + set read_ports_mask 0 + set write_ports_mask 0 + set reset_ports_mask 0 + + for {set index 0} {${index} < ${rows}} {incr index} { + # check for invalid combinations of type/width + set mytype [lindex $type_list $index] + set mywidth [lindex $width_list $index] + + if {$mywidth < 64} { + send_message warning "Setting the slave port width of interface f2h_sdram${index} to ${mywidth} results in bandwidth under-utilization. Altera recommends you set the interface data width to 64-bit or greater." + } + + # count used ports + # command + if { [string compare $mytype [F2HSDRAM_AXI3]] == 0 } { + if { [ expr $command_ports_bit % 2 ] } { + incr command_ports_bit 1 + } + set command_ports_mask [ expr $command_ports_mask | ( 3 << $command_ports_bit) ] + incr command_ports_bit 2 + } else { + set command_ports_mask [ expr $command_ports_mask | ( 1 << $command_ports_bit) ] + incr command_ports_bit 1 + } + + # read + if {$mytype != [F2HSDRAM_AVM_WRITEONLY]} { + if {$mywidth <= 64} { + set read_ports_mask [ expr $read_ports_mask | ( 1 << $read_ports_bit) ] + incr read_ports_bit 1 + } elseif {$mywidth == 128} { + set read_ports_mask [ expr $read_ports_mask | ( 3 << $read_ports_bit) ] + incr read_ports_bit 2 + } else { + set read_ports_mask [ expr $read_ports_mask | ( 15 << $read_ports_bit) ] + incr read_ports_bit 4 + } + } + + # write + if {$mytype != [F2HSDRAM_AVM_READONLY]} { + if {$mywidth <= 64} { + set write_ports_mask [ expr $write_ports_mask | ( 1 << $write_ports_bit) ] + incr write_ports_bit 1 + } elseif {$mywidth == 128} { + set write_ports_mask [ expr $write_ports_mask | ( 3 << $write_ports_bit) ] + incr write_ports_bit 2 + } else { + set write_ports_mask [ expr $write_ports_mask | ( 15 << $write_ports_bit) ] + incr write_ports_bit 4 + } + } + + # reset + set reset_ports_mask [ expr ($command_ports_mask << 8) | ($write_ports_mask << 4) | ($read_ports_mask) ] + + } + # check for port over-use + if {$command_ports_bit > 6} { + send_message error "The current FPGA to SDRAM configuration is using more command ports than are available." + } + if {$read_ports_bit > 4} { + send_message error "The current FPGA to SDRAM configuration is using more read ports than are available." + } + if {$write_ports_bit > 4} { + send_message error "The current FPGA to SDRAM configuration is using more write ports than are available." + } + + # Store ports used & number of elements to determine when new rows are added + set_parameter_value F2SDRAM_Width_Last_Size $rows + set_parameter_value F2SDRAM_CMD_PORT_USED [ format "0x%X" $command_ports_mask ] + set_parameter_value F2SDRAM_RD_PORT_USED [ format "0x%X" $read_ports_mask ] + set_parameter_value F2SDRAM_WR_PORT_USED [ format "0x%X" $write_ports_mask ] + set_parameter_value F2SDRAM_RST_PORT_USED [ format "0x%X" $reset_ports_mask ] + + # Bonding_out signals will be exported if f2sdram selected + if { ${rows} > 0 } { + set param [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] + set_parameter_property BONDING_OUT_ENABLED visible $param + set_parameter_property BONDING_OUT_ENABLED enabled $param + } else { + set_parameter_property BONDING_OUT_ENABLED enabled false + } + +} + +proc update_S2F_CLK_mux_options {} { + # TODO: retrieve mux options + # TODO: set allowed_ranges on muxes +} + +proc dec2bin {i} { + set res {} + while {$i>0} { + set res [ expr {$i%2} ]$res + set i [expr {$i/2}] + } + if {$res == {}} { + set res 0 + } + return $res +} + +##################################################################### +# +# Gets valid modes for a peripheral with a given pin muxing option. +# Parameters: * peripheral_ref: name of an array pointing to the +# Peripheral HPS I/O Data +# +# Update parameter value with label +proc get_valid_modes {peripheral_name pin_muxing_option peripheral_ref fpga_available} { +##################################################################### + upvar 1 $peripheral_ref peripheral + + if {[info exists peripheral(pin_sets)]} { + array set pin_sets $peripheral(pin_sets) + } + + if {[info exists pin_sets($pin_muxing_option)]} { + array set pin_set $pin_sets($pin_muxing_option) + set pin_set_modes $pin_set(valid_modes) + if {[string match -nocase "trace" $peripheral_name]} { + set valid_modes [list "HPS:8-bit Data" "HPSx4:4-bit Data"] + } elseif {[string match -nocase "usb*" $peripheral_name]} { + set valid_modes [list "SDR:SDR with PHY clock output mode" "SDR without external clock:SDR with PHY clock input mode"] + } else { + set valid_modes [lsort -ascii -increasing $pin_set_modes] + } + } elseif {$fpga_available && [string compare $pin_muxing_option [FPGA_MUX_VALUE]] == 0} { + set valid_modes [list "Full"] + } else { + set valid_modes [list [NA_MODE_VALUE]] + } + return $valid_modes +} + +proc is_peripheral_low_speed_serial_interface {peripheral_name} { + if {[string match -nocase "i2c*" $peripheral_name] || + [string match -nocase "can*" $peripheral_name] || + [string match -nocase "spi*" $peripheral_name] || + [string match -nocase "uart*" $peripheral_name] + } { + return 1 + } + return 0 +} + +# updates the _PinMuxing and _Mode parameter allowed ranges +# -uses a data structure to keep track of choices +# -allowed ranges can come from FPGA Peripheral Interfaces or IOs +# -when a pin muxing option is selected, the mode allowed ranges are +# set according to what's specified from the source (FPGA or pin i/o) +proc update_pin_muxing_ui {device_family} { + + set peripheral_names [list_peripheral_names] + foreach peripheral $peripheral_names { + + get_peripheral_parameter_valid_ranges hps_ip_pin_muxing_model $peripheral\ + selected_pin_muxing_option pin_muxing_options mode_options + + set pin_muxing_param_name [format [PIN_MUX_PARAM_FORMAT] $peripheral] + set mode_param_name [format [MODE_PARAM_FORMAT] $peripheral] + + set pin_muxing_options [lsort -ascii $pin_muxing_options] + set pin_muxing_options [linsert $pin_muxing_options 0 [UNUSED_MUX_VALUE]] + set_parameter_property $pin_muxing_param_name enabled true + set_parameter_property $pin_muxing_param_name visible true + set_parameter_property $pin_muxing_param_name allowed_ranges $pin_muxing_options + set_parameter_property $mode_param_name visible true + + + set selected_mode_option [get_parameter_value $mode_param_name] + + # Disable I2C parameters so they can only be changed by altering EMAC parameters + # in the HPS IP GUI + if {([string compare $peripheral "I2C2" ] == 0 || [string compare $peripheral "I2C3" ] == 0) + && [string match "*EMAC*" $selected_mode_option]} { + set_parameter_property $pin_muxing_param_name enabled false + set_parameter_property $mode_param_name enabled false + } else { + set_parameter_property $mode_param_name enabled true + } + set_parameter_property $mode_param_name allowed_ranges $mode_options + + # Disabled peripherals that not supported by certain device family + if {[check_device_family_equivalence $device_family ARRIAV]} { + foreach excluded_peripheral [ARRIAV_EXCLUDED_PERIPHRERALS] { + if {[string compare $excluded_peripheral $peripheral] == 0} { + set_parameter_property $pin_muxing_param_name enabled false + set_parameter_property $pin_muxing_param_name visible false + set_parameter_property $mode_param_name enabled false + set_parameter_property $mode_param_name visible false + } + } + } + } + + # Only show I2C's "Used by EMACx" modes when EMAC is using I2C + if {[is_pin_mux_data_available hps_ip_pin_muxing_model]} { + foreach emac {EMAC0 EMAC1} { + set emac_pin_set [get_parameter_value [format [PIN_MUX_PARAM_FORMAT] $emac]] + set emac_mode [get_parameter_value [format [MODE_PARAM_FORMAT] $emac]] + + funset i2c_name + get_linked_peripheral hps_ip_pin_muxing_model $emac $emac_pin_set\ + i2c_name i2c_pin_set i2c_mode + + if {[info exists i2c_name] && ![string match "*${i2c_name}*" $emac_mode]} { + # remove EMAC mode + set i2c_mode_param [format [MODE_PARAM_FORMAT] $i2c_name] + set i2c_valid_modes [get_parameter_property $i2c_mode_param ALLOWED_RANGES] + + set new_i2c_valid_modes [list] + foreach mode $i2c_valid_modes { + if {![string match "*${emac}*" $mode]} { + lappend new_i2c_valid_modes $mode + } + } + set_parameter_property $i2c_mode_param ALLOWED_RANGES $new_i2c_valid_modes + } + } + } +} + +proc validate_interrupt {device_family} { + set interrupt_groups [list_h2f_interrupt_groups] + set excluded "CAN" + foreach interrupt_group $interrupt_groups { + set parameter "S2FINTERRUPT_${interrupt_group}_Enable" + set_parameter_property $parameter enabled true + set_parameter_property $parameter visible true + if {[check_device_family_equivalence $device_family ARRIAV] && [string compare $excluded $interrupt_group] == 0} { + set_parameter_property $parameter enabled false + set_parameter_property $parameter visible false + } + } +} + +proc update_gpio_ui {placement_by_pin_ref} { + upvar 1 $placement_by_pin_ref placement_by_pin + # TODO: caching of what needs to be updated? + set customer_pin_names [list] + set gpio_names [list] + set loanio_names [list] + set conflicts [list] + + set customer_pin_names [hps_ip_pin_muxing_model::get_customer_pin_names] + + foreach_gpio_entry hps_ip_pin_muxing_model\ + entry gpio_index gpio_name pin gplin_used gplin_select\ + { + lappend gpio_names $gpio_name + + set conflict "" + if {[info exists placement_by_pin($pin)]} { + set conflict [join $placement_by_pin($pin) ", "] + } + lappend conflicts $conflict + } + foreach_loan_io_entry hps_ip_pin_muxing_model\ + entry loanio_index loanio_name pin gplin_used gplin_select\ + { + lappend loanio_names $loanio_name + } + set_parameter_value Customer_Pin_Name_DERIVED $customer_pin_names + set_parameter_value GPIO_Name_DERIVED $gpio_names + set_parameter_value LOANIO_Name_DERIVED $loanio_names + set_parameter_value GPIO_Conflict_DERIVED $conflicts +} + +proc peripheral_to_wys_atom_name {device_family peripheral} { + set generic_atom_name [hps_io_peripheral_to_generic_atom_name $peripheral] + set wys_atom_name [generic_atom_to_wys_atom $device_family $generic_atom_name] + return $wys_atom_name +} + +# TODO: deal with going out of bounds (gpio_index > 70) +proc gpio_index_to_gpio_port_index {gpio_index} { + set group [expr {$gpio_index / 29}] + set port_index [expr {$gpio_index % 29}] + + set result [list $group $port_index] + return $result +} + + + +proc validate_pin_muxing {device_family placement_by_pin_ref} { + upvar 1 $placement_by_pin_ref placement_by_pin + + # see which pins are being used more than once + # peripherals + funset pin_to_peripheral ;# pin names to peripheral that is occupying + funset conflict_pin_list ; + + foreach peripheral_name [list_peripheral_names] { + set pins_used 0 + set mapping_msg "Peripheral $peripheral_name pin mapping:" + set comma " " + set periph_inst [string tolower "${peripheral_name}_inst"] + foreach_used_peripheral_pin hps_ip_pin_muxing_model $peripheral_name\ + signal_name\ + map\ + pin\ + location\ + mux_select\ + { + # Validate + set entry_exists [info exists pin_to_peripheral($pin)] + if {$entry_exists == 1} { + set conflicting_peripheral $pin_to_peripheral($pin) + # only emit an error once per unique pair of conflicting peripherals + if {[info exists known_conflicts($conflicting_peripheral)] == 0} { + set known_conflicts($conflicting_peripheral) 1 + # TODO: more detailed error message e.g. which pins? explicitly say the bank and modes? + send_message error "Refer to the Peripherals Mux Table for more details. The selected peripherals '$conflicting_peripheral' and '$peripheral_name' are conflicting. " + } + set conflict_pin_list($pin) 1 + } else { + set pin_to_peripheral($pin) $peripheral_name + } + + # Render pins + lassign $map in_port out_port oe_port + set goes_out 0 + set goes_in 0 + + # by default, all signals are assumed to be from the same instance + if {$in_port != ""} { + set in_port "${periph_inst}:${in_port}" + set goes_in 1 + } + if {$out_port != ""} { + set out_port "${periph_inst}:${out_port}" + set goes_out 1 + } + if {$oe_port != ""} { + set oe_port "${periph_inst}:${oe_port}" + set goes_out 1 + } + + if {$goes_in && $goes_out} { + set dir bidir + } elseif {$goes_out} { + set dir output + } else { + set dir input + } + + hps_io::add_pin $periph_inst $signal_name $dir $location $in_port $out_port $oe_port + + if {[info exists placement_by_pin($pin)] == 0} { + set placement_by_pin($pin) [list] + } + lappend placement_by_pin($pin) "${peripheral_name}.${signal_name}" + + set mapping_msg "${mapping_msg}${comma}${signal_name}:${pin}" + set comma ", " + set pins_used 1 + } + if {$pins_used} { + # send_message info $mapping_msg + set wys_atom_name [peripheral_to_wys_atom_name $device_family $peripheral_name] + set location [locations::get_hps_io_peripheral_location $peripheral_name] + hps_io::add_peripheral ${periph_inst} $wys_atom_name $location + } + } + + # HLGPI input only pins + set hlgpi_pins [hps_ip_pin_muxing_model::get_hlgpi_pins] + set hlgpi_count [llength $hlgpi_pins] + set wys_atom_name [peripheral_to_wys_atom_name $device_family "GPIO"] + set periph_inst "gpio_inst" + set gpio_unused 1 + set device [get_device] + + if { [ string range $device 0 3 ] == "5CSE" && [ string range $device 8 9 ] == "19" } { + send_message info "HLGPI is not available for Device $device (484 pins)" + set_parameter_property HLGPI_Enable enabled false + } else { + set_parameter_property HLGPI_Enable enabled true + } + + if { [is_enabled HLGPI_Enable] && [get_parameter_property HLGPI_Enable enabled] } { + for {set hlgpi_pin_index 0} {$hlgpi_pin_index < $hlgpi_count} {incr hlgpi_pin_index} { + # HLGPI connected to gpio[26:13] + set gpio_port_index [ expr {$hlgpi_pin_index + 13} ] + set hlgpi_pin [ lindex $hlgpi_pins $hlgpi_pin_index] + + if {$gpio_unused} { + set atom_location [locations::get_hps_io_peripheral_location "GPIO"] + hps_io::add_peripheral ${periph_inst} $wys_atom_name $atom_location + set gpio_unused 0 + } + + set signal_name "HLGPI${hlgpi_pin_index}" + set pin_location [::pin_mux_db::get_location_of_pin $hlgpi_pin] + set in_port "${periph_inst}:GPIO2_PORTA_I($gpio_port_index:$gpio_port_index)" + set out_port "" + set oe_port "" + + hps_io::add_pin ${periph_inst} $signal_name input $pin_location $in_port $out_port $oe_port + } + } + + # gpio + funset gpio_port_placement_set ;# set of gpio ports that are being used + set enable_list [get_parameter_value GPIO_Enable] + set wys_atom_name [peripheral_to_wys_atom_name $device_family "GPIO"] + set periph_inst "gpio_inst" + + # check and set GPIO_Pin_Used_DERIVED parameter + set_parameter_value GPIO_Pin_Used_DERIVED false + + foreach_gpio_entry hps_ip_pin_muxing_model\ + entry gpio_index gpio_name pin gplin_used gplin_select\ + { + set enabled 0 + set enable_value [lindex $enable_list $entry] + if { [string compare $enable_value "Yes" ] == 0 } { + set enabled 1 + } + if {$enabled} { + set entry_exists [info exists pin_to_peripheral($pin)] + if {$entry_exists} { + set conflicting_peripheral $pin_to_peripheral($pin) + send_message error "Refer to the Peripherals Mux Table for more details. The selected peripheral '$conflicting_peripheral' and '${gpio_name}' are conflicting." + set conflict_pin_list($pin) 1 + } else { + set pin_to_peripheral($pin) $gpio_name + } + + if {[info exists gpio_port_placement_set($gpio_index)]} { + send_message error "Refer to the Peripherals Mux Table for more details. GPIO${gpio_index} cannot be used twice." + set conflict_pin_list($pin) 1 + } else { + set gpio_port_placement_set($gpio_index) 1 + } + + if {$gpio_unused} { + set atom_location [locations::get_hps_io_peripheral_location "GPIO"] + hps_io::add_peripheral ${periph_inst} $wys_atom_name $atom_location + set gpio_unused 0 + } + + lassign [gpio_index_to_gpio_port_index $gpio_index] gpio_group gpio_port_index + set in_port "${periph_inst}:GPIO${gpio_group}_PORTA_I($gpio_port_index:$gpio_port_index)" + set out_port "${periph_inst}:GPIO${gpio_group}_PORTA_O($gpio_port_index:$gpio_port_index)" + set oe_port "${periph_inst}:GPIO${gpio_group}_PORTA_OE($gpio_port_index:$gpio_port_index)" + + set pin_location [::pin_mux_db::get_location_of_pin $pin] + hps_io::add_pin $periph_inst $gpio_name bidir $pin_location $in_port $out_port $oe_port + + # set GPIO_Pin_Used_DERIVED to true if GPIO pins used + set_parameter_value GPIO_Pin_Used_DERIVED true + } + } + + # loan i/o + set enable_list [get_parameter_value LOANIO_Enable] + set loanio_used 0 + set loanio_count 0 + foreach_loan_io_entry hps_ip_pin_muxing_model\ + entry loanio_index loanio_name pin gplin_used gplin_select\ + { + if {$loanio_count < $loanio_index} { + set loanio_count $loanio_index + } + set enabled 0 + set enable_value [lindex $enable_list $entry] + if { [string compare $enable_value "Yes" ] == 0 } { + set enabled 1 + } + + if {$enabled} { + set entry_exists [info exists pin_to_peripheral($pin)] + if {$entry_exists} { + set conflicting_peripheral $pin_to_peripheral($pin) + send_message error "Refer to the Peripherals Mux Table for more details. The selected peripheral for '$conflicting_peripheral' and '${loanio_name}' are conflicting." + set conflict_pin_list($pin) 1 + } else { + set pin_to_peripheral($pin) $loanio_name + } + + if {[info exists gpio_port_placement_set($loanio_index)]} { + send_message error "Refer to the Peripherals Mux Table for more details. GPIO${loanio_index} cannot be used twice." + set conflict_pin_list($pin) 1 + } else { + set gpio_port_placement_set($loanio_index) 1 + } + + set loanio_used 1 + if {$gpio_unused} { + set atom_location [locations::get_hps_io_peripheral_location "GPIO"] + hps_io::add_peripheral ${periph_inst} $wys_atom_name $atom_location + set gpio_unused 0 + } + + lassign [gpio_index_to_gpio_port_index $loanio_index] gpio_group gpio_port_index + set in_port "${periph_inst}:GPIO${gpio_group}_PORTA_I($gpio_port_index:$gpio_port_index)" + set out_port "${periph_inst}:GPIO${gpio_group}_PORTA_O($gpio_port_index:$gpio_port_index)" + set oe_port "${periph_inst}:GPIO${gpio_group}_PORTA_OE($gpio_port_index:$gpio_port_index)" + + set pin_location [::pin_mux_db::get_location_of_pin $pin] + hps_io::add_pin $periph_inst $loanio_name bidir $pin_location $in_port $out_port $oe_port + + } + } + incr loanio_count ;# count is one greater than the highest index + if $loanio_used { + set wys_atom_name [peripheral_to_wys_atom_name $device_family "LOANIO"] + set location {} + set periph_inst "loan_io_inst" + set iface_name "h2f_loan_io" + set z "h2f_loan_" + fpga_interfaces::add_module_instance ${periph_inst} $wys_atom_name $location + fpga_interfaces::add_interface $iface_name conduit Input + set pin_muxing [get_parameter_value pin_muxing] + fpga_interfaces::add_interface_port $iface_name "${z}in" in Output ${loanio_count} $periph_inst loanio_in + fpga_interfaces::add_interface_port $iface_name "${z}out" out Input ${loanio_count} $periph_inst loanio_out + fpga_interfaces::add_interface_port $iface_name "${z}oe" oe Input ${loanio_count} $periph_inst loanio_oe + + # add loanIO to GPIO atom connection + set loanio_periph_inst "loan_io_inst" + set loanio_iface_name "loanio_gpio" + set loanio_z "loanio_gpio_" + set gpio_periph_inst "gpio_inst" + set gpio_iface_name "gpio_loanio" + set gpio_z "gpio_loanio_" + set gpio_port_size 29 + set start_index 0 + + if {$gpio_unused} { + set gpio_wys_atom_name [peripheral_to_wys_atom_name $device_family "GPIO"] + set gpio_atom_location [locations::get_hps_io_peripheral_location "GPIO"] + hps_io::add_peripheral ${gpio_periph_inst} ${gpio_wys_atom_name} ${gpio_atom_location} + set gpio_unused 0 + } + + fpga_interfaces::add_interface $loanio_iface_name conduit Input "NO_EXPORT" + ::hps_io::internal::add_interface $gpio_iface_name conduit Output "NO_EXPORT" + + for {set i 0} {$i <= 2} {incr i} { + if {[expr ($loanio_count - $start_index)] < $gpio_port_size} { + set gpio_port_size [expr ($loanio_count - $start_index)] + } + set end_index [expr ($start_index + $gpio_port_size - 1)] + + fpga_interfaces::add_interface_port $loanio_iface_name "${loanio_z}loanio${i}_i" "loanio${i}_i" Input ${gpio_port_size} + fpga_interfaces::add_interface_port $loanio_iface_name "${loanio_z}loanio${i}_oe" "loanio${i}_oe" Output ${gpio_port_size} + fpga_interfaces::add_interface_port $loanio_iface_name "${loanio_z}loanio${i}_o" "loanio${i}_o" Output ${gpio_port_size} + + fpga_interfaces::set_port_fragments $loanio_iface_name "${loanio_z}loanio${i}_i" "${loanio_periph_inst}:GPIO_IN($end_index:$start_index)" + fpga_interfaces::set_port_fragments $loanio_iface_name "${loanio_z}loanio${i}_oe" "${loanio_periph_inst}:GPIO_OE($end_index:$start_index)" + fpga_interfaces::set_port_fragments $loanio_iface_name "${loanio_z}loanio${i}_o" "${loanio_periph_inst}:GPIO_OUT($end_index:$start_index)" + + ::hps_io::internal::add_interface_port $gpio_iface_name "${gpio_z}loanio${i}_i" "loanio${i}_i" Output ${gpio_port_size} $gpio_periph_inst "LOANIO${i}_I" + ::hps_io::internal::add_interface_port $gpio_iface_name "${gpio_z}loanio${i}_oe" "loanio${i}_oe" Input ${gpio_port_size} $gpio_periph_inst "LOANIO${i}_OE" + ::hps_io::internal::add_interface_port $gpio_iface_name "${gpio_z}loanio${i}_o" "loanio${i}_o" Input ${gpio_port_size} $gpio_periph_inst "LOANIO${i}_O" + + set start_index [expr ($end_index + 1)] + } + } + set conflicts [list] + set pins [list] + foreach_gpio_entry hps_ip_pin_muxing_model\ + entry gpio_index gpio_name pin gplin_used gplin_select\ + { + set entry_exists [info exists conflict_pin_list($pin)] + if {$entry_exists} { + set conflict "Yes" + } else { + set conflict "No" + } + lappend conflicts $conflict + lappend pins $pin + } + set_parameter_value JAVA_CONFLICT_PIN $conflicts + set_parameter_value JAVA_GUI_PIN_LIST $pins +} + +##################################################### +# +# Sets a valid mode for the peripheral when its pin +# muxing option changes. Will try to retain the +# original mode if available. +# +proc on_altered_peripheral_pin_muxing {peripheral_name} { +##################################################### + set mode_param_name "${peripheral_name}_Mode" + set mode_option [get_parameter_value $mode_param_name] + + get_peripheral_parameter_valid_ranges hps_ip_pin_muxing_model $peripheral_name\ + selected_pin_muxing_option pin_muxing_options new_valid_modes + + # filter the label name of the parameter value if exist + if {[lsearch $new_valid_modes $mode_option] == -1} { + regsub ":.*" [lindex $new_valid_modes 0] "" new_mode_option + } else { + set new_mode_option $mode_option + } + set_parameter_value $mode_param_name $new_mode_option + + if {[string match "*EMAC*" $peripheral_name]} { + on_emac_mode_switch_internal $peripheral_name + } +} + +# Adds the pin muxing model argument +proc on_emac_mode_switch_internal {peripheral_name} { + on_emac_mode_switch hps_ip_pin_muxing_model $peripheral_name +} + +proc validate_and_update_ddr {} { + set desired_operational_freq [get_parameter_value DDR_DesiredFreq] + if {$desired_operational_freq < 0.0} { + send_message error "The operational frequency of the DDR Controller cannot be negative." + } else { + send_message warning "The recommended DDR Controller clock frequency and phase shift information is not correct." + + set_parameter_value DDR_PLLC0RecommendedFreq_DERIVED $desired_operational_freq + set_parameter_value DDR_PLLC1RecommendedFreq_DERIVED [expr $desired_operational_freq * 2.0] + set_parameter_value DDR_PLLC2RecommendedFreq_DERIVED $desired_operational_freq + set_parameter_value DDR_PLLC3RecommendedFreq_DERIVED $desired_operational_freq + + set_parameter_value DDR_PLLC0RecommendedPhase_DERIVED 0.0 + set_parameter_value DDR_PLLC1RecommendedPhase_DERIVED 1.0 + set_parameter_value DDR_PLLC2RecommendedPhase_DERIVED 2.0 + set_parameter_value DDR_PLLC3RecommendedPhase_DERIVED 3.0 + } + + for {set index 0} {${index} < 4} {incr index} { + set p_name "DDR_PLLC${index}ActualFreq" + set value [get_parameter_value $p_name] + if {$value < 0.0} { + send_message error "DDR PLL Output C${index} cannot have a negative clock frequency." + } + + set p_name "DDR_PLLC${index}ActualPhase" + set value [get_parameter_value $p_name] + if {$value < 0.0} { + send_message error "DDR PLL Output C${index} cannot have a negative clock phase shift." + } + } +} + + +###################### +##### Elaboration ##### +###################### + +proc elab {logical_view} { + # TODO: add RTL information for each + set device_family [get_parameter_value hps_device_family] + + elab_clocks_resets $device_family + + elab_MPU_EVENTS $device_family + elab_DEBUGAPB $device_family + elab_STM $device_family + elab_CTI $device_family + elab_TPIUFPGA $device_family + elab_GP $device_family + elab_BOOTFROMFPGA $device_family + + if {$logical_view == 0} { + elab_F2S $device_family + elab_LWH2F $device_family + elab_S2F $device_family + elab_F2SDRAM $device_family + + } + + elab_DMA $device_family + elab_INTERRUPTS $device_family $logical_view + + elab_emac_ptp $device_family + + elab_TEST $device_family + + # Handle Special Case EMAC signal... ptp_ref_clk + set emac0_pin_mux_param_name [format [PIN_MUX_PARAM_FORMAT] EMAC0] + set emac1_pin_mux_param_name [format [PIN_MUX_PARAM_FORMAT] EMAC1] + set emac0_pin_mux_value [get_parameter_value $emac0_pin_mux_param_name] + set emac1_pin_mux_value [get_parameter_value $emac1_pin_mux_param_name] + set emac0_pin_mux_allowed_ranges [get_parameter_property $emac0_pin_mux_param_name allowed_ranges] + set emac1_pin_mux_allowed_ranges [get_parameter_property $emac1_pin_mux_param_name allowed_ranges] + + set emac0_ptp_enabled [expr {[string compare $emac0_pin_mux_value [FPGA_MUX_VALUE]] == 0 && [lsearch $emac0_pin_mux_allowed_ranges [FPGA_MUX_VALUE]] != -1}] + set emac1_ptp_enabled [expr {[string compare $emac1_pin_mux_value [FPGA_MUX_VALUE]] == 0 && [lsearch $emac1_pin_mux_allowed_ranges [FPGA_MUX_VALUE]] != -1}] + + set emac0_io_enabled [expr {[string compare $emac0_pin_mux_value "HPS I/O Set 0"] == 0 && [lsearch $emac0_pin_mux_allowed_ranges "HPS I/O Set 0"] != -1}] + set emac1_io_enabled [expr {[string compare $emac1_pin_mux_value "HPS I/O Set 0"] == 0 && [lsearch $emac1_pin_mux_allowed_ranges "HPS I/O Set 0"] != -1}] + + set emac0_ptp [get_parameter_value EMAC0_PTP] + set emac1_ptp [get_parameter_value EMAC1_PTP] + + if {$emac0_ptp && $emac0_io_enabled} { + set emac0_ptp_enabled 1 + } + if {$emac1_ptp && $emac1_io_enabled} { + set emac1_ptp_enabled 1 + } + + if {$emac0_ptp_enabled || $emac1_ptp_enabled } { + set instance_name clocks_resets + fpga_interfaces::add_interface emac_ptp_ref_clock clock Input + fpga_interfaces::add_interface_port emac_ptp_ref_clock emac_ptp_ref_clk clk Input 1 $instance_name ptp_ref_clk + } + + # TODO: elab peripherals that mux signals to the fpga + elab_FPGA_Peripheral_Signals $device_family + + set_parameter_value DEVICE_FAMILY [get_parameter_value SYS_INFO_DEVICE_FAMILY] +} + +proc elab_MPU_EVENTS {device_family} { + if [is_enabled MPU_EVENTS_Enable] { + set instance_name mpu_events + set atom_name hps_interface_mpu_event_standby + set location [locations::get_fpga_location $instance_name $atom_name] + + set iface_name "h2f_mpu_events" + set z "h2f_mpu_" + fpga_interfaces::add_interface $iface_name conduit Input + fpga_interfaces::add_interface_port $iface_name ${z}eventi eventi Input 1 $instance_name eventi + fpga_interfaces::add_interface_port $iface_name ${z}evento evento Output 1 $instance_name evento + fpga_interfaces::add_interface_port $iface_name ${z}standbywfe standbywfe Output 2 $instance_name standbywfe + fpga_interfaces::add_interface_port $iface_name ${z}standbywfi standbywfi Output 2 $instance_name standbywfi + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } +} + +proc elab_DEBUGAPB {device_family} { + set instance_name debug_apb + set atom_name hps_interface_dbg_apb + set location [locations::get_fpga_location $instance_name $atom_name] + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + + if [is_enabled DEBUGAPB_Enable] { + set clock_name "h2f_debug_apb_clock" + fpga_interfaces::add_interface $clock_name clock Input + fpga_interfaces::add_interface_port $clock_name "h2f_dbg_apb_clk" clk Input 1 $instance_name P_CLK + + set reset_name "h2f_debug_apb_reset" + fpga_interfaces::add_interface $reset_name reset Output + fpga_interfaces::add_interface_port $reset_name "h2f_dbg_apb_rst_n" reset_n Output 1 $instance_name P_RESET_N + fpga_interfaces::set_interface_property $reset_name associatedClock $clock_name + + set iface_name "h2f_debug_apb" + set z "h2f_dbg_apb_" + fpga_interfaces::add_interface $iface_name apb master + fpga_interfaces::add_interface_port $iface_name "${z}PADDR" paddr Output 18 $instance_name P_ADDR + fpga_interfaces::add_interface_port $iface_name "${z}PADDR31" paddr31 Output 1 $instance_name P_ADDR_31 + fpga_interfaces::add_interface_port $iface_name "${z}PENABLE" penable Output 1 $instance_name P_ENABLE + fpga_interfaces::add_interface_port $iface_name "${z}PRDATA" prdata Input 32 $instance_name P_RDATA + fpga_interfaces::add_interface_port $iface_name "${z}PREADY" pready Input 1 $instance_name P_READY + fpga_interfaces::add_interface_port $iface_name "${z}PSEL" psel Output 1 $instance_name P_SEL + fpga_interfaces::add_interface_port $iface_name "${z}PSLVERR" pslverr Input 1 $instance_name P_SLV_ERR + fpga_interfaces::add_interface_port $iface_name "${z}PWDATA" pwdata Output 32 $instance_name P_WDATA + fpga_interfaces::add_interface_port $iface_name "${z}PWRITE" pwrite Output 1 $instance_name P_WRITE + fpga_interfaces::set_interface_property $iface_name associatedClock $clock_name + fpga_interfaces::set_interface_property $iface_name associatedReset $reset_name + + set iface_name "h2f_debug_apb_sideband" + set z "h2f_dbg_apb_" + fpga_interfaces::add_interface $iface_name conduit Input + fpga_interfaces::add_interface_port $iface_name "${z}PCLKEN" pclken Input 1 $instance_name P_CLK_EN + fpga_interfaces::add_interface_port $iface_name "${z}DBG_APB_DISABLE" dbg_apb_disable Input 1 $instance_name DBG_APB_DISABLE + fpga_interfaces::set_interface_property $iface_name associatedClock $clock_name + fpga_interfaces::set_interface_property $iface_name associatedReset $reset_name + + } else { + # Tie low when FPGA debug apb not being used + fpga_interfaces::set_instance_port_termination ${instance_name} "P_CLK_EN" 1 0 0:0 0 + fpga_interfaces::set_instance_port_termination ${instance_name} "DBG_APB_DISABLE" 1 0 0:0 0 + } +} + +proc elab_STM {device_family} { + if [is_enabled STM_Enable] { + set instance_name stm_event + set atom_name hps_interface_stm_event + set location [locations::get_fpga_location $instance_name $atom_name] + + fpga_interfaces::add_interface f2h_stm_hw_events conduit Input + fpga_interfaces::add_interface_port f2h_stm_hw_events f2h_stm_hwevents stm_hwevents Input 28 $instance_name stm_event + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } +} + +proc elab_CTI {device_family} { + set instance_name cross_trigger_interface + set atom_name hps_interface_cross_trigger + set location [locations::get_fpga_location $instance_name $atom_name] + + if [is_enabled CTI_Enable] { + set iface_name "h2f_cti" + set z "h2f_cti_" + fpga_interfaces::add_interface $iface_name conduit Input + fpga_interfaces::add_interface_port $iface_name ${z}trig_in trig_in Input 8 $instance_name trig_in + fpga_interfaces::add_interface_port $iface_name ${z}trig_in_ack trig_in_ack Output 8 $instance_name trig_inack + fpga_interfaces::add_interface_port $iface_name ${z}trig_out trig_out Output 8 $instance_name trig_out + fpga_interfaces::add_interface_port $iface_name ${z}trig_out_ack trig_out_ack Input 8 $instance_name trig_outack + # case:105603 hide asicctl output signal + # fpga_interfaces::add_interface_port $iface_name ${z}asicctl asicctl Output 8 $instance_name asicctl + fpga_interfaces::add_interface_port $iface_name ${z}fpga_clk_en fpga_clk_en Input 1 $instance_name clk_en + fpga_interfaces::set_interface_property $iface_name associatedClock h2f_cti_clock + fpga_interfaces::set_interface_property $iface_name associatedReset h2f_reset + + fpga_interfaces::add_interface h2f_cti_clock clock Input + fpga_interfaces::add_interface_port h2f_cti_clock h2f_cti_clk clk Input 1 $instance_name clk + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } +} + +proc elab_TPIUFPGA {device_family} { + set instance_name tpiu + set atom_name hps_interface_tpiu_trace + set location [locations::get_fpga_location $instance_name $atom_name] + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + + if { [string compare [get_parameter_value TPIUFPGA_Enable] "true" ] == 0 } { + set_parameter_property TPIUFPGA_alt enabled true + set iface_name "h2f_tpiu" + set z "h2f_tpiu_" + fpga_interfaces::add_interface $iface_name conduit input + fpga_interfaces::add_interface_port $iface_name ${z}clk_ctl clk_ctl Input 1 $instance_name traceclk_ctl + fpga_interfaces::add_interface_port $iface_name ${z}data data Output 32 $instance_name trace_data + + # case 245159 + if {[string compare [get_parameter_value TPIUFPGA_alt] "true" ] == 0} { + fpga_interfaces::add_interface_port $iface_name ${z}clkin clkin Input 1 $instance_name traceclkin + } else { + set iface_name "h2f_tpiu_clock_in" + fpga_interfaces::add_interface $iface_name clock input + fpga_interfaces::add_interface_port $iface_name ${z}clk_in clk Input 1 $instance_name traceclkin + } + + set clock_in_rate [get_parameter_value H2F_TPIU_CLOCK_IN_FREQ] + set clock_rate [expr {$clock_in_rate / 2}] + set iface_name "h2f_tpiu_clock" + fpga_interfaces::add_interface $iface_name clock output + fpga_interfaces::add_interface_port $iface_name ${z}clk clk Output 1 $instance_name traceclk + fpga_interfaces::set_interface_property $iface_name clockRateKnown true + fpga_interfaces::set_interface_property $iface_name clockRate $clock_rate + + add_clock_constraint_if_valid $clock_rate "*|fpga_interfaces|${instance_name}|traceclk" + + } else { + set_parameter_property TPIUFPGA_alt enabled false + fpga_interfaces::set_instance_port_termination ${instance_name} "traceclk_ctl" 1 1 0:0 1 + } +} + +proc elab_GP {device_family} { + if [is_enabled GP_Enable] { + set instance_name h2f_gp + set atom_name hps_interface_mpu_general_purpose + set location [locations::get_fpga_location $instance_name $atom_name] + + set iface_name "h2f_gp" + set z "h2f_gp_" + fpga_interfaces::add_interface $iface_name conduit Input + fpga_interfaces::add_interface_port $iface_name ${z}in gp_in Input 32 $instance_name gp_in + fpga_interfaces::add_interface_port $iface_name ${z}out gp_out Output 32 $instance_name gp_out + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } +} + +proc elab_BOOTFROMFPGA {device_family} { + set instance_name boot_from_fpga + set atom_name hps_interface_boot_from_fpga + set location [locations::get_fpga_location $instance_name $atom_name] + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + + set bsel_en [expr { [string compare [get_parameter_value BSEL_EN] "true" ] == 0 } ] + set bsel [get_parameter_value BSEL] + set csel_en [expr { [string compare [get_parameter_value CSEL_EN] "true" ] == 0 } ] + set csel [get_parameter_value CSEL] + set boot_from_fpga_enable [expr { [string compare [get_parameter_value BOOTFROMFPGA_Enable] "true" ] == 0 } ] + set ini_string [get_parameter_value quartus_ini_hps_ip_enable_bsel_csel] + set ini_enabled [expr { [string compare $ini_string "true" ] == 0 } ] + + # force disable bsel/csel by default + if {!$ini_enabled} { + set bsel_en 0 + set bsel 1 + set csel_en 0 + set csel 1 + } + + # when INI enabled, the controls should appear in the GUI + foreach parameter {BSEL BSEL_EN CSEL CSEL_EN} { + set_parameter_property $parameter visible $ini_string + set_parameter_property $parameter enabled $ini_string + } + + fpga_interfaces::set_instance_port_termination ${instance_name} "bsel" 3 0 2:0 $bsel + fpga_interfaces::set_instance_port_termination ${instance_name} "csel" 2 0 1:0 $csel + + if {$bsel_en} { + fpga_interfaces::set_instance_port_termination ${instance_name} "bsel_en" 1 0 0:0 1 + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "bsel_en" 1 0 0:0 0 + } + + if {$csel_en} { + fpga_interfaces::set_instance_port_termination ${instance_name} "csel_en" 1 0 0:0 1 + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "csel_en" 1 0 0:0 0 + } + + if {$boot_from_fpga_enable} { + set iface_name "f2h_boot_from_fpga" + set z "f2h_boot_from_fpga_" + fpga_interfaces::add_interface $iface_name conduit Input + fpga_interfaces::add_interface_port $iface_name "${z}ready" boot_from_fpga_ready Input 1 $instance_name boot_from_fpga_ready + fpga_interfaces::add_interface_port $iface_name "${z}on_failure" boot_from_fpga_on_failure Input 1 $instance_name boot_from_fpga_on_failure + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "boot_from_fpga_ready" 1 0 0:0 0 + fpga_interfaces::set_instance_port_termination ${instance_name} "boot_from_fpga_on_failure" 1 0 0:0 0 + } + + if {$boot_from_fpga_enable} { + send_message info "Ensure that valid Cortex A9 boot code is available to the HPS system when enabling boot from FPGA and h2f_axi_master interface is connecting to slave component start at address 0x0." + } + + if {$bsel_en && $bsel == 1 && !$boot_from_fpga_enable} { + send_message warning "Boot from FPGA ready must be enabled to correctly boot from the FPGA." + } +} + + +proc elab_F2S {device_family} { + set instance_name fpga2hps + set atom_name hps_interface_fpga2hps + set location [locations::get_fpga_location $instance_name $atom_name] + set termination_value 3 + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + + set addr_width 32 + set width [get_parameter_value F2S_Width] + if {$width > 0} { + set data_width 32 + set strb_width 4 + set termination_value 0 + if {$width == 2} { + set data_width 64 + set strb_width 8 + set termination_value 1 + } elseif {$width == 3} { + set data_width 128 + set strb_width 16 + set termination_value 2 + } + + set clock_name "f2h_axi_clock" + fpga_interfaces::add_interface $clock_name clock Input + fpga_interfaces::add_interface_port $clock_name f2h_axi_clk clk Input 1 $instance_name clk + + set iface_name "f2h_axi_slave" + set z "f2h_" + + fpga_interfaces::add_interface $iface_name axi slave + fpga_interfaces::set_interface_property $iface_name associatedClock $clock_name + fpga_interfaces::set_interface_property $iface_name associatedReset h2f_reset + fpga_interfaces::set_interface_property $iface_name readAcceptanceCapability 8 + fpga_interfaces::set_interface_property $iface_name writeAcceptanceCapability 8 + fpga_interfaces::set_interface_property $iface_name combinedAcceptanceCapability 16 + fpga_interfaces::set_interface_property $iface_name readDataReorderingDepth 16 + fpga_interfaces::set_interface_meta_property $iface_name data_width $data_width + fpga_interfaces::set_interface_meta_property $iface_name address_width $addr_width + + fpga_interfaces::add_interface_port $iface_name ${z}AWID awid Input 8 $instance_name awid + fpga_interfaces::add_interface_port $iface_name ${z}AWADDR awaddr Input $addr_width $instance_name awaddr + fpga_interfaces::add_interface_port $iface_name ${z}AWLEN awlen Input 4 $instance_name awlen + fpga_interfaces::add_interface_port $iface_name ${z}AWSIZE awsize Input 3 $instance_name awsize + fpga_interfaces::add_interface_port $iface_name ${z}AWBURST awburst Input 2 $instance_name awburst + fpga_interfaces::add_interface_port $iface_name ${z}AWLOCK awlock Input 2 $instance_name awlock + fpga_interfaces::add_interface_port $iface_name ${z}AWCACHE awcache Input 4 $instance_name awcache + fpga_interfaces::add_interface_port $iface_name ${z}AWPROT awprot Input 3 $instance_name awprot + fpga_interfaces::add_interface_port $iface_name ${z}AWVALID awvalid Input 1 $instance_name awvalid + fpga_interfaces::add_interface_port $iface_name ${z}AWREADY awready Output 1 $instance_name awready + fpga_interfaces::add_interface_port $iface_name ${z}AWUSER awuser Input 5 $instance_name awuser + + fpga_interfaces::add_interface_port $iface_name ${z}WID wid Input 8 $instance_name wid + fpga_interfaces::add_interface_port $iface_name ${z}WDATA wdata Input $data_width $instance_name wdata + fpga_interfaces::add_interface_port $iface_name ${z}WSTRB wstrb Input $strb_width $instance_name wstrb + fpga_interfaces::add_interface_port $iface_name ${z}WLAST wlast Input 1 $instance_name wlast + fpga_interfaces::add_interface_port $iface_name ${z}WVALID wvalid Input 1 $instance_name wvalid + fpga_interfaces::add_interface_port $iface_name ${z}WREADY wready Output 1 $instance_name wready + + fpga_interfaces::add_interface_port $iface_name ${z}BID bid Output 8 $instance_name bid + fpga_interfaces::add_interface_port $iface_name ${z}BRESP bresp Output 2 $instance_name bresp + fpga_interfaces::add_interface_port $iface_name ${z}BVALID bvalid Output 1 $instance_name bvalid + fpga_interfaces::add_interface_port $iface_name ${z}BREADY bready Input 1 $instance_name bready + + + fpga_interfaces::add_interface_port $iface_name ${z}ARID arid Input 8 $instance_name arid + fpga_interfaces::add_interface_port $iface_name ${z}ARADDR araddr Input $addr_width $instance_name araddr + fpga_interfaces::add_interface_port $iface_name ${z}ARLEN arlen Input 4 $instance_name arlen + fpga_interfaces::add_interface_port $iface_name ${z}ARSIZE arsize Input 3 $instance_name arsize + fpga_interfaces::add_interface_port $iface_name ${z}ARBURST arburst Input 2 $instance_name arburst + fpga_interfaces::add_interface_port $iface_name ${z}ARLOCK arlock Input 2 $instance_name arlock + fpga_interfaces::add_interface_port $iface_name ${z}ARCACHE arcache Input 4 $instance_name arcache + fpga_interfaces::add_interface_port $iface_name ${z}ARPROT arprot Input 3 $instance_name arprot + fpga_interfaces::add_interface_port $iface_name ${z}ARVALID arvalid Input 1 $instance_name arvalid + fpga_interfaces::add_interface_port $iface_name ${z}ARREADY arready Output 1 $instance_name arready + fpga_interfaces::add_interface_port $iface_name ${z}ARUSER aruser Input 5 $instance_name aruser + + fpga_interfaces::add_interface_port $iface_name ${z}RID rid Output 8 $instance_name rid + fpga_interfaces::add_interface_port $iface_name ${z}RDATA rdata Output $data_width $instance_name rdata + fpga_interfaces::add_interface_port $iface_name ${z}RRESP rresp Output 2 $instance_name rresp + fpga_interfaces::add_interface_port $iface_name ${z}RLAST rlast Output 1 $instance_name rlast + fpga_interfaces::add_interface_port $iface_name ${z}RVALID rvalid Output 1 $instance_name rvalid + fpga_interfaces::add_interface_port $iface_name ${z}RREADY rready Input 1 $instance_name rready + } + fpga_interfaces::set_instance_port_termination ${instance_name} "port_size_config" 2 0 1:0 $termination_value +} + +proc elab_S2F {device_family} { + set instance_name hps2fpga + set atom_name hps_interface_hps2fpga + set location [locations::get_fpga_location $instance_name $atom_name] + set termination_value 3 + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + + set addr_width 30 + set id_width 12 + set width [get_parameter_value S2F_Width] + if {$width > 0} { + set data_width 32 + set strb_width 4 + set termination_value 0 + + if {$width == 2} { + set data_width 64 + set strb_width 8 + set termination_value 1 + + } elseif {$width == 3} { + set data_width 128 + set strb_width 16 + set termination_value 2 + } + + set clock_name "h2f_axi_clock" + fpga_interfaces::add_interface $clock_name clock Input + fpga_interfaces::add_interface_port $clock_name h2f_axi_clk clk Input 1 $instance_name clk + + set iface_name "h2f_axi_master" + set z "h2f_" + + fpga_interfaces::add_interface $iface_name axi master + fpga_interfaces::set_interface_property $iface_name associatedClock $clock_name + fpga_interfaces::set_interface_property $iface_name associatedReset h2f_reset + fpga_interfaces::set_interface_property $iface_name readIssuingCapability 8 + fpga_interfaces::set_interface_property $iface_name writeIssuingCapability 8 + fpga_interfaces::set_interface_property $iface_name combinedIssuingCapability 16 + +# set svd_path [file join $::env(QUARTUS_ROOTDIR) .. ip altera hps altera_hps golden_ref_design_CMSIS_1_1_to_arm_v2.svd] +# send_message info "REMOVE! SVD_PATH = $svd_path" +# fpga_interfaces::set_interface_property $iface_name CMSIS_SVD_FILE $svd_path +# fpga_interfaces::set_interface_property $iface_name SVD_ADDRESS_GROUP hps +# fpga_interfaces::set_interface_property $iface_name SVD_ADDRESS_OFFSET [expr {0xC0000000}] + fpga_interfaces::set_interface_meta_property $iface_name data_width $data_width + fpga_interfaces::set_interface_meta_property $iface_name address_width $addr_width + fpga_interfaces::set_interface_meta_property $iface_name id_width $id_width + + fpga_interfaces::add_interface_port $iface_name ${z}AWID awid Output $id_width $instance_name awid + fpga_interfaces::add_interface_port $iface_name ${z}AWADDR awaddr Output $addr_width $instance_name awaddr + fpga_interfaces::add_interface_port $iface_name ${z}AWLEN awlen Output 4 $instance_name awlen + fpga_interfaces::add_interface_port $iface_name ${z}AWSIZE awsize Output 3 $instance_name awsize + fpga_interfaces::add_interface_port $iface_name ${z}AWBURST awburst Output 2 $instance_name awburst + fpga_interfaces::add_interface_port $iface_name ${z}AWLOCK awlock Output 2 $instance_name awlock + fpga_interfaces::add_interface_port $iface_name ${z}AWCACHE awcache Output 4 $instance_name awcache + fpga_interfaces::add_interface_port $iface_name ${z}AWPROT awprot Output 3 $instance_name awprot + fpga_interfaces::add_interface_port $iface_name ${z}AWVALID awvalid Output 1 $instance_name awvalid + fpga_interfaces::add_interface_port $iface_name ${z}AWREADY awready Input 1 $instance_name awready + + fpga_interfaces::add_interface_port $iface_name ${z}WID wid Output $id_width $instance_name wid + fpga_interfaces::add_interface_port $iface_name ${z}WDATA wdata Output $data_width $instance_name wdata + fpga_interfaces::add_interface_port $iface_name ${z}WSTRB wstrb Output $strb_width $instance_name wstrb + fpga_interfaces::add_interface_port $iface_name ${z}WLAST wlast Output 1 $instance_name wlast + fpga_interfaces::add_interface_port $iface_name ${z}WVALID wvalid Output 1 $instance_name wvalid + fpga_interfaces::add_interface_port $iface_name ${z}WREADY wready Input 1 $instance_name wready + + fpga_interfaces::add_interface_port $iface_name ${z}BID bid Input $id_width $instance_name bid + fpga_interfaces::add_interface_port $iface_name ${z}BRESP bresp Input 2 $instance_name bresp + fpga_interfaces::add_interface_port $iface_name ${z}BVALID bvalid Input 1 $instance_name bvalid + fpga_interfaces::add_interface_port $iface_name ${z}BREADY bready Output 1 $instance_name bready + + fpga_interfaces::add_interface_port $iface_name ${z}ARID arid Output $id_width $instance_name arid + fpga_interfaces::add_interface_port $iface_name ${z}ARADDR araddr Output $addr_width $instance_name araddr + fpga_interfaces::add_interface_port $iface_name ${z}ARLEN arlen Output 4 $instance_name arlen + fpga_interfaces::add_interface_port $iface_name ${z}ARSIZE arsize Output 3 $instance_name arsize + fpga_interfaces::add_interface_port $iface_name ${z}ARBURST arburst Output 2 $instance_name arburst + fpga_interfaces::add_interface_port $iface_name ${z}ARLOCK arlock Output 2 $instance_name arlock + fpga_interfaces::add_interface_port $iface_name ${z}ARCACHE arcache Output 4 $instance_name arcache + fpga_interfaces::add_interface_port $iface_name ${z}ARPROT arprot Output 3 $instance_name arprot + fpga_interfaces::add_interface_port $iface_name ${z}ARVALID arvalid Output 1 $instance_name arvalid + fpga_interfaces::add_interface_port $iface_name ${z}ARREADY arready Input 1 $instance_name arready + + fpga_interfaces::add_interface_port $iface_name ${z}RID rid Input $id_width $instance_name rid + fpga_interfaces::add_interface_port $iface_name ${z}RDATA rdata Input $data_width $instance_name rdata + fpga_interfaces::add_interface_port $iface_name ${z}RRESP rresp Input 2 $instance_name rresp + fpga_interfaces::add_interface_port $iface_name ${z}RLAST rlast Input 1 $instance_name rlast + fpga_interfaces::add_interface_port $iface_name ${z}RVALID rvalid Input 1 $instance_name rvalid + fpga_interfaces::add_interface_port $iface_name ${z}RREADY rready Output 1 $instance_name rready + + } + fpga_interfaces::set_instance_port_termination ${instance_name} "port_size_config" 2 0 1:0 $termination_value +} + +proc elab_LWH2F {device_family} { + set instance_name hps2fpga_light_weight + set atom_name hps_interface_hps2fpga_light_weight + set location [locations::get_fpga_location $instance_name $atom_name] + + if [is_enabled LWH2F_Enable] { + set addr_width 21 + set data_width 32 + set strb_width 4 + set id_width 12 + set clock_name "h2f_lw_axi_clock" + fpga_interfaces::add_interface $clock_name clock Input + fpga_interfaces::add_interface_port $clock_name h2f_lw_axi_clk clk Input 1 $instance_name clk + + set iface_name "h2f_lw_axi_master" + set z "h2f_lw_" + fpga_interfaces::add_interface $iface_name axi master +# fpga_interfaces::set_interface_property $iface_name SVD_ADDRESS_GROUP hps +# fpga_interfaces::set_interface_property $iface_name SVD_ADDRESS_OFFSET [expr {0xFC000000}] + fpga_interfaces::set_interface_property $iface_name associatedClock $clock_name + fpga_interfaces::set_interface_property $iface_name associatedReset h2f_reset + fpga_interfaces::set_interface_property $iface_name readIssuingCapability 8 + fpga_interfaces::set_interface_property $iface_name writeIssuingCapability 8 + fpga_interfaces::set_interface_property $iface_name combinedIssuingCapability 16 + fpga_interfaces::set_interface_meta_property $iface_name data_width $data_width + fpga_interfaces::set_interface_meta_property $iface_name address_width $addr_width + fpga_interfaces::set_interface_meta_property $iface_name id_width $id_width + + fpga_interfaces::add_interface_port $iface_name ${z}AWID awid Output $id_width $instance_name awid + fpga_interfaces::add_interface_port $iface_name ${z}AWADDR awaddr Output $addr_width $instance_name awaddr + fpga_interfaces::add_interface_port $iface_name ${z}AWLEN awlen Output 4 $instance_name awlen + fpga_interfaces::add_interface_port $iface_name ${z}AWSIZE awsize Output 3 $instance_name awsize + fpga_interfaces::add_interface_port $iface_name ${z}AWBURST awburst Output 2 $instance_name awburst + fpga_interfaces::add_interface_port $iface_name ${z}AWLOCK awlock Output 2 $instance_name awlock + fpga_interfaces::add_interface_port $iface_name ${z}AWCACHE awcache Output 4 $instance_name awcache + fpga_interfaces::add_interface_port $iface_name ${z}AWPROT awprot Output 3 $instance_name awprot + fpga_interfaces::add_interface_port $iface_name ${z}AWVALID awvalid Output 1 $instance_name awvalid + fpga_interfaces::add_interface_port $iface_name ${z}AWREADY awready Input 1 $instance_name awready + + fpga_interfaces::add_interface_port $iface_name ${z}WID wid Output $id_width $instance_name wid + fpga_interfaces::add_interface_port $iface_name ${z}WDATA wdata Output $data_width $instance_name wdata + fpga_interfaces::add_interface_port $iface_name ${z}WSTRB wstrb Output $strb_width $instance_name wstrb + fpga_interfaces::add_interface_port $iface_name ${z}WLAST wlast Output 1 $instance_name wlast + fpga_interfaces::add_interface_port $iface_name ${z}WVALID wvalid Output 1 $instance_name wvalid + fpga_interfaces::add_interface_port $iface_name ${z}WREADY wready Input 1 $instance_name wready + + fpga_interfaces::add_interface_port $iface_name ${z}BID bid Input $id_width $instance_name bid + fpga_interfaces::add_interface_port $iface_name ${z}BRESP bresp Input 2 $instance_name bresp + fpga_interfaces::add_interface_port $iface_name ${z}BVALID bvalid Input 1 $instance_name bvalid + fpga_interfaces::add_interface_port $iface_name ${z}BREADY bready Output 1 $instance_name bready + + fpga_interfaces::add_interface_port $iface_name ${z}ARID arid Output $id_width $instance_name arid + fpga_interfaces::add_interface_port $iface_name ${z}ARADDR araddr Output $addr_width $instance_name araddr + fpga_interfaces::add_interface_port $iface_name ${z}ARLEN arlen Output 4 $instance_name arlen + fpga_interfaces::add_interface_port $iface_name ${z}ARSIZE arsize Output 3 $instance_name arsize + fpga_interfaces::add_interface_port $iface_name ${z}ARBURST arburst Output 2 $instance_name arburst + fpga_interfaces::add_interface_port $iface_name ${z}ARLOCK arlock Output 2 $instance_name arlock + fpga_interfaces::add_interface_port $iface_name ${z}ARCACHE arcache Output 4 $instance_name arcache + fpga_interfaces::add_interface_port $iface_name ${z}ARPROT arprot Output 3 $instance_name arprot + fpga_interfaces::add_interface_port $iface_name ${z}ARVALID arvalid Output 1 $instance_name arvalid + fpga_interfaces::add_interface_port $iface_name ${z}ARREADY arready Input 1 $instance_name arready + + fpga_interfaces::add_interface_port $iface_name ${z}RID rid Input $id_width $instance_name rid + fpga_interfaces::add_interface_port $iface_name ${z}RDATA rdata Input $data_width $instance_name rdata + fpga_interfaces::add_interface_port $iface_name ${z}RRESP rresp Input 2 $instance_name rresp + fpga_interfaces::add_interface_port $iface_name ${z}RLAST rlast Input 1 $instance_name rlast + fpga_interfaces::add_interface_port $iface_name ${z}RVALID rvalid Input 1 $instance_name rvalid + fpga_interfaces::add_interface_port $iface_name ${z}RREADY rready Output 1 $instance_name rready + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } +} + +proc elab_F2SDRAM {device_family} { + f2sdram::init_registers + + set instance_name f2sdram + set atom_name hps_interface_fpga2sdram + set location [locations::get_fpga_location $instance_name $atom_name] + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + + set use_fast_sim_model [expr { [string compare [get_parameter_value quartus_ini_hps_ip_fast_f2sdram_sim_model] "true" ] == 0 }] + set bonding_out_signal [expr { [string compare [get_parameter_value BONDING_OUT_ENABLED] "true"] == 0} && {[string compare [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] "true"] == 0}] + #newly added + set width_list [get_parameter_value F2SDRAM_Width] + set rows [llength $width_list] + if {$rows > 0} { + # TODO: move outside of 'if' once registers are rendered + + + set type_list [get_parameter_value F2SDRAM_Type] + for {set i 0} {${i} < $rows} {incr i} { + set width [lindex $width_list $i] + set type_choice [lindex $type_list $i] + + set type "axi" + set type_id 0 + if { [string compare $type_choice [F2HSDRAM_AVM]] == 0 } { + set type "avalon" + set type_id 1 + } elseif { [string compare $type_choice [F2HSDRAM_AVM_WRITEONLY]] == 0 } { + set type "avalon" + set type_id 2 + } elseif { [string compare $type_choice [F2HSDRAM_AVM_READONLY]] == 0 } { + set type "avalon" + set type_id 3 + } + + set sim_is_synth [expr !$use_fast_sim_model] + + # To make sure bonding_out_signal only being added once even thought there are more than one f2sdram + if {$i == 0 } { + set bonding_out_signal [expr { [string compare [get_parameter_value BONDING_OUT_ENABLED] "true"] == 0} && {[string compare [get_parameter_value quartus_ini_hps_ip_f2sdram_bonding_out] "true"] == 0}] + } else { + set bonding_out_signal 0 + } + + f2sdram::add_port registers $i $type_id $width $instance_name $sim_is_synth $bonding_out_signal + } + f2sdram::add_sdc $use_fast_sim_model + fpga_interfaces::set_property IMPLEMENT_F2SDRAM_MEMORY_BACKED_SIM $use_fast_sim_model + + } + # write the registers out + f2sdram::render_registers registers $instance_name +} + +proc elab_clocks_resets {device_family} { + set instance_name clocks_resets + set atom_name hps_interface_clocks_resets + set location [locations::get_fpga_location $instance_name $atom_name] + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + + fpga_interfaces::add_interface h2f_reset reset Output + fpga_interfaces::add_interface_port h2f_reset h2f_rst_n reset_n Output 1 $instance_name + fpga_interfaces::set_interface_property h2f_reset synchronousEdges none + fpga_interfaces::set_interface_property h2f_reset associatedResetSinks none + + if [is_enabled S2FCLK_COLDRST_Enable] { + fpga_interfaces::add_interface h2f_cold_reset reset Output + fpga_interfaces::add_interface_port h2f_cold_reset h2f_cold_rst_n reset_n Output 1 $instance_name + fpga_interfaces::set_interface_property h2f_cold_reset synchronousEdges none + fpga_interfaces::set_interface_property h2f_cold_reset associatedResetSinks none + } + + if [is_enabled F2SCLK_COLDRST_Enable] { + fpga_interfaces::add_interface f2h_cold_reset_req reset Input + fpga_interfaces::add_interface_port f2h_cold_reset_req f2h_cold_rst_req_n reset_n Input 1 $instance_name + fpga_interfaces::set_interface_property f2h_cold_reset_req synchronousEdges none + fpga_interfaces::set_interface_property h2f_reset associatedResetSinks f2h_cold_reset_req + if [is_enabled S2FCLK_COLDRST_Enable] { + fpga_interfaces::set_interface_property h2f_cold_reset associatedResetSinks f2h_cold_reset_req + } + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_cold_rst_req_n" 1 1 0:0 1 + } + + if [is_enabled S2FCLK_PENDINGRST_Enable] { + fpga_interfaces::add_interface h2f_warm_reset_handshake conduit Output + fpga_interfaces::add_interface_port h2f_warm_reset_handshake h2f_pending_rst_req_n h2f_pending_rst_req_n Output 1 $instance_name + fpga_interfaces::add_interface_port h2f_warm_reset_handshake f2h_pending_rst_ack_n f2h_pending_rst_ack_n Input 1 $instance_name f2h_pending_rst_ack + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_pending_rst_ack" 1 1 0:0 1 + } + + if [is_enabled F2SCLK_DBGRST_Enable] { + fpga_interfaces::add_interface f2h_debug_reset_req reset Input + fpga_interfaces::add_interface_port f2h_debug_reset_req f2h_dbg_rst_req_n reset_n Input 1 $instance_name + fpga_interfaces::set_interface_property f2h_debug_reset_req synchronousEdges none + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_dbg_rst_req_n" 1 1 0:0 1 + } + + if [is_enabled F2SCLK_WARMRST_Enable] { + fpga_interfaces::add_interface f2h_warm_reset_req reset Input + fpga_interfaces::add_interface_port f2h_warm_reset_req f2h_warm_rst_req_n reset_n Input 1 $instance_name + fpga_interfaces::set_interface_property f2h_warm_reset_req synchronousEdges none + + if [is_enabled F2SCLK_COLDRST_Enable] { + fpga_interfaces::set_interface_property h2f_reset associatedResetSinks {f2h_warm_reset_req f2h_cold_reset_req} + } else { + fpga_interfaces::set_interface_property h2f_reset associatedResetSinks {f2h_warm_reset_req} + } + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_warm_rst_req_n" 1 1 0:0 1 + } + + if [is_enabled S2FCLK_USER0CLK_Enable] { + fpga_interfaces::add_interface h2f_user0_clock clock Output + fpga_interfaces::add_interface_port h2f_user0_clock h2f_user0_clk clk Output 1 $instance_name + set frequency [get_parameter_value S2FCLK_USER0CLK_FREQ] + set frequency [expr {$frequency * [MHZ_TO_HZ]}] + fpga_interfaces::set_interface_property h2f_user0_clock clockRateKnown true + fpga_interfaces::set_interface_property h2f_user0_clock clockRate $frequency + add_clock_constraint_if_valid $frequency "*|fpga_interfaces|${instance_name}|h2f_user0_clk" + } + + if [is_enabled S2FCLK_USER1CLK_Enable] { + fpga_interfaces::add_interface h2f_user1_clock clock Output + fpga_interfaces::add_interface_port h2f_user1_clock h2f_user1_clk clk Output 1 $instance_name + set frequency [get_parameter_value S2FCLK_USER1CLK_FREQ] + set frequency [expr {$frequency * [MHZ_TO_HZ]}] + fpga_interfaces::set_interface_property h2f_user1_clock clockRateKnown true + fpga_interfaces::set_interface_property h2f_user1_clock clockRate $frequency + add_clock_constraint_if_valid $frequency "*|fpga_interfaces|${instance_name}|h2f_user1_clk" + } + + set_parameter_property S2FCLK_USER2CLK enabled false + + if [is_enabled F2SCLK_PERIPHCLK_Enable] { + fpga_interfaces::add_interface f2h_periph_ref_clock clock Input + fpga_interfaces::add_interface_port f2h_periph_ref_clock f2h_periph_ref_clk clk Input 1 $instance_name + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_periph_ref_clk" 1 0 + } + + + if [is_enabled F2SCLK_SDRAMCLK_Enable] { + fpga_interfaces::add_interface f2h_sdram_ref_clock clock Input + fpga_interfaces::add_interface_port f2h_sdram_ref_clock f2h_sdram_ref_clk clk Input 1 $instance_name + } else { + fpga_interfaces::set_instance_port_termination ${instance_name} "f2h_sdram_ref_clk" 1 0 + } +} + +# Elaborate peripheral request interfaces for the fpga and +# the clk/reset per pair +# TODO: Make sure the DMA RTL contains the wrapper +proc elab_DMA {device_family} { + set instance_name dma + set atom_name hps_interface_dma + set location [locations::get_fpga_location $instance_name $atom_name] + + set can_message 0 + set available_list [get_parameter_value DMA_Enable] + if {[llength $available_list] > 0} { + set dma_used 0 + set periph_id 0 + foreach entry $available_list { + if {[string compare $entry "Yes" ] == 0} { + elab_DMA_entry $periph_id $instance_name + set dma_used 1 + if {$periph_id >= 4} { + set can_message 1 + } + } + incr periph_id + } + if $dma_used { + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } + if $can_message { + send_message info "DMA Peripheral Request Interfaces 4-7 may be consumed by an HPS CAN Controller" + } + } +} + +proc elab_DMA_make_conduit_name {periph_id} { + return "f2h_dma_req${periph_id}" +} + +proc elab_DMA_entry {periph_id instance_name} { + set iname [elab_DMA_make_conduit_name $periph_id] + set atom_signal_prefix "channel${periph_id}" + fpga_interfaces::add_interface $iname conduit Output + fpga_interfaces::add_interface_port $iname "${iname}_req" "dma_req" Input 1 $instance_name ${atom_signal_prefix}_req + fpga_interfaces::add_interface_port $iname "${iname}_single" "dma_single" Input 1 $instance_name ${atom_signal_prefix}_single + fpga_interfaces::add_interface_port $iname "${iname}_ack" "dma_ack" Output 1 $instance_name ${atom_signal_prefix}_xx_ack +} + + +proc elab_emac_ptp {device_family} { + # added for case http://fogbugz.altera.com/default.asp?307450 + for {set i 0} {$i < 2} {incr i} { + set emac_fpga_enabled false + set emac_io_enabled false + + set emac_pin_mux_value [get_parameter_value EMAC${i}_PinMuxing] + set emac_ptp [get_parameter_value EMAC${i}_PTP] + + if {[string compare $emac_pin_mux_value [FPGA_MUX_VALUE]] == 0} { + set emac_fpga_enabled true + } + if {[string compare $emac_pin_mux_value "HPS I/O Set 0"] == 0} { + set emac_io_enabled true + } + + set_parameter_property EMAC${i}_PTP enabled $emac_io_enabled + + if {$emac_io_enabled && $emac_ptp } { + set instance_name peripheral_emac${i} + set atom_name hps_interface_peripheral_emac + set wys_atom_name arriav_hps_interface_peripheral_emac + set location [locations::get_fpga_location $instance_name $atom_name] + + set iface_name "emac${i}" + + fpga_interfaces::add_interface $iface_name conduit input + fpga_interfaces::add_interface_port $iface_name emac${i}_ptp_aux_ts_trig_i ptp_aux_ts_trig_i Input 1 $instance_name ptp_aux_ts_trig_i + fpga_interfaces::add_interface_port $iface_name emac${i}_ptp_pps_o ptp_pps_o Output 1 $instance_name ptp_pps_o + + + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } + + } +} + +proc elab_INTERRUPTS {device_family logical_view} { + set instance_name interrupts + set atom_name hps_interface_interrupts + set location [locations::get_fpga_location $instance_name $atom_name] + set any_interrupt_enabled 0 + + ##### F2H ##### + if [is_enabled F2SINTERRUPT_Enable] { + set any_interrupt_enabled 1 + set iname "f2h_irq" + set pname "f2h_irq" + if { $logical_view == 0 } { + fpga_interfaces::add_interface "${iname}0" interrupt receiver + fpga_interfaces::add_interface_port "${iname}0" "${pname}_p0" irq Input 32 + fpga_interfaces::set_port_fragments "${iname}0" "${pname}_p0" "${instance_name}:irq(31:0)" + + fpga_interfaces::add_interface "${iname}1" interrupt receiver + fpga_interfaces::add_interface_port "${iname}1" "${pname}_p1" irq Input 32 + fpga_interfaces::set_port_fragments "${iname}1" "${pname}_p1" "${instance_name}:irq(63:32)" + } + } + + ##### H2F ##### + load_h2f_interrupt_table\ + functions_by_group width_by_function inverted_by_function + + set interrupt_groups [list_h2f_interrupt_groups] + foreach group $interrupt_groups { + set parameter "S2FINTERRUPT_${group}_Enable" + set enabled [is_enabled $parameter] + + if {!$enabled} { + continue + } + set any_interrupt_enabled 1 + + foreach function $functions_by_group($group) { + set width 1 + if {[info exists width_by_function($function)]} { + set width $width_by_function($function) + } + + set suffix "" + set inverted [info exists inverted_by_function($function)] + if {$inverted} { + set suffix "_n" + } + + #skip fpga_interfaces interrupt declaration for uart + if { ($logical_view == 1) && ( + $function == "uart0" || + $function == "uart1" )} { + continue + } + + set prefix "h2f_${function}_" + set interface "${prefix}interrupt" + set port "${prefix}irq" + + if {$width > 1} { ;# for buses, use index in interface/port names + for {set i 0} {$i < $width} {incr i} { + set indexed_interface "${interface}${i}" + set indexed_port "${port}${i}${suffix}" + fpga_interfaces::add_interface\ + $indexed_interface interrupt sender + fpga_interfaces::add_interface_port\ + $indexed_interface $indexed_port irq Output 1\ + $instance_name $indexed_port + } + } else { + set port "$port${suffix}" + fpga_interfaces::add_interface\ + $interface interrupt sender + fpga_interfaces::add_interface_port\ + $interface $port irq Output 1 $instance_name $port + } + } + } + + if {$any_interrupt_enabled} { + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } +} + +proc elab_TEST {device_family} { + set parameter_enabled [expr {[string compare [get_parameter_value TEST_Enable] "true" ] == 0}] + set ini_enabled [expr {[string compare [get_parameter_value quartus_ini_hps_ip_enable_test_interface] "true" ] == 0}] + + if {$parameter_enabled && $ini_enabled} { + set instance_name test_interface + set atom_name hps_interface_test + set location [locations::get_fpga_location $instance_name $atom_name] + + set iname "test" + set z "test_" + + set data [get_parameter_value test_iface_definition] + + fpga_interfaces::add_interface $iname conduit input + foreach {port width dir} $data { + fpga_interfaces::add_interface_port $iname "${z}${port}" $port $dir $width $instance_name $port + } + + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } +} + +# TODO: Mode usage data +proc elab_FPGA_Peripheral_Signals {device_family} { + # disable and hide all parameters related to fpga outputs + set emac0_fpga [get_parameter_value quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface] + set lssis_fpga [get_parameter_value quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces] + set all_fpga "true" + + set peripherals [list_peripheral_names] + foreach peripheral $peripherals { + if { [string compare $peripheral "SDIO" ] == 0 } { + continue + } + set visible false + if {[string compare $all_fpga "true" ] == 0} { + set visible true + } elseif {[string compare $emac0_fpga "true" ] == 0 && [string compare -nocase $peripheral "emac0"] == 0} { + set visible true + } elseif {[string compare $lssis_fpga "true" ] == 0 && [is_peripheral_low_speed_serial_interface $peripheral_name]} { + set visible true + } + if {[string compare -nocase $peripheral "emac0" ] == 0 || [string compare -nocase $peripheral "emac1" ] == 0} { + set visible true + } + set clocks [get_peripheral_fpga_output_clocks $peripheral] + foreach clock $clocks { + set parameter [form_peripheral_fpga_output_clock_frequency_parameter $clock] + set_parameter_property $parameter enabled false + set_parameter_property $parameter visible $visible + set clock_output_set($clock) 1 + } + + set clocks [get_peripheral_fpga_input_clocks $peripheral] + foreach clock $clocks { + set clock_input_set($clock) 1 + } + } + + array set fpga_ifaces [get_parameter_value DB_periph_ifaces] + array set iface_ports [get_parameter_value DB_iface_ports] + array set port_pins [get_parameter_value DB_port_pins] + foreach peripheral_name $fpga_ifaces([ORDERED_NAMES]) { ;# Peripherals + set pin_mux_param_name [format [PIN_MUX_PARAM_FORMAT] $peripheral_name] + set pin_mux_value [get_parameter_value $pin_mux_param_name] + set allowed_ranges [get_parameter_property $pin_mux_param_name allowed_ranges] + + if {[string compare $pin_mux_value [FPGA_MUX_VALUE]] == 0 && [lsearch $allowed_ranges [FPGA_MUX_VALUE]] != -1} { + funset peripheral + array set peripheral $fpga_ifaces($peripheral_name) + funset interfaces + array set interfaces $peripheral(interfaces) + + set instance_name [invent_peripheral_instance_name $peripheral_name] + + foreach interface_name $interfaces([ORDERED_NAMES]) { ;# Interfaces + funset interface + array set interface $interfaces($interface_name) + fpga_interfaces::add_interface $interface_name $interface(type) $interface(direction) + foreach {property_key property_value} $interface(properties) { + fpga_interfaces::set_interface_property $interface_name $property_key $property_value + } + #send_message info "NEA: peripheral_name $peripheral_name interface_name $interface_name " + + if { [string match "EMAC?" $peripheral_name] && [string match "*x_reset" $interface_name ] } { + fpga_interfaces::set_interface_property $interface_name associatedResetSinks none + } + + foreach {meta_property} [array names interface] { + # Meta Property if leading with an @ + if {[string compare [string index ${meta_property} 0] "@"] == 0} { + fpga_interfaces::set_interface_meta_property $interface_name [string replace ${meta_property} 0 0] $interface($meta_property) + } + } + + set once_per_clock 1 + funset ports + array set ports $iface_ports($interface_name) + foreach port_name $ports([ORDERED_NAMES]) { ;# Ports + funset port + array set port $ports($port_name) + + # TODO: determine width based on pins available via mode + set width [calculate_port_width $port_pins($port_name)] + + fpga_interfaces::add_interface_port $interface_name $port_name $port(role) $port(direction) $width $instance_name $port(atom_signal_name) + + set frequency 0 + # enable and show clock frequency parameters for outputs + if {[info exists clock_output_set($interface_name)]} { + set parameter [form_peripheral_fpga_output_clock_frequency_parameter $interface_name] + set_parameter_property $parameter enabled true + set frequency [get_parameter_value $parameter] + set frequency [expr {$frequency * [MHZ_TO_HZ]}] + fpga_interfaces::set_interface_property $interface_name clockRateKnown true + fpga_interfaces::set_interface_property $interface_name clockRate $frequency + } + + if {[string compare -nocase $interface(type) "clock"] == 0 && $once_per_clock} { + set once_per_clock 0 + add_clock_constraint_if_valid $frequency "*|fpga_interfaces|${instance_name}|[string tolower $port(atom_signal_name)]" + } + } + } + + # device-specific atom + set atom_name $peripheral(atom_name) + set wys_atom_name [generic_atom_to_wys_atom $device_family $atom_name] + set location [locations::get_fpga_location $peripheral_name $atom_name] + + fpga_interfaces::add_module_instance $instance_name $wys_atom_name $location + } + } +} + +# derives the WYS (device family-specific) atom name from the generic one +proc generic_atom_to_wys_atom {device_family atom_name} { + # TODO: base this on a table of data instead of on code + set result "" + if {[check_device_family_equivalence $device_family CYCLONEV]} { + set result "cyclonev_${atom_name}" + } elseif {[check_device_family_equivalence $device_family ARRIAV]} { + set result "arriav_${atom_name}" + } + return $result +} + +# invents an instance name from the peripheral's name +# assumes that the instance name is the same across a peripheral +proc invent_peripheral_instance_name {peripheral_name} { + return "peripheral_[string tolower $peripheral_name]" +} + +# TODO: do width calculation at db load time so we don't do it every elaboration! +# then make it accessible by a mode to width array for every peripheral with fpga periph interface +# TODO: also validate the static data, checking if the mode signals make sense aka only contiguous, 0-indexed mappings +proc calculate_port_width {pin_array_string} { + array set pins $pin_array_string + # TODO: -do we need to be able to support ports that don't start with pins at 0? + # -e.g. pins D0-D7 are indexed 0-7. if want D4-D7, can we do indexes 4-7? + # -for now, no! + set bit_index 0 + while {[info exists pins($bit_index)]} { + incr bit_index + } + return $bit_index +} + +proc pin_to_bank {pin} { + set io_index [string first "IO" $pin] + return [string range $pin 0 [expr {$io_index - 1}]] +} + +proc sort_pins {pins} { + set pin_suffixes [list] + foreach pin $pins { + set io_index [string first "IO" $pin] + set suffix_start [expr {$io_index + 2}] + set length [string length $pin] + set suffix [string range $pin $suffix_start [expr {$length - 1}]] + lappend pin_suffixes $suffix + } + set result [list] + set indices [lsort-indices -increasing -integer $pin_suffixes] + foreach index $indices { + lappend result [lindex $pins $index] + } + return $result +} + +proc set_peripheral_pin_muxing_description {peripheral_name pin_muxing_description mode_description} { + set parameter "[string toupper $peripheral_name]_PinMuxing" + set_display_item_property $parameter DESCRIPTION $pin_muxing_description + + set parameter "[string toupper $peripheral_name]_Mode" + set_display_item_property $parameter DESCRIPTION $mode_description +} + +# Expects same set of keys between both parameters +proc create_pin_muxing_description_table_html {signals_by_option_str pins_by_option_str} { + array set pins_by_option $pins_by_option_str + + set options [list] + foreach {option signals} $signals_by_option_str { + lappend options $option + + set pins $pins_by_option($option) + + foreach signal $signals pin $pins { + set key "${option}.${signal}" + set pins_by_option_and_signal($key) $pin + set signal_set($signal) 1 + } + } + + set sorted_signals [lsort -increasing -ascii [array names signal_set]] + set sorted_options [lsort -increasing -ascii $options] + + set ALIGN_CENTER {align="center"} + + set html "" ;# start of table, first row cell empty for signal column + foreach option $sorted_options { + set html "${html}" + } + set html "${html}" + foreach signal $sorted_signals { + set html "${html}" ;# new row w/ first cell (header) being the signal name + foreach option $sorted_options { + set key "${option}.${signal}" + if {[info exists pins_by_option_and_signal($key)]} { + set pin $pins_by_option_and_signal($key) + } else { + set pin "" + } + set html "${html}" + } + set html "${html}" + } + set html "${html}
${option}
${signal}${pin}
" + return $html +} + +proc create_mode_description_table_html {signals_by_mode_str} { + set modes [list] + + foreach {mode signals} $signals_by_mode_str { + lappend modes $mode + foreach signal $signals { + set key "${mode}.${signal}" + set membership_by_mode_and_signal($key) 1 + set signal_set($signal) 1 + } + } + + set sorted_signals [lsort -increasing -ascii [array names signal_set]] + set sorted_modes [lsort -increasing -ascii $modes] + + set ALIGN_CENTER {align="center"} + + set html "" ;# start of table, first row cell empty for signal column + foreach mode $sorted_modes { + set html "${html}" + } + set html "${html}" + foreach signal $sorted_signals { + set html "${html}" ;# new row w/ first cell (header) being the signal name + + foreach mode $sorted_modes { + set key "${mode}.${signal}" + if {[info exists membership_by_mode_and_signal($key)]} { + set member_marker "X" + } else { + set member_marker "" + } + set html "${html}" + } + set html "${html}" + } + set html "${html}
${mode}
${signal}${member_marker}
" + return $html +} + +proc get_quartus_edition {} { + set code { + set version "" + regexp {([a-zA-Z]+) (Edition|Version)$} $quartus(version) total version + return $version + } + set safe_code [string map {\n ; \t ""} $code] + set package_name "advanced_device" + set result [lindex [run_quartus_tcl_command "${package_name}:${safe_code}"] 0] + return $result +} + +proc is_soc_device {device} { + return [::pin_mux_db::verify_soc_device $device] +} + +proc set_peripheral_pin_muxing_descriptions {peripherals_ref} { + upvar 1 $peripherals_ref peripherals + + foreach peripheral_name [array names peripherals] { + set signals_by_option [list] + set pins_by_option [list] + + funset peripheral + array set peripheral $peripherals($peripheral_name) + funset pin_sets + array set pin_sets $peripheral(pin_sets) + + foreach pin_set_name [array names pin_sets] { + funset pin_set + array set pin_set $pin_sets($pin_set_name) + set signals $pin_set(signals) + lappend signals_by_option $pin_set_name $signals + set pins $pin_set(pins) + lappend pins_by_option $pin_set_name $pins + } + set signals_by_mode $peripheral(signals_by_mode) + + set table_html [create_pin_muxing_description_table_html $signals_by_option $pins_by_option] + set pin_muxing_description "" + + set table_html [create_mode_description_table_html $signals_by_mode] + set mode_description "Signal Membership Per Mode Usage Option:
${table_html}" + set_peripheral_pin_muxing_description $peripheral_name $pin_muxing_description $mode_description + } +} + +# Add pin muxing details to soc_io peripheral/signal data +add_storage_parameter pin_muxing {} +add_storage_parameter pin_muxing_check "" +proc ensure_pin_muxing_data {device_family} { + if {[check_device_family_equivalence $device_family [get_module_property SUPPORTED_DEVICE_FAMILIES]] == 0} { + return + } + + set device [get_device] + + if {![is_soc_device $device]} { + send_message error "Selected device '${device}' is not an SoC device. Please choose a valid SoC device to use the Hard Processor System." + return + } + + set device_configuration "${device_family}+${device}" + + set old_device_configuration [get_parameter_value pin_muxing_check] + if {$old_device_configuration == $device_configuration} { + return + } + + set load_rc [::pin_mux_db::load $device] + if {!$load_rc} { + send_message error "The pin information for the Hard Processor System could not be determined. Please check whether your edition of Quartus Prime supports the selected device." + return + } + locations::load $device + + load_peripherals_pin_muxing_model pin_muxing_peripherals + set_peripheral_pin_muxing_descriptions pin_muxing_peripherals + + set gpio_pins [::pin_mux_db::get_gpio_pins] + set loanio_pins [::pin_mux_db::get_loan_io_pins] + set customer_pin_names [::pin_mux_db::get_customer_pin_names] + set hlgpi_pins [::pin_mux_db::get_hlgpi_pins] + + set pin_muxing [list [array get pin_muxing_peripherals] $gpio_pins $loanio_pins $customer_pin_names $hlgpi_pins] + set_parameter_value pin_muxing $pin_muxing + set_parameter_value pin_muxing_check $device_configuration + + #### update pin_muxing data to use in java GUI #### + set pinmux_peripherals [array get pin_muxing_peripherals] + array set periph_key_value $pinmux_peripherals + + foreach {key value} [array get periph_key_value] { + set_parameter_value JAVA_${key}_DATA "$key \{$value\}" + } +} + +proc get_device {} { + + set device_name [get_parameter_value device_name] + return $device_name +} + +proc construct_hps_parameter_map {} { + set parameters [get_parameters] + foreach parameter $parameters { + set value [get_parameter_value $parameter] + set result($parameter) $value + } + return [array get result] +} + +################################################################################ +# Implements interface of util/pin_mux.tcl +# +namespace eval hps_ip_pin_muxing_model { +################################################################################ + proc get_peripherals_model {} { + set pin_muxing [get_parameter_value pin_muxing] + set peripherals [lindex $pin_muxing 0] + return $peripherals + } + proc get_emac0_fpga_ini {} { + return [is_enabled quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface] + } + proc get_lssis_fpga_ini {} { + return [is_enabled quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces] + } + proc get_all_fpga_ini {} { + return [is_enabled quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces] + } + proc get_peripheral_pin_muxing_selection {peripheral_name} { + set pin_muxing_param_name [format [PIN_MUX_PARAM_FORMAT] $peripheral_name] + set selection [get_parameter_value $pin_muxing_param_name] + return $selection + } + proc get_peripheral_mode_selection {peripheral_name} { + set mode_param_name [format [MODE_PARAM_FORMAT] $peripheral_name] + set selection [get_parameter_value $mode_param_name] + return $selection + } + proc get_gpio_pins {} { + set pin_muxing [get_parameter_value pin_muxing] + set pins [lindex $pin_muxing 1] + return $pins + } + proc get_loanio_pins {} { + set pin_muxing [get_parameter_value pin_muxing] + set pins [lindex $pin_muxing 2] + return $pins + } + proc get_customer_pin_names {} { + set pin_muxing [get_parameter_value pin_muxing] + set pins [lindex $pin_muxing 3] + return $pins + } + proc get_hlgpi_pins {} { + set pin_muxing [get_parameter_value pin_muxing] + set pins [lindex $pin_muxing 4] + return $pins + } + proc get_unsupported_peripheral {peripheral_name} { + set device_family [get_parameter_value hps_device_family] + set skip 0 + if {[check_device_family_equivalence $device_family ARRIAV]} { + foreach excluded_peripheral [ARRIAV_EXCLUDED_PERIPHRERALS] { + if {[string compare $excluded_peripheral $peripheral_name] == 0} { + set skip 1 + } + } + } + return $skip + } +} + + +## Add documentation links for user guide and/or release notes +add_documentation_link "User Guide" https://www.altera.com/products/soc/overview.html diff --git a/sys/ip/reset_source.v b/sys/ip/reset_source.v new file mode 100644 index 0000000..e9f0435 --- /dev/null +++ b/sys/ip/reset_source.v @@ -0,0 +1,48 @@ +// reset_source.v + +// This file was auto-generated as a prototype implementation of a module +// created in component editor. It ties off all outputs to ground and +// ignores all inputs. It needs to be edited to make it do something +// useful. +// +// This file will not be automatically regenerated. You should check it in +// to your version control system if you want to keep it. + +`timescale 1 ps / 1 ps +module reset_source +( + input wire clk, // clock.clk + input wire reset_hps, // reset_hps.reset + output wire reset_sys, // reset_sys.reset + output wire reset_cold, // reset_cold.reset + input wire cold_req, // reset_ctl.cold_req + output wire reset, // .reset + input wire reset_req, // .reset_req + input wire warm_req, // .warm_req + output wire reset_warm // reset_warm.reset +); + +assign reset_cold = cold_req; +assign reset_warm = warm_req; + +assign reset = reset_sys; +assign reset_sys = sys_reset | reset_hps | reset_req; + +reg sys_reset = 1; +always @(posedge clk) begin + integer timeout = 0; + reg reset_lock = 0; + + reset_lock <= reset_lock | cold_req; + + if(timeout < 2000000) begin + sys_reset <= 1; + timeout <= timeout + 1; + reset_lock <= 0; + end + else begin + sys_reset <= reset_lock; + end +end + +endmodule diff --git a/sys/ip/reset_source_hw.tcl b/sys/ip/reset_source_hw.tcl new file mode 100644 index 0000000..528bdf6 --- /dev/null +++ b/sys/ip/reset_source_hw.tcl @@ -0,0 +1,151 @@ +# TCL File Generated by Component Editor 16.1 +# Thu Apr 20 14:20:36 CST 2017 +# DO NOT MODIFY + + +# +# reset_source "reset_source" v1.0 +# Sorgelig 2017.04.20.14:20:36 +# +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module reset_source +# +set_module_property DESCRIPTION "" +set_module_property NAME reset_source +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR Sorgelig +set_module_property DISPLAY_NAME reset_source +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL reset_source +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true +add_fileset_file reset_source.v VERILOG PATH reset_source.v TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point reset_hps +# +add_interface reset_hps reset end +set_interface_property reset_hps associatedClock "" +set_interface_property reset_hps synchronousEdges NONE +set_interface_property reset_hps ENABLED true +set_interface_property reset_hps EXPORT_OF "" +set_interface_property reset_hps PORT_NAME_MAP "" +set_interface_property reset_hps CMSIS_SVD_VARIABLES "" +set_interface_property reset_hps SVD_ADDRESS_GROUP "" + +add_interface_port reset_hps reset_hps reset Input 1 + + +# +# connection point reset_sys +# +add_interface reset_sys reset start +set_interface_property reset_sys associatedClock "" +set_interface_property reset_sys associatedDirectReset "" +set_interface_property reset_sys associatedResetSinks "" +set_interface_property reset_sys synchronousEdges NONE +set_interface_property reset_sys ENABLED true +set_interface_property reset_sys EXPORT_OF "" +set_interface_property reset_sys PORT_NAME_MAP "" +set_interface_property reset_sys CMSIS_SVD_VARIABLES "" +set_interface_property reset_sys SVD_ADDRESS_GROUP "" + +add_interface_port reset_sys reset_sys reset Output 1 + + +# +# connection point reset_ctl +# +add_interface reset_ctl conduit end +set_interface_property reset_ctl associatedClock "" +set_interface_property reset_ctl associatedReset "" +set_interface_property reset_ctl ENABLED true +set_interface_property reset_ctl EXPORT_OF "" +set_interface_property reset_ctl PORT_NAME_MAP "" +set_interface_property reset_ctl CMSIS_SVD_VARIABLES "" +set_interface_property reset_ctl SVD_ADDRESS_GROUP "" + +add_interface_port reset_ctl cold_req cold_req Input 1 +add_interface_port reset_ctl reset reset Output 1 +add_interface_port reset_ctl reset_req reset_req Input 1 +add_interface_port reset_ctl warm_req warm_req Input 1 + + +# +# connection point reset_warm +# +add_interface reset_warm reset start +set_interface_property reset_warm associatedClock "" +set_interface_property reset_warm associatedDirectReset "" +set_interface_property reset_warm associatedResetSinks "" +set_interface_property reset_warm synchronousEdges NONE +set_interface_property reset_warm ENABLED true +set_interface_property reset_warm EXPORT_OF "" +set_interface_property reset_warm PORT_NAME_MAP "" +set_interface_property reset_warm CMSIS_SVD_VARIABLES "" +set_interface_property reset_warm SVD_ADDRESS_GROUP "" + +add_interface_port reset_warm reset_warm reset Output 1 + + +# +# connection point reset_cold +# +add_interface reset_cold reset start +set_interface_property reset_cold associatedClock "" +set_interface_property reset_cold associatedDirectReset "" +set_interface_property reset_cold associatedResetSinks "" +set_interface_property reset_cold synchronousEdges NONE +set_interface_property reset_cold ENABLED true +set_interface_property reset_cold EXPORT_OF "" +set_interface_property reset_cold PORT_NAME_MAP "" +set_interface_property reset_cold CMSIS_SVD_VARIABLES "" +set_interface_property reset_cold SVD_ADDRESS_GROUP "" + +add_interface_port reset_cold reset_cold reset Output 1 + diff --git a/sys/lpf48k.sv b/sys/lpf48k.sv new file mode 100644 index 0000000..2a32981 --- /dev/null +++ b/sys/lpf48k.sv @@ -0,0 +1,100 @@ +// low pass filter +// Revision 1.00 +// +// Copyright (c) 2008 Takayuki Hara. +// All rights reserved. +// +// Redistribution and use of this source code or any derivative works, are +// permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// 3. Redistributions may not be sold, nor may they be used in a commercial +// product or activity without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// +// LPF (cut off 48kHz at 3.58MHz) + +module lpf48k #(parameter MSB = 15) +( + input RESET, + input CLK, + input CE, + input ENABLE, + + input [MSB:0] IDATA, + output [MSB:0] ODATA +); + +wire [7:0] LPF_TAP_DATA[0:71] = +'{ + 8'h51, 8'h07, 8'h07, 8'h08, 8'h08, 8'h08, 8'h09, 8'h09, + 8'h09, 8'h0A, 8'h0A, 8'h0A, 8'h0A, 8'h0B, 8'h0B, 8'h0B, + 8'h0B, 8'h0C, 8'h0C, 8'h0C, 8'h0C, 8'h0D, 8'h0D, 8'h0D, + 8'h0D, 8'h0D, 8'h0D, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, + 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, + 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0D, 8'h0D, 8'h0D, + 8'h0D, 8'h0D, 8'h0D, 8'h0C, 8'h0C, 8'h0C, 8'h0C, 8'h0B, + 8'h0B, 8'h0B, 8'h0B, 8'h0A, 8'h0A, 8'h0A, 8'h0A, 8'h09, + 8'h09, 8'h09, 8'h08, 8'h08, 8'h08, 8'h07, 8'h07, 8'h51 +}; + +reg [7:0] FF_ADDR = 0; +reg [MSB+10:0] FF_INTEG = 0; +wire [MSB+8:0] W_DATA; +wire W_ADDR_END; + +assign W_ADDR_END = ((FF_ADDR == 71)); + +reg [MSB:0] OUT; + +assign ODATA = ENABLE ? OUT : IDATA; + +always @(posedge RESET or posedge CLK) begin + if (RESET) FF_ADDR <= 0; + else + begin + if (CE) begin + if (W_ADDR_END) FF_ADDR <= 0; + else FF_ADDR <= FF_ADDR + 1'd1; + end + end +end + +assign W_DATA = LPF_TAP_DATA[FF_ADDR] * IDATA; + +always @(posedge RESET or posedge CLK) begin + if (RESET) FF_INTEG <= 0; + else + begin + if (CE) begin + if (W_ADDR_END) FF_INTEG <= 0; + else FF_INTEG <= FF_INTEG + W_DATA; + end + end +end + +always @(posedge RESET or posedge CLK) begin + if (RESET) OUT <= 0; + else + begin + if (CE && W_ADDR_END) OUT <= FF_INTEG[MSB + 10:10]; + end +end + +endmodule diff --git a/sys/osd.v b/sys/osd.v new file mode 100644 index 0000000..87a2eff --- /dev/null +++ b/sys/osd.v @@ -0,0 +1,168 @@ +// A simple OSD implementation. Can be hooked up between a cores +// VGA output and the physical VGA pins + +module osd +( + input clk_sys, + + input io_osd, + input io_strobe, + input [7:0] io_din, + + input clk_video, + input [23:0] din, + output [23:0] dout, + input de +); + +parameter OSD_COLOR = 3'd4; +parameter OSD_X_OFFSET = 12'd0; +parameter OSD_Y_OFFSET = 12'd0; + +localparam OSD_WIDTH = 12'd256; +localparam OSD_HEIGHT = 12'd64; + +// this core supports only the display related OSD commands +// of the minimig v1 +reg osd_enable; +(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[4096]; // the OSD buffer itself + +reg highres = 0; + +// the OSD has its own SPI interface to the io controller +always@(posedge clk_sys) begin + reg [11:0] bcnt; + reg [7:0] cmd; + reg has_cmd; + reg old_strobe; + + old_strobe <= io_strobe; + + if(~io_osd) begin + bcnt <= 0; + has_cmd <= 0; + end else begin + if(~old_strobe & io_strobe) begin + if(!has_cmd) begin + has_cmd <= 1; + cmd <= io_din; + // command 0x40: OSDCMDENABLE, OSDCMDDISABLE + if(io_din[7:4] == 4'b0100) begin + osd_enable <= io_din[0]; + if(!io_din[0]) highres <= 0; + end + bcnt <= {io_din[3:0], 8'h00}; + if(io_din[7:3] == 5'b00101) highres <= 1; + end else begin + // command 0x20: OSDCMDWRITE + if(cmd[7:4] == 4'b0010) begin + osd_buffer[bcnt] <= io_din; + bcnt <= bcnt + 1'd1; + end + end + end + end +end + +reg ce_pix; +always @(negedge clk_video) begin + integer cnt = 0; + integer pixsz, pixcnt; + reg deD; + + cnt <= cnt + 1; + deD <= de; + + pixcnt <= pixcnt + 1; + if(pixcnt == pixsz) pixcnt <= 0; + ce_pix <= !pixcnt; + + if(~deD && de) cnt <= 0; + + if(deD && ~de) begin + pixsz <= (((cnt+1'b1) >> 9) > 1) ? (((cnt+1'b1) >> 9) - 1) : 0; + pixcnt <= 0; + end +end + +reg [23:0] h_cnt; +reg [21:0] v_cnt; +reg [21:0] dsp_width; +reg [21:0] dsp_height; +reg [7:0] osd_byte; +reg [21:0] osd_vcnt; +reg [21:0] fheight; + +wire [21:0] hrheight = (OSD_HEIGHT< {dsp_width, 2'b00}) begin + v_cnt <= 0; + dsp_height <= v_cnt; + + if(v_cnt<320) begin + multiscan <= 0; + fheight <= hrheight; + end + else if(v_cnt<640) begin + multiscan <= 1; + fheight <= hrheight << 1; + end + else if(v_cnt<960) begin + multiscan <= 2; + fheight <= hrheight + (hrheight<<1); + end + else begin + multiscan <= 3; + fheight <= hrheight << 2; + end + end + h_cnt <= 0; + + osd_div <= osd_div + 1'd1; + if(osd_div == multiscan) begin + osd_div <= 0; + osd_vcnt <= osd_vcnt + 1'd1; + end + if(v_osd_start == (v_cnt+1'b1)) {osd_div, osd_vcnt} <= 0; + end + + osd_byte <= osd_buffer[{osd_vcnt[6:3], osd_hcnt[7:0]}]; + end +end + +// area in which OSD is being displayed +wire [21:0] h_osd_start = ((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET; +wire [21:0] h_osd_end = h_osd_start + OSD_WIDTH; +wire [21:0] v_osd_start = ((dsp_height- fheight)>>1) + OSD_Y_OFFSET; +wire [21:0] v_osd_end = v_osd_start + fheight; + +wire [21:0] osd_hcnt = h_cnt[21:0] - h_osd_start + 1'd1; + +wire osd_de = osd_enable && + (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) && + (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); + +wire osd_pixel = osd_byte[osd_vcnt[2:0]]; + + +assign dout = !osd_de ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]}, + {osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]}, + {osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}}; + +endmodule diff --git a/sys/pattern_vg.v b/sys/pattern_vg.v new file mode 100644 index 0000000..6379278 --- /dev/null +++ b/sys/pattern_vg.v @@ -0,0 +1,120 @@ +module pattern_vg +#( + parameter B=8, // number of bits per channel + X_BITS=13, + Y_BITS=13, + FRACTIONAL_BITS = 12 +) + +( + input reset, clk_in, + input wire [X_BITS-1:0] x, + input wire [Y_BITS-1:0] y, + input wire vn_in, hn_in, dn_in, + input wire [B-1:0] r_in, g_in, b_in, + output reg vn_out, hn_out, den_out, + output reg [B-1:0] r_out, g_out, b_out, + input wire [X_BITS-1:0] total_active_pix, + input wire [Y_BITS-1:0] total_active_lines, + input wire [7:0] pattern, + input wire [B+FRACTIONAL_BITS-1:0] ramp_step +); + +reg [B+FRACTIONAL_BITS-1:0] ramp_values; // 12-bit fractional end for ramp values + + +//wire bar_0 = y<90; +wire bar_1 = y>=90 & y<180; +wire bar_2 = y>=180 & y<270; +wire bar_3 = y>=270 & y<360; +wire bar_4 = y>=360 & y<450; +wire bar_5 = y>=450 & y<540; +wire bar_6 = y>=540 & y<630; +wire bar_7 = y>=630 & y<720; + + +wire red_enable = bar_1 | bar_3 | bar_5 | bar_7; +wire green_enable = bar_2 | bar_3 | bar_6 | bar_7; +wire blue_enable = bar_4 | bar_5 | bar_6 | bar_7; + +always @(posedge clk_in) + begin + vn_out <= vn_in; + hn_out <= hn_in; + den_out <= dn_in; + if (reset) + ramp_values <= 0; + else if (pattern == 8'b0) // no pattern + begin + r_out <= r_in; + g_out <= g_in; + b_out <= b_in; + end + else if (pattern == 8'b1) // border + begin + if (dn_in && ((y == 12'b0) || (x == 12'b0) || (x == total_active_pix - 1) || (y == total_active_lines - 1))) + begin + r_out <= 8'hFF; + g_out <= 8'hFF; + b_out <= 8'hFF; + end + else // Double-border (OzOnE)... + if (dn_in && ((y == 12'b0+20) || (x == 12'b0+20) || (x == total_active_pix - 1 - 20) || (y == total_active_lines - 1 - 20))) + begin + r_out <= 8'hD0; + g_out <= 8'hB0; + b_out <= 8'hB0; + end + else + begin + r_out <= r_in; + g_out <= g_in; + b_out <= b_in; + end + end + else if (pattern == 8'd2) // moireX + begin + if ((dn_in) && x[0] == 1'b1) + begin + r_out <= 8'hFF; + g_out <= 8'hFF; + b_out <= 8'hFF; + end + else + begin + r_out <= 8'b0; + g_out <= 8'b0; + b_out <= 8'b0; + end + end + else if (pattern == 8'd3) // moireY + begin + if ((dn_in) && y[0] == 1'b1) + begin + r_out <= 8'hFF; + g_out <= 8'hFF; + b_out <= 8'hFF; + end + else + begin + r_out <= 8'b0; + g_out <= 8'b0; + b_out <= 8'b0; + end + end + else if (pattern == 8'd4) // Simple RAMP + begin + r_out <= (red_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00; + g_out <= (green_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00; + b_out <= (blue_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00; + + if ((x == total_active_pix - 1) && (dn_in)) + ramp_values <= 0; + else if ((x == 0) && (dn_in)) + ramp_values <= ramp_step; + else if (dn_in) + ramp_values <= ramp_values + ramp_step; + end +end + +endmodule diff --git a/sys/pll.qip b/sys/pll.qip new file mode 100644 index 0000000..a7b258d --- /dev/null +++ b/sys/pll.qip @@ -0,0 +1,337 @@ +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_VERSION "17.0" +set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] +set_global_assignment -entity "pll" -library "pll" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" +set_global_assignment -entity "pll" -library "pll" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -entity "pll" -library "pll" -name IP_QSYS_MODE "UNKNOWN" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_NAME "cGxs" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA==" +set_global_assignment -entity "pll" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_NAME "cGxsXzAwMDI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_VERSION "MTcuMA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjguMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTQ=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MjU=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTQuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTQ=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::NTA=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::NTAwMA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MTgwLjA=::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::NDM0MCBwcw==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTI2::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::NjMw::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MzAuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTI2::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MjEw::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::ODAuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MTI2::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::ODA=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MjEuMA==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjguMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTQuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::NTAwMCBwcw==::cGhhc2Vfc2hpZnQx" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::Nyw3LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwxMywxMiwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDI1LDI1LDQsNCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEsMjAsNDAwMCw3MDAuMCBNSHosMSxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=" + +set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"] +set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002.qip"] + +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "17.0" +set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_ENV "mwpim" diff --git a/sys/pll.v b/sys/pll.v new file mode 100644 index 0000000..25c6d94 --- /dev/null +++ b/sys/pll.v @@ -0,0 +1,255 @@ +// megafunction wizard: %Altera PLL v17.0% +// GENERATION: XML +// pll.v + +// Generated using ACDS version 17.0 598 + +`timescale 1 ps / 1 ps +module pll ( + input wire refclk, // refclk.clk + input wire rst, // reset.reset + output wire outclk_0, // outclk0.clk + output wire outclk_1, // outclk1.clk + output wire locked // locked.export + ); + + pll_0002 pll_inst ( + .refclk (refclk), // refclk.clk + .rst (rst), // reset.reset + .outclk_0 (outclk_0), // outclk0.clk + .outclk_1 (outclk_1), // outclk1.clk + .locked (locked) // locked.export + ); + +endmodule +// Retrieval info: +// +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// 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Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// IPFS_FILES : pll.vo +// RELATED_FILES: pll.v, pll_0002.v diff --git a/sys/pll/pll_0002.qip b/sys/pll/pll_0002.qip new file mode 100644 index 0000000..aec45eb --- /dev/null +++ b/sys/pll/pll_0002.qip @@ -0,0 +1,4 @@ +set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*" + +set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" diff --git a/sys/pll/pll_0002.v b/sys/pll/pll_0002.v new file mode 100644 index 0000000..a77cf7a --- /dev/null +++ b/sys/pll/pll_0002.v @@ -0,0 +1,90 @@ +`timescale 1ns/10ps +module pll_0002( + + // interface 'refclk' + input wire refclk, + + // interface 'reset' + input wire rst, + + // interface 'outclk0' + output wire outclk_0, + + // interface 'outclk1' + output wire outclk_1, + + // interface 'locked' + output wire locked +); + + altera_pll #( + .fractional_vco_multiplier("false"), + .reference_clock_frequency("50.0 MHz"), + .operation_mode("direct"), + .number_of_clocks(2), + .output_clock_frequency0("28.000000 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("14.000000 MHz"), + .phase_shift1("5000 ps"), + .duty_cycle1(50), + .output_clock_frequency2("0 MHz"), + .phase_shift2("0 ps"), + .duty_cycle2(50), + .output_clock_frequency3("0 MHz"), + .phase_shift3("0 ps"), + .duty_cycle3(50), + .output_clock_frequency4("0 MHz"), + .phase_shift4("0 ps"), + .duty_cycle4(50), + .output_clock_frequency5("0 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("0 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("0 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("General"), + .pll_subtype("General") + ) altera_pll_i ( + .rst (rst), + .outclk ({outclk_1, outclk_0}), + .locked (locked), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk) + ); +endmodule + diff --git a/sys/pll_hdmi.qip b/sys/pll_hdmi.qip new file mode 100644 index 0000000..2c1e916 --- /dev/null +++ b/sys/pll_hdmi.qip @@ -0,0 +1,337 @@ +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "17.0" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"] +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_QSYS_MODE "UNKNOWN" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_NAME "cGxsX2hkbWk=" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMA==" +set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_NAME "cGxsX2hkbWlfMDAwMg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTcuMA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NzQuMjU=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MzkwODQyMDE1Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NzQuMjUwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwzLDMsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMiwyMCw0MDAwLDQ0NS40OTk5OTkgTUh6LDM5MDg0MjAxNTMsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=" + +set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"] +set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"] +set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.qip"] + +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "17.0" +set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim" diff --git a/sys/pll_hdmi.v b/sys/pll_hdmi.v new file mode 100644 index 0000000..5ff1175 --- /dev/null +++ b/sys/pll_hdmi.v @@ -0,0 +1,252 @@ +// megafunction wizard: %Altera PLL v17.0% +// GENERATION: XML +// pll_hdmi.v + +// Generated using ACDS version 17.0 598 + +`timescale 1 ps / 1 ps +module pll_hdmi ( + input wire refclk, // refclk.clk + input wire rst, // reset.reset + output wire outclk_0 // outclk0.clk + ); + + pll_hdmi_0002 pll_hdmi_inst ( + .refclk (refclk), // refclk.clk + .rst (rst), // reset.reset + .outclk_0 (outclk_0), // outclk0.clk + .locked () // (terminated) + ); + +endmodule +// Retrieval info: +// +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// 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Retrieval info: +// Retrieval info: +// Retrieval info: +// IPFS_FILES : pll_hdmi.vo +// RELATED_FILES: pll_hdmi.v, pll_hdmi_0002.v diff --git a/sys/pll_hdmi/pll_hdmi_0002.qip b/sys/pll_hdmi/pll_hdmi_0002.qip new file mode 100644 index 0000000..fb8053d --- /dev/null +++ b/sys/pll_hdmi/pll_hdmi_0002.qip @@ -0,0 +1,4 @@ +set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*" diff --git a/sys/pll_hdmi/pll_hdmi_0002.v b/sys/pll_hdmi/pll_hdmi_0002.v new file mode 100644 index 0000000..6bea229 --- /dev/null +++ b/sys/pll_hdmi/pll_hdmi_0002.v @@ -0,0 +1,87 @@ +`timescale 1ns/10ps +module pll_hdmi_0002( + + // interface 'refclk' + input wire refclk, + + // interface 'reset' + input wire rst, + + // interface 'outclk0' + output wire outclk_0, + + // interface 'locked' + output wire locked +); + + altera_pll #( + .fractional_vco_multiplier("true"), + .reference_clock_frequency("50.0 MHz"), + .operation_mode("direct"), + .number_of_clocks(1), + .output_clock_frequency0("74.250000 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("0 MHz"), + .phase_shift1("0 ps"), + .duty_cycle1(50), + .output_clock_frequency2("0 MHz"), + .phase_shift2("0 ps"), + .duty_cycle2(50), + .output_clock_frequency3("0 MHz"), + .phase_shift3("0 ps"), + .duty_cycle3(50), + .output_clock_frequency4("0 MHz"), + .phase_shift4("0 ps"), + .duty_cycle4(50), + .output_clock_frequency5("0 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("0 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("0 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("General"), + .pll_subtype("General") + ) altera_pll_i ( + .rst (rst), + .outclk ({outclk_0}), + .locked (locked), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk) + ); +endmodule + diff --git a/sys/scandoubler.v b/sys/scandoubler.v new file mode 100644 index 0000000..f0728fc --- /dev/null +++ b/sys/scandoubler.v @@ -0,0 +1,186 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// Copyright (c) 2017 Sorgelig +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +// TODO: Delay vsync one line + +module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) +( + // system interface + input clk_sys, + input ce_pix, + output ce_pix_out, + + input hq2x, + + // shifter video interface + input hs_in, + input vs_in, + input hb_in, + input vb_in, + + input [DWIDTH:0] r_in, + input [DWIDTH:0] g_in, + input [DWIDTH:0] b_in, + input mono, + + // output interface + output reg hs_out, + output vs_out, + output hb_out, + output vb_out, + output [DWIDTH:0] r_out, + output [DWIDTH:0] g_out, + output [DWIDTH:0] b_out +); + + +localparam DWIDTH = HALF_DEPTH ? 3 : 7; + +assign vs_out = vs_in; +assign ce_pix_out = ce_x4; + +//Compensate picture shift after HQ2x +assign vb_out = vbo[2]; +assign hb_out = &hbo[5:4]; + +reg [7:0] pix_len = 0; +wire [7:0] pl = pix_len + 1'b1; + +reg ce_x1, ce_x4; +reg req_line_reset; +always @(negedge clk_sys) begin + reg old_ce; + reg [2:0] ce_cnt; + + reg [7:0] pixsz2, pixsz4 = 0; + + old_ce <= ce_pix; + if(~&pix_len) pix_len <= pix_len + 1'd1; + + ce_x4 <= 0; + ce_x1 <= 0; + + // use such odd comparison to place ce_x4 evenly if master clock isn't multiple 4. + if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin + ce_x4 <= 1; + end + + if(~old_ce & ce_pix) begin + pixsz2 <= {1'b0, pl[7:1]}; + pixsz4 <= {2'b00, pl[7:2]}; + ce_x1 <= 1; + ce_x4 <= 1; + pix_len <= 0; + req_line_reset <= 0; + + if(hb_in) req_line_reset <= 1; + end +end + +localparam AWIDTH = `BITS_TO_FIT(LENGTH); +Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x +( + .clk(clk_sys), + .ce_x4(ce_x4), + .inputpixel({b_d,g_d,r_d}), + .mono(mono), + .disable_hq2x(~hq2x), + .reset_frame(vs_in), + .reset_line(req_line_reset), + .read_y(sd_line), + .read_x(sd_h), + .outpixel({b_out,g_out,r_out}) +); + +reg [10:0] sd_h; +reg [1:0] sd_line; +reg [2:0] vbo; +reg [5:0] hbo; + +reg [DWIDTH:0] r_d; +reg [DWIDTH:0] g_d; +reg [DWIDTH:0] b_d; + + +always @(posedge clk_sys) begin + + reg [11:0] hs_max,hs_rise; + reg [10:0] hcnt; + reg [11:0] sd_hcnt; + reg [11:0] hde_start, hde_end; + + reg hs, hs2, vs, hb; + + if(ce_x1) begin + hs <= hs_in; + hb <= hb_in; + + r_d <= r_in; + g_d <= g_in; + b_d <= b_in; + + if(hb && !hb_in) begin + hde_start <= {hcnt,1'b0}; + vbo <= {vbo[1:0], vb_in}; + end + if(!hb && hb_in) hde_end <= {hcnt,1'b0}; + + // falling edge of hsync indicates start of line + if(hs && !hs_in) begin + hs_max <= {hcnt,1'b1}; + hcnt <= 0; + end else begin + hcnt <= hcnt + 1'd1; + end + + // save position of rising edge + if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; + + vs <= vs_in; + if(vs && ~vs_in) sd_line <= 0; + end + + if(ce_x4) begin + hs2 <= hs_in; + hbo[5:1] <= hbo[4:0]; + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 1'd1; + if(~&hbo) sd_h <= sd_h + 1'd1; + + if(hs2 && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 0; + + + //prepare to read in advance + if(sd_hcnt == (hde_start-2)) begin + sd_h <= 0; + sd_line <= sd_line + 1'd1; + end + + if(sd_hcnt == hde_start) hbo[0] <= 0; + if(sd_hcnt == hde_end) hbo[0] <= 1; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_out <= 0; + if(sd_hcnt == hs_rise) hs_out <= 1; + end +end + +endmodule diff --git a/sys/sdram.sv b/sys/sdram.sv new file mode 100644 index 0000000..7828cd8 --- /dev/null +++ b/sys/sdram.sv @@ -0,0 +1,262 @@ +// +// sdram.v +// +// Static RAM controller implementation using SDRAM MT48LC16M16A2 +// +// Copyright (c) 2015,2016 Sorgelig +// +// Some parts of SDRAM code used from project: +// http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// +// ------------------------------------------ +// +// v2.1 - Add universal 8/16 bit mode. +// + +module sdram +( + input init, // reset to initialize RAM + input clk, // clock ~100MHz + // + // SDRAM_* - signals to the MT48LC16M16 chip + inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus + output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus + output reg SDRAM_DQML, // two byte masks + output reg SDRAM_DQMH, // + output reg [1:0] SDRAM_BA, // two banks + output SDRAM_nCS, // a single chip select + output SDRAM_nWE, // write enable + output SDRAM_nRAS, // row address select + output SDRAM_nCAS, // columns address select + output SDRAM_CKE, // clock enable + // + input [1:0] wtbt, // 16bit mode: bit1 - write high byte, bit0 - write low byte, + // 8bit mode: 2'b00 - use addr[0] to decide which byte to write + // Ignored while reading. + // + input [24:0] addr, // 25 bit address for 8bit mode. addr[0] = 0 for 16bit mode for correct operations. + output [15:0] dout, // data output to cpu + input [15:0] din, // data input from cpu + input we, // cpu requests write + input rd, // cpu requests read + output reg ready // dout is valid. Ready to accept new read/write. +); + +assign SDRAM_nCS = command[3]; +assign SDRAM_nRAS = command[2]; +assign SDRAM_nCAS = command[1]; +assign SDRAM_nWE = command[0]; +assign SDRAM_CKE = cke; +assign dout = latched ? data_l : data_d; + +// no burst configured +localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8 +localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved +localparam CAS_LATENCY = 3'd2; // 2 for < 100MHz, 3 for >100MHz +localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed +localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write +localparam MODE = {3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; + +localparam sdram_startup_cycles= 14'd12100;// 100us, plus a little more, @ 100MHz +localparam cycles_per_refresh = 14'd780; // (64000*100)/8192-1 Calc'd as (64ms @ 100MHz)/8192 rose +localparam startup_refresh_max = 14'b11111111111111; + +// SDRAM commands +localparam CMD_INHIBIT = 4'b1111; +localparam CMD_NOP = 4'b0111; +localparam CMD_ACTIVE = 4'b0011; +localparam CMD_READ = 4'b0101; +localparam CMD_WRITE = 4'b0100; +localparam CMD_BURST_TERMINATE = 4'b0110; +localparam CMD_PRECHARGE = 4'b0010; +localparam CMD_AUTO_REFRESH = 4'b0001; +localparam CMD_LOAD_MODE = 4'b0000; + +reg [13:0] refresh_count = startup_refresh_max - sdram_startup_cycles; +reg [3:0] command = CMD_INHIBIT; +reg cke = 0; +reg [24:0] save_addr; + +reg latched; +reg [15:0] data; +wire[15:0] data_l = save_addr[0] ? {data[7:0], data[15:8]} : {data[15:8], data[7:0]}; +wire[15:0] data_d = save_addr[0] ? {SDRAM_DQ[7:0], SDRAM_DQ[15:8]} : {SDRAM_DQ[15:8], SDRAM_DQ[7:0]}; + +typedef enum +{ + STATE_STARTUP, + STATE_OPEN_1, STATE_OPEN_2, + STATE_WRITE, + STATE_READ, + STATE_IDLE, STATE_IDLE_1, STATE_IDLE_2, STATE_IDLE_3, + STATE_IDLE_4, STATE_IDLE_5, STATE_IDLE_6, STATE_IDLE_7 +} state_t; + +always @(posedge clk) begin + reg old_we, old_rd; + reg [CAS_LATENCY:0] data_ready_delay; + + reg [15:0] new_data; + reg [1:0] new_wtbt; + reg new_we; + reg new_rd; + reg save_we = 1; + + state_t state = STATE_STARTUP; + + command <= CMD_NOP; + refresh_count <= refresh_count+1'b1; + + data_ready_delay <= {1'b0, data_ready_delay[CAS_LATENCY:1]}; + + // make it ready 1T in advance + if(data_ready_delay[1]) {latched, ready} <= {1'b0, 1'b1}; + if(data_ready_delay[0]) {latched, data} <= {1'b1, SDRAM_DQ}; + + case(state) + STATE_STARTUP: begin + //------------------------------------------------------------------------ + //-- This is the initial startup state, where we wait for at least 100us + //-- before starting the start sequence + //-- + //-- The initialisation is sequence is + //-- * de-assert SDRAM_CKE + //-- * 100us wait, + //-- * assert SDRAM_CKE + //-- * wait at least one cycle, + //-- * PRECHARGE + //-- * wait 2 cycles + //-- * REFRESH, + //-- * tREF wait + //-- * REFRESH, + //-- * tREF wait + //-- * LOAD_MODE_REG + //-- * 2 cycles wait + //------------------------------------------------------------------------ + cke <= 1; + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + SDRAM_DQML <= 1; + SDRAM_DQMH <= 1; + SDRAM_A <= 0; + SDRAM_BA <= 0; + + // All the commands during the startup are NOPS, except these + if(refresh_count == startup_refresh_max-31) begin + // ensure all rows are closed + command <= CMD_PRECHARGE; + SDRAM_A[10] <= 1; // all banks + SDRAM_BA <= 2'b00; + end else if (refresh_count == startup_refresh_max-23) begin + // these refreshes need to be at least tREF (66ns) apart + command <= CMD_AUTO_REFRESH; + end else if (refresh_count == startup_refresh_max-15) + command <= CMD_AUTO_REFRESH; + else if (refresh_count == startup_refresh_max-7) begin + // Now load the mode register + command <= CMD_LOAD_MODE; + SDRAM_A <= MODE; + end + + //------------------------------------------------------ + //-- if startup is complete then go into idle mode, + //-- get prepared to accept a new command, and schedule + //-- the first refresh cycle + //------------------------------------------------------ + if(!refresh_count) begin + state <= STATE_IDLE; + ready <= 1; + refresh_count <= 0; + end + end + + STATE_IDLE_7: state <= STATE_IDLE_6; + STATE_IDLE_6: state <= STATE_IDLE_5; + STATE_IDLE_5: state <= STATE_IDLE_4; + STATE_IDLE_4: state <= STATE_IDLE_3; + STATE_IDLE_3: state <= STATE_IDLE_2; + STATE_IDLE_2: state <= STATE_IDLE_1; + STATE_IDLE_1: begin + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + state <= STATE_IDLE; + // mask possible refresh to reduce colliding. + if(refresh_count > cycles_per_refresh) begin + //------------------------------------------------------------------------ + //-- Start the refresh cycle. + //-- This tasks tRFC (66ns), so 6 idle cycles are needed @ 100MHz + //------------------------------------------------------------------------ + state <= STATE_IDLE_7; + command <= CMD_AUTO_REFRESH; + refresh_count <= refresh_count - cycles_per_refresh + 1'd1; + end + end + + STATE_IDLE: begin + // Priority is to issue a refresh if one is outstanding + if(refresh_count > (cycles_per_refresh<<1)) state <= STATE_IDLE_1; + else if(new_rd | new_we) begin + new_we <= 0; + new_rd <= 0; + save_addr<= addr; + save_we <= new_we; + state <= STATE_OPEN_1; + command <= CMD_ACTIVE; + SDRAM_A <= addr[13:1]; + SDRAM_BA <= addr[24:23]; + end + end + + // ACTIVE-to-READ or WRITE delay >20ns (-75) + STATE_OPEN_1: state <= STATE_OPEN_2; + STATE_OPEN_2: begin + SDRAM_A <= {4'b0010, save_addr[22:14]}; + SDRAM_DQML <= save_we & (new_wtbt ? ~new_wtbt[0] : save_addr[0]); + SDRAM_DQMH <= save_we & (new_wtbt ? ~new_wtbt[1] : ~save_addr[0]); + state <= save_we ? STATE_WRITE : STATE_READ; + end + + STATE_READ: begin + state <= STATE_IDLE_5; + command <= CMD_READ; + SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ; + + // Schedule reading the data values off the bus + data_ready_delay[CAS_LATENCY] <= 1; + end + + STATE_WRITE: begin + state <= STATE_IDLE_5; + command <= CMD_WRITE; + SDRAM_DQ <= new_wtbt ? new_data : {new_data[7:0], new_data[7:0]}; + ready <= 1; + end + endcase + + if(init) begin + state <= STATE_STARTUP; + refresh_count <= startup_refresh_max - sdram_startup_cycles; + end + + old_we <= we; + if(we & ~old_we) {ready, new_we, new_data, new_wtbt} <= {1'b0, 1'b1, din, wtbt}; + + old_rd <= rd; + if(rd & ~old_rd) begin + if(ready & ~save_we & (save_addr[24:1] == addr[24:1])) save_addr <= addr; + else {ready, new_rd} <= {1'b0, 1'b1}; + end +end + +endmodule diff --git a/sys/sigma_delta_dac.v b/sys/sigma_delta_dac.v new file mode 100644 index 0000000..d0d6be0 --- /dev/null +++ b/sys/sigma_delta_dac.v @@ -0,0 +1,33 @@ +// +// PWM DAC +// +// MSBI is the highest bit number. NOT amount of bits! +// +module sigma_delta_dac #(parameter MSBI=7, parameter INV=1'b1) +( + output reg DACout, //Average Output feeding analog lowpass + input [MSBI:0] DACin, //DAC input (excess 2**MSBI) + input CLK, + input RESET +); + +reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder +reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder +reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder +reg [MSBI+2:0] DeltaB; //B input of Delta Adder + +always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); +always @(*) DeltaAdder = DACin + DeltaB; +always @(*) SigmaAdder = DeltaAdder + SigmaLatch; + +always @(posedge CLK or posedge RESET) begin + if(RESET) begin + SigmaLatch <= 1'b1 << (MSBI+1); + DACout <= INV; + end else begin + SigmaLatch <= SigmaAdder; + DACout <= SigmaLatch[MSBI+2] ^ INV; + end +end + +endmodule diff --git a/sys/spdif.v b/sys/spdif.v new file mode 100644 index 0000000..d4e711e --- /dev/null +++ b/sys/spdif.v @@ -0,0 +1,392 @@ +//----------------------------------------------------------------- +// SPDIF Transmitter +// V0.1 +// Ultra-Embedded.com +// Copyright 2012 +// +// Email: admin@ultra-embedded.com +// +// License: GPL +// If you would like a version with a more permissive license for +// use in closed source commercial applications please contact me +// for details. +//----------------------------------------------------------------- +// +// This file is open source HDL; you can redistribute it and/or +// modify it under the terms of the GNU General Public License as +// published by the Free Software Foundation; either version 2 of +// the License, or (at your option) any later version. +// +// This file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public +// License along with this file; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 +// USA +//----------------------------------------------------------------- +// altera message_off 10762 +// altera message_off 10240 + +module spdif + +//----------------------------------------------------------------- +// Params +//----------------------------------------------------------------- +#( + parameter CLK_RATE = 50000000, + parameter AUDIO_RATE = 48000, + + // Generated params + parameter WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*128), + parameter ERROR_BASE = 10000, + parameter [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*128)) - (WHOLE_CYCLES * ERROR_BASE) +) + +//----------------------------------------------------------------- +// Ports +//----------------------------------------------------------------- +( + input clk_i, + input rst_i, + input half_rate, + + // Output + output spdif_o, + + // Audio interface (16-bit x 2 = RL) + input [15:0] audio_r, + input [15:0] audio_l, + output sample_req_o +); + +reg bit_clk_q; + +// Clock pulse generator +always @ (posedge rst_i or posedge clk_i) begin + reg [31:0] count_q; + reg [31:0] error_q; + reg ce; + + if (rst_i) begin + count_q <= 0; + error_q <= 0; + bit_clk_q <= 1; + ce <= 0; + end + else + begin + if(count_q == WHOLE_CYCLES-1) begin + if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin + error_q <= error_q + ERRORS_PER_BIT[31:0]; + count_q <= 0; + end else begin + error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE; + count_q <= count_q + 1; + end + end else if(count_q == WHOLE_CYCLES) begin + count_q <= 0; + end else begin + count_q <= count_q + 1; + end + + bit_clk_q <= 0; + if(!count_q) begin + ce <= ~ce; + if(~half_rate || ce) bit_clk_q <= 1; + end + end +end + +//----------------------------------------------------------------- +// Core SPDIF +//----------------------------------------------------------------- + +wire [31:0] sample_i = {audio_r, audio_l}; + +spdif_core +u_core +( + .clk_i(clk_i), + .rst_i(rst_i), + + .bit_out_en_i(bit_clk_q), + + .spdif_o(spdif_o), + + .sample_i(sample_i), + .sample_req_o(sample_req_o) +); + +endmodule + +module spdif_core +( + input clk_i, + input rst_i, + + // SPDIF bit output enable + // Single cycle pulse synchronous to clk_i which drives + // the output bit rate. + // For 44.1KHz, 44100×32×2×2 = 5,644,800Hz + // For 48KHz, 48000×32×2×2 = 6,144,000Hz + input bit_out_en_i, + + // Output + output spdif_o, + + // Audio interface (16-bit x 2 = RL) + input [31:0] sample_i, + output reg sample_req_o +); + +//----------------------------------------------------------------- +// Registers +//----------------------------------------------------------------- +reg [15:0] audio_sample_q; +reg [8:0] subframe_count_q; + +reg load_subframe_q; +reg [7:0] preamble_q; +wire [31:0] subframe_w; + +reg [5:0] bit_count_q; +reg bit_toggle_q; + +reg spdif_out_q; + +reg [5:0] parity_count_q; + +//----------------------------------------------------------------- +// Subframe Counter +//----------------------------------------------------------------- +always @ (posedge rst_i or posedge clk_i ) +begin + if (rst_i == 1'b1) + subframe_count_q <= 9'd0; + else if (load_subframe_q) + begin + // 192 frames (384 subframes) in an audio block + if (subframe_count_q == 9'd383) + subframe_count_q <= 9'd0; + else + subframe_count_q <= subframe_count_q + 9'd1; + end +end + +//----------------------------------------------------------------- +// Sample capture +//----------------------------------------------------------------- +reg [15:0] sample_buf_q; + +always @ (posedge rst_i or posedge clk_i ) +begin + if (rst_i == 1'b1) + begin + audio_sample_q <= 16'h0000; + sample_buf_q <= 16'h0000; + sample_req_o <= 1'b0; + end + else if (load_subframe_q) + begin + // Start of frame (first subframe)? + if (subframe_count_q[0] == 1'b0) + begin + // Use left sample + audio_sample_q <= sample_i[15:0]; + + // Store right sample + sample_buf_q <= sample_i[31:16]; + + // Request next sample + sample_req_o <= 1'b1; + end + else + begin + // Use right sample + audio_sample_q <= sample_buf_q; + + sample_req_o <= 1'b0; + end + end + else + sample_req_o <= 1'b0; +end + +// Timeslots 3 - 0 = Preamble +assign subframe_w[3:0] = 4'b0000; + +// Timeslots 7 - 4 = 24-bit audio LSB +assign subframe_w[7:4] = 4'b0000; + +// Timeslots 11 - 8 = 20-bit audio LSB +assign subframe_w[11:8] = 4'b0000; + +// Timeslots 27 - 12 = 16-bit audio +assign subframe_w[27:12] = audio_sample_q; + +// Timeslots 28 = Validity +assign subframe_w[28] = 1'b0; // Valid + +// Timeslots 29 = User bit +assign subframe_w[29] = 1'b0; + +// Timeslots 30 = Channel status bit +assign subframe_w[30] = 1'b0; + +// Timeslots 31 = Even Parity bit (31:4) +assign subframe_w[31] = 1'b0; + +//----------------------------------------------------------------- +// Preamble +//----------------------------------------------------------------- +localparam PREAMBLE_Z = 8'b00010111; +localparam PREAMBLE_Y = 8'b00100111; +localparam PREAMBLE_X = 8'b01000111; + +reg [7:0] preamble_r; + +always @ * +begin + // Start of audio block? + // Z(B) - Left channel + if (subframe_count_q == 9'd0) + preamble_r = PREAMBLE_Z; // Z(B) + // Right Channel? + else if (subframe_count_q[0] == 1'b1) + preamble_r = PREAMBLE_Y; // Y(W) + // Left Channel (but not start of block)? + else + preamble_r = PREAMBLE_X; // X(M) +end + +always @ (posedge rst_i or posedge clk_i ) +if (rst_i == 1'b1) + preamble_q <= 8'h00; +else if (load_subframe_q) + preamble_q <= preamble_r; + +//----------------------------------------------------------------- +// Parity Counter +//----------------------------------------------------------------- +always @ (posedge rst_i or posedge clk_i ) +begin + if (rst_i == 1'b1) + begin + parity_count_q <= 6'd0; + end + // Time to output a bit? + else if (bit_out_en_i) + begin + // Preamble bits? + if (bit_count_q < 6'd8) + begin + parity_count_q <= 6'd0; + end + // Normal timeslots + else if (bit_count_q < 6'd62) + begin + // On first pass through this timeslot, count number of high bits + if (bit_count_q[0] == 0 && subframe_w[bit_count_q / 2] == 1'b1) + parity_count_q <= parity_count_q + 6'd1; + end + end +end + +//----------------------------------------------------------------- +// Bit Counter +//----------------------------------------------------------------- +always @ (posedge rst_i or posedge clk_i) +begin + if (rst_i == 1'b1) + begin + bit_count_q <= 6'b0; + load_subframe_q <= 1'b1; + end + // Time to output a bit? + else if (bit_out_en_i) + begin + // 32 timeslots (x2 for double frequency) + if (bit_count_q == 6'd63) + begin + bit_count_q <= 6'd0; + load_subframe_q <= 1'b1; + end + else + begin + bit_count_q <= bit_count_q + 6'd1; + load_subframe_q <= 1'b0; + end + end + else + load_subframe_q <= 1'b0; +end + +//----------------------------------------------------------------- +// Bit half toggle +//----------------------------------------------------------------- +always @ (posedge rst_i or posedge clk_i) +if (rst_i == 1'b1) + bit_toggle_q <= 1'b0; +// Time to output a bit? +else if (bit_out_en_i) + bit_toggle_q <= ~bit_toggle_q; + +//----------------------------------------------------------------- +// Output bit (BMC encoded) +//----------------------------------------------------------------- +reg bit_r; + +always @ * +begin + bit_r = spdif_out_q; + + // Time to output a bit? + if (bit_out_en_i) + begin + // Preamble bits? + if (bit_count_q < 6'd8) + begin + bit_r = preamble_q[bit_count_q[2:0]]; + end + // Normal timeslots + else if (bit_count_q < 6'd62) + begin + if (subframe_w[bit_count_q / 2] == 1'b0) + begin + if (bit_toggle_q == 1'b0) + bit_r = ~spdif_out_q; + else + bit_r = spdif_out_q; + end + else + bit_r = ~spdif_out_q; + end + // Parity timeslot + else + begin + // Even number of high bits, make odd + if (parity_count_q[0] == 1'b0) + begin + if (bit_toggle_q == 1'b0) + bit_r = ~spdif_out_q; + else + bit_r = spdif_out_q; + end + else + bit_r = ~spdif_out_q; + end + end +end + +always @ (posedge rst_i or posedge clk_i ) +if (rst_i == 1'b1) + spdif_out_q <= 1'b0; +else + spdif_out_q <= bit_r; + +assign spdif_o = spdif_out_q; + +endmodule diff --git a/sys/sync_vg.v b/sys/sync_vg.v new file mode 100644 index 0000000..c54ba2f --- /dev/null +++ b/sys/sync_vg.v @@ -0,0 +1,123 @@ +module sync_vg +#( + parameter X_BITS=12, + Y_BITS=12 +) +( + input wire clk, + input wire reset, + input wire interlaced, + input wire [Y_BITS-1:0] v_total_0, + input wire [Y_BITS-1:0] v_fp_0, + input wire [Y_BITS-1:0] v_bp_0, + input wire [Y_BITS-1:0] v_sync_0, + input wire [Y_BITS-1:0] v_total_1, + input wire [Y_BITS-1:0] v_fp_1, + input wire [Y_BITS-1:0] v_bp_1, + input wire [Y_BITS-1:0] v_sync_1, + input wire [X_BITS-1:0] h_total, + input wire [X_BITS-1:0] h_fp, + input wire [X_BITS-1:0] h_bp, + input wire [X_BITS-1:0] h_sync, + input wire [X_BITS-1:0] hv_offset_0, + input wire [X_BITS-1:0] hv_offset_1, + output reg vs_out, + output reg hs_out, + output reg hde_out, + output reg vde_out, + output reg [Y_BITS:0] v_count_out, + output reg [X_BITS-1:0] h_count_out, + output reg [X_BITS-1:0] x_out, + output reg [Y_BITS:0] y_out, + output reg field_out, + output wire clk_out +); + +reg [X_BITS-1:0] h_count; +reg [Y_BITS-1:0] v_count; +reg field; +reg [Y_BITS-1:0] v_total; +reg [Y_BITS-1:0] v_fp; +reg [Y_BITS-1:0] v_bp; +reg [Y_BITS-1:0] v_sync; +reg [X_BITS-1:0] hv_offset; + +assign clk_out = !clk; + +/* horizontal counter */ +always @(posedge clk) + if (reset) + h_count <= 0; + else + if (h_count < h_total - 1) + h_count <= h_count + 1'd1; + else + h_count <= 0; + +/* vertical counter */ +always @(posedge clk) + if (reset) + v_count <= 0; + else + if (h_count == h_total - 1) + begin + if (v_count == v_total - 1) + v_count <= 0; + else + v_count <= v_count + 1'd1; + end + +/* field */ +always @(posedge clk) + if (reset) + begin + field <= 0; + v_total <= v_total_0; + v_fp <= interlaced ? v_fp_1 : v_fp_0; // In the interlaced mode this value must be inverted as v_fp_1 is still in field0 + v_bp <= v_bp_0; + v_sync <= v_sync_0; + hv_offset <= hv_offset_0; + end + else + if ((interlaced) && ((v_count == v_total - 1) && (h_count == h_total - 1))) + begin + field <= field + interlaced; + v_total <= field ? v_total_0 : v_total_1; + v_fp <= field ? v_fp_1 : v_fp_0; // This order is inverted as v_fp_1 is still in field0 + v_bp <= field ? v_bp_0 : v_bp_1; + v_sync <= field ? v_sync_0 : v_sync_1; + hv_offset <= field ? hv_offset_0 : hv_offset_1; + end + +always @(posedge clk) + if (reset) + { vs_out, hs_out, hde_out, vde_out, field_out } <= 4'b0; + else begin + hs_out <= ((h_count < h_sync)); + + hde_out <= (h_count >= h_sync + h_bp) && (h_count <= h_total - h_fp - 1); + vde_out <= (v_count >= v_sync + v_bp) && (v_count <= v_total - v_fp - 1); + + if ((v_count == 0) && (h_count == hv_offset)) + vs_out <= 1'b1; + else if ((v_count == v_sync) && (h_count == hv_offset)) + vs_out <= 1'b0; + + /* H_COUNT_OUT and V_COUNT_OUT */ + h_count_out <= h_count; + if (field) + v_count_out <= v_count + v_total_0; + else + v_count_out <= v_count; + + /* X and Y coords � for a backend pattern generator */ + x_out <= h_count - (h_sync + h_bp); + if (interlaced) + y_out <= { (v_count - (v_sync + v_bp)) , field }; + else + y_out <= { 1'b0, (v_count - (v_sync + v_bp)) }; + field_out <= field; + + end + +endmodule diff --git a/sys/sys.qip b/sys/sys.qip new file mode 100644 index 0000000..0697df2 --- /dev/null +++ b/sys/sys.qip @@ -0,0 +1,20 @@ +set_global_assignment -name VERILOG_FILE sys/sys_top.v +set_global_assignment -name SDC_FILE sys/sys_top.sdc +set_global_assignment -name QIP_FILE sys/pll.qip +set_global_assignment -name QIP_FILE sys/pll_hdmi.qip +set_global_assignment -name SYSTEMVERILOG_FILE sys/sdram.sv +set_global_assignment -name SYSTEMVERILOG_FILE sys/ddram.sv +set_global_assignment -name SYSTEMVERILOG_FILE sys/hq2x.sv +set_global_assignment -name VERILOG_FILE sys/scandoubler.v +set_global_assignment -name SYSTEMVERILOG_FILE sys/video_mixer.sv +set_global_assignment -name VERILOG_FILE sys/osd.v +set_global_assignment -name SYSTEMVERILOG_FILE sys/vga_out.sv +set_global_assignment -name VERILOG_FILE sys/sync_vg.v +set_global_assignment -name VERILOG_FILE sys/pattern_vg.v +set_global_assignment -name VERILOG_FILE sys/i2c.v +set_global_assignment -name VERILOG_FILE sys/i2s.v +set_global_assignment -name VERILOG_FILE sys/spdif.v +set_global_assignment -name VERILOG_FILE sys/sigma_delta_dac.v +set_global_assignment -name SYSTEMVERILOG_FILE sys/lpf48k.sv +set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_config.sv +set_global_assignment -name VERILOG_FILE sys/hps_io.v diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc new file mode 100644 index 0000000..c445ee5 --- /dev/null +++ b/sys/sys_top.sdc @@ -0,0 +1,27 @@ +create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50] +create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50] +create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50] +create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk] + +derive_pll_clocks + +#create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \ + -name SDRAM_CLK [get_ports {SDRAM_CLK}] + +derive_clock_uncertainty + +#set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]] +#set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]] + +#set_multicycle_path -from [get_clocks {SDRAM_CLK}] \ + -to [get_clocks {*|pll|pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}] \ + -setup 2 + +#set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +#set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] + +set_false_path -from * -to [get_ports {LED_*}] +set_false_path -from * -to [get_ports {BTN_*}] +set_false_path -from * -to [get_ports {VGA_*}] +set_false_path -from * -to [get_ports {AUDIO_L}] +set_false_path -from * -to [get_ports {AUDIO_R}] diff --git a/sys/sys_top.v b/sys/sys_top.v new file mode 100644 index 0000000..596d84c --- /dev/null +++ b/sys/sys_top.v @@ -0,0 +1,714 @@ +//============================================================================ +// +// DE10-nano HAL top module +// (c)2017 Sorgelig +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 of the License, or (at your option) +// any later version. +// +// This program is distributed in the hope that it will be useful, but WITHOUT +// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +// more details. +// +// You should have received a copy of the GNU General Public License along +// with this program; if not, write to the Free Software Foundation, Inc., +// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +// +//============================================================================ + +module sys_top +( + /////////// CLOCK ////////// + input FPGA_CLK1_50, + input FPGA_CLK2_50, + input FPGA_CLK3_50, + + //////////// VGA /////////// + output [5:0] VGA_R, + output [5:0] VGA_G, + output [5:0] VGA_B, + output VGA_HS, + output VGA_VS, + input VGA_EN, + + /////////// AUDIO ////////// + output AUDIO_L, + output AUDIO_R, + output AUDIO_SPDIF, + + //////////// HDMI ////////// + output HDMI_I2C_SCL, + inout HDMI_I2C_SDA, + + output HDMI_MCLK, + output HDMI_SCLK, + output HDMI_LRCLK, + output HDMI_I2S, + + output HDMI_TX_CLK, + output HDMI_TX_DE, + output [23:0] HDMI_TX_D, + output HDMI_TX_HS, + output HDMI_TX_VS, + + //////////// SDR /////////// + output [12:0] SDRAM_A, + inout [15:0] SDRAM_DQ, + output SDRAM_DQML, + output SDRAM_DQMH, + output SDRAM_nWE, + output SDRAM_nCAS, + output SDRAM_nRAS, + output SDRAM_nCS, + output [1:0] SDRAM_BA, + output SDRAM_CLK, + output SDRAM_CKE, + + //////////// I/O /////////// + output LED_USER, + output LED_HDD, + output LED_POWER, + input BTN_USER, + input BTN_OSD, + input BTN_RESET, + + //////////// SDIO /////////// + inout [3:0] SDIO_DAT, + inout SDIO_CMD, + output SDIO_CLK, + input SDIO_CD, + + ////////// MB KEY /////////// + input [1:0] KEY, + + ////////// MB LED /////////// + output [7:0] LED +); + + +assign SDIO_DAT[2:1] = 2'bZZ; + +////////////////////////// LEDs /////////////////////////////////////// + +wire led_p = led_power[1] ? ~led_power[0] : 1'b0; +wire led_d = led_disk[1] ? ~led_disk[0] : ~(led_disk[0] | gp_out[29]); +wire led_u = ~led_user; + +assign LED_POWER = led_p ? 1'bZ : 1'b0; +assign LED_HDD = led_d ? 1'bZ : 1'b0; +assign LED_USER = led_u ? 1'bZ : 1'b0; + +//LEDs on main board +assign LED = {3'b000, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u}; + + +////////////////////////// Buttons /////////////////////////////////// +reg btn_user, btn_osd; +always @(posedge FPGA_CLK2_50) begin + integer div; + reg [7:0] deb_user; + reg [7:0] deb_osd; + + div <= div + 1'b1; + if(div > 100000) div <= 0; + + if(!div) begin + deb_user <= {deb_user[6:0], ~(BTN_USER & KEY[1])}; + if(&deb_user) btn_user <= 1; + if(!deb_user) btn_user <= 0; + + deb_osd <= {deb_osd[6:0], ~(BTN_OSD & KEY[0])}; + if(&deb_osd) btn_osd <= 1; + if(!deb_osd) btn_osd <= 0; + end +end + +reg btn_reset = 1; +always @(posedge FPGA_CLK2_50) btn_reset <= BTN_RESET; + + +///////////////////////// HPS I/O ///////////////////////////////////// + +// gp_in[31] = 0 - quick flag that FPGA is initialized (HPS reads 1 when FPGA is not in user mode) +// used to avoid lockups while JTAG loading +wire [31:0] gp_in = {1'b0, btn_user, btn_osd, 9'd0, io_ver, io_ack, io_wide, io_dout}; +wire [31:0] gp_out; + +wire [1:0] io_ver = 1; // 0 - standard MiST I/O (for quick porting of complex MiST cores). 1 - optimized HPS I/O. 2,3 - reserved for future. +wire io_wait; +wire io_wide; +wire [15:0] io_dout; +wire [15:0] io_din = gp_outr[15:0]; +wire io_clk = gp_outr[17]; +wire io_fpga = gp_outr[18]; +wire io_osd = gp_outr[19]; +wire io_uio = gp_outr[20]; +//wire io_sdd = gp_outr[21]; // used only in ST core + +reg io_ack; +reg rack; +wire io_strobe = ~rack & io_clk; + +always @(posedge clk_sys) begin + if(~io_wait | io_strobe) begin + rack <= io_clk; + io_ack <= rack; + end +end + +reg [31:0] gp_outr; +always @(posedge clk_sys) begin + reg [31:0] gp_outd; + gp_outr <= gp_outd; + gp_outd <= gp_out; +end + +wire [7:0] core_type = 'hA4; // A4 - generic core. + +// HPS will not communicate to core if magic is different +wire [31:0] core_magic = {24'h5CA623, core_type}; + +cyclonev_hps_interface_mpu_general_purpose h2f_gp +( + .gp_in({~gp_out[31] ? core_magic : gp_in}), + .gp_out(gp_out) +); + + +reg [15:0] cfg; + +reg cfg_ready = 0; +wire audio_96k = cfg[6]; +wire ypbpr_en = cfg[5]; +wire csync = cfg[3]; +`ifndef LITE +wire vga_scaler= cfg[2]; +`endif + +always@(posedge clk_sys) begin + reg [7:0] cmd; + reg has_cmd; + reg old_strobe; + + old_strobe <= io_strobe; + + if(~io_uio) has_cmd <= 0; + else + if(~old_strobe & io_strobe) begin + if(!has_cmd) begin + has_cmd <= 1; + cmd <= io_din[7:0]; + end + else + if(cmd == 1) begin + cfg <= io_din; + cfg_ready <= 1; + end + end +end + + +/////////////////////////// RESET /////////////////////////////////// + +reg reset_req = 0; +always @(posedge FPGA_CLK2_50) begin + reg [1:0] resetd, resetd2; + reg old_reset; + + //latch the reset + old_reset <= reset; + if(~old_reset & reset) reset_req <= 1; + + //special combination to set/clear the reset + //preventing of accidental reset control + if(resetd==1) reset_req <= 1; + if(resetd==2 && resetd2==0) reset_req <= 0; + + resetd <= gp_out[31:30]; + resetd2 <= resetd; +end + +// 100MHz +wire ctl_clk; + +///////////////////////// VIP version /////////////////////////////// + +`ifndef LITE + +wire reset; +vip vip +( + //Reset/Clock + .reset_reset_req(reset_req), + .reset_reset(reset), + + //DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button. + .reset_cold_req(~btn_reset), + .reset_warm_req(0), + + //control + .ctl_address(ctl_address), + .ctl_write(ctl_write), + .ctl_writedata(ctl_writedata), + .ctl_waitrequest(ctl_waitrequest), + .ctl_clock(ctl_clk), + .ctl_reset(ctl_reset), + + //64-bit DDR3 RAM access + .ramclk1_clk(ram_clk), + .ram1_address(ram_address), + .ram1_burstcount(ram_burstcount), + .ram1_waitrequest(ram_waitrequest), + .ram1_readdata(ram_readdata), + .ram1_readdatavalid(ram_readdatavalid), + .ram1_read(ram_read), + .ram1_writedata(ram_writedata), + .ram1_byteenable(ram_byteenable), + .ram1_write(ram_write), + + //Spare 64-bit DDR3 RAM access + //currently unused + //can combine with ram1 to make a wider RAM bus (although will increase the latency) + .ramclk2_clk(0), + .ram2_address(0), + .ram2_burstcount(0), + .ram2_waitrequest(), + .ram2_readdata(), + .ram2_readdatavalid(), + .ram2_read(0), + .ram2_writedata(0), + .ram2_byteenable(0), + .ram2_write(0), + + //Video input + .in_vid_clk(clk_vid), + .in_vid_data({r_out, g_out, b_out}), + .in_vid_de(de), + .in_vid_v_sync(vs), + .in_vid_h_sync(hs), + .in_vid_datavalid(ce_pix), + .in_vid_locked(1), + .in_vid_f(0), + .in_vid_color_encoding(0), + .in_vid_bit_width(0), + + //HDMI output + .hdmi_vid_clk(~HDMI_TX_CLK), + .hdmi_vid_data(hdmi_data), + .hdmi_vid_datavalid(HDMI_TX_DE), + .hdmi_vid_v_sync(HDMI_TX_VS), + .hdmi_vid_h_sync(HDMI_TX_HS) +); + +wire [8:0] ctl_address; +wire ctl_write; +wire [31:0] ctl_writedata; +wire ctl_waitrequest; +wire ctl_reset; +wire [7:0] ARX, ARY; + +vip_config vip_config +( + .clk(ctl_clk), + .reset(ctl_reset), + + .ARX(ARX), + .ARY(ARY), + + .address(ctl_address), + .write(ctl_write), + .writedata(ctl_writedata), + .waitrequest(ctl_waitrequest) +); +`endif + + +///////////////////////// Lite version //////////////////////////////// + +`ifdef LITE + +wire INTERLACED = 0; +wire [11:0] V_TOTAL_0 = 750; +wire [11:0] V_FP_0 = 5; +wire [11:0] V_BP_0 = 20; +wire [11:0] V_SYNC_0 = 5; +wire [11:0] V_TOTAL_1 = 0; +wire [11:0] V_FP_1 = 0; +wire [11:0] V_BP_1 = 0; +wire [11:0] V_SYNC_1 = 0; +wire [11:0] H_TOTAL = 1650; +wire [11:0] H_FP = 110; +wire [11:0] H_BP = 220; +wire [11:0] H_SYNC = 40; +wire [11:0] HV_OFFSET_0 = 0; +wire [11:0] HV_OFFSET_1 = 0; + +wire [11:0] x; +wire [12:0] y; + +sync_vg #(.X_BITS(12), .Y_BITS(12)) sync_vg +( + .clk(HDMI_TX_CLK), + .reset(reset), + .interlaced(INTERLACED), + .clk_out(), // inverted output clock - unconnected + .v_total_0(V_TOTAL_0), + .v_fp_0(V_FP_0), + .v_bp_0(V_BP_0), + .v_sync_0(V_SYNC_0), + .v_total_1(V_TOTAL_1), + .v_fp_1(V_FP_1), + .v_bp_1(V_BP_1), + .v_sync_1(V_SYNC_1), + .h_total(H_TOTAL), + .h_fp(H_FP), + .h_bp(H_BP), + .h_sync(H_SYNC), + .hv_offset_0(HV_OFFSET_0), + .hv_offset_1(HV_OFFSET_1), + .vde_out(vde), + .hde_out(hde), + .vs_out(vs_hdmi), + .v_count_out(), + .h_count_out(), + .x_out(x), + .y_out(y), + .hs_out(hs_hdmi), + .field_out(field) +); + +wire vde, hde; +wire vs_hdmi; +wire hs_hdmi; +wire field; + +pattern_vg +#( + .B(8), // Bits per channel + .X_BITS(12), + .Y_BITS(12), + .FRACTIONAL_BITS(12) // Number of fractional bits for ramp pattern +) +pattern_vg +( + .reset(reset), + .clk_in(HDMI_TX_CLK), + .x(x), + .y(y[11:0]), + .vn_in(vs_hdmi), + .hn_in(hs_hdmi), + .dn_in(vde & hde), + .r_in(0), + .g_in(0), + .b_in(0), + .vn_out(HDMI_TX_VS), + .hn_out(HDMI_TX_HS), + .den_out(HDMI_TX_DE), + .r_out(hdmi_data[23:16]), + .g_out(hdmi_data[15:8]), + .b_out(hdmi_data[7:0]), + .total_active_pix(H_TOTAL - (H_FP + H_BP + H_SYNC)), + .total_active_lines(INTERLACED ? (V_TOTAL_0 - (V_FP_0 + V_BP_0 + V_SYNC_0)) + (V_TOTAL_1 - (V_FP_1 + V_BP_1 + V_SYNC_1)) : (V_TOTAL_0 - (V_FP_0 + V_BP_0 + V_SYNC_0))), // originally: 13'd480 + .pattern(4), + .ramp_step(20'h0333) +); + +wire reset; +sysmem_lite sysmem +( + //Reset/Clock + .reset_reset_req(reset_req), + .reset_reset(reset), + .ctl_clock(ctl_clk), + + //DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button. + .reset_cold_req(~btn_reset), + .reset_warm_req(0), + + //64-bit DDR3 RAM access + .ramclk1_clk(ram_clk), + .ram1_address(ram_address), + .ram1_burstcount(ram_burstcount), + .ram1_waitrequest(ram_waitrequest), + .ram1_readdata(ram_readdata), + .ram1_readdatavalid(ram_readdatavalid), + .ram1_read(ram_read), + .ram1_writedata(ram_writedata), + .ram1_byteenable(ram_byteenable), + .ram1_write(ram_write), + + //Spare 64-bit DDR3 RAM access + //currently unused + //can combine with ram1 to make a wider RAM bus (although will increase the latency) + .ramclk2_clk(0), + .ram2_address(0), + .ram2_burstcount(0), + .ram2_waitrequest(), + .ram2_readdata(), + .ram2_readdatavalid(), + .ram2_read(0), + .ram2_writedata(0), + .ram2_byteenable(0), + .ram2_write(0) +); + +`endif + + +///////////////////////// HDMI output ///////////////////////////////// + +pll_hdmi pll_hdmi +( + .refclk(FPGA_CLK1_50), + .rst(reset), + .outclk_0(HDMI_TX_CLK) +); + +hdmi_config hdmi_config +( + .iCLK(FPGA_CLK1_50), + .iRST_N(cfg_ready), + .I2C_SCL(HDMI_I2C_SCL), + .I2C_SDA(HDMI_I2C_SDA), + + .audio_48k(~audio_96k), + .iRES(4), // 720p + .iAR(1) // Aspect Ratio +); + +wire [23:0] hdmi_data; +osd hdmi_osd +( + .clk_sys(clk_sys), + + .io_osd(io_osd), + .io_strobe(io_strobe), + .io_din(io_din[7:0]), + + .clk_video(HDMI_TX_CLK), + .din(hdmi_data), + .dout(HDMI_TX_D), + .de(HDMI_TX_DE) +); + +assign HDMI_MCLK = 0; +i2s i2s +( + .reset(~cfg_ready), + .clk_sys(FPGA_CLK1_50), + .half_rate(~audio_96k), + + .sclk(HDMI_SCLK), + .lrclk(HDMI_LRCLK), + .sdata(HDMI_I2S), + + //Could inverse the MSB but it will shift 0 level to -MAX level + .left_chan (audio_l >> !audio_s), + .right_chan(audio_r >> !audio_s) +); + + +///////////////////////// VGA output ////////////////////////////////// + +wire [23:0] vga_q; +osd vga_osd +( + .clk_sys(clk_sys), + + .io_osd(io_osd), + .io_strobe(io_strobe), + .io_din(io_din[7:0]), + + .clk_video(clk_vid), + .din(de ? {r_out, g_out, b_out} : 24'd0), + .dout(vga_q), + .de(de) +); + +wire [23:0] vga_o; + +vga_out vga_out +( + .ypbpr_full(1), + .ypbpr_en(ypbpr_en), + .dout(vga_o), +`ifdef LITE + .din(vga_q) +`else + .din(vga_scaler ? HDMI_TX_D : vga_q) +`endif +); + +`ifdef LITE + wire vs1 = vs; + wire hs1 = hs; +`else + wire vs1 = vga_scaler ? HDMI_TX_VS : vs; + wire hs1 = vga_scaler ? HDMI_TX_HS : hs; +`endif + +assign VGA_VS = VGA_EN ? 1'bZ : csync ? 1'b1 : ~vs1; +assign VGA_HS = VGA_EN ? 1'bZ : csync ? ~(vs1 ^ hs1) : ~hs1; +assign VGA_R = VGA_EN ? 6'bZZZZZZ : vga_o[23:18]; +assign VGA_G = VGA_EN ? 6'bZZZZZZ : vga_o[15:10]; +assign VGA_B = VGA_EN ? 6'bZZZZZZ : vga_o[7:2]; + + +///////////////////////// Audio output //////////////////////////////// + +sigma_delta_dac #(15) dac_l +( + .CLK(FPGA_CLK3_50), + .RESET(reset), + .DACin({audio_l[15] ^ audio_s, audio_l[14:0]}), + .DACout(AUDIO_L) +); + +sigma_delta_dac #(15) dac_r +( + .CLK(FPGA_CLK3_50), + .RESET(reset), + .DACin({audio_r[15] ^ audio_s, audio_r[14:0]}), + .DACout(AUDIO_R) +); + +spdif toslink +( + .clk_i(FPGA_CLK3_50), + + .rst_i(reset), + .half_rate(0), + + .audio_l(audio_l >> !audio_s), + .audio_r(audio_r >> !audio_s), + + .spdif_o(AUDIO_SPDIF) +); + + +/////////////////// User module connection //////////////////////////// + +wire [15:0] audio_l, audio_r; +wire audio_s; +wire [7:0] r_out, g_out, b_out; +wire vs, hs, de; +wire clk_sys, clk_vid, ce_pix; + +wire ram_clk; +wire [28:0] ram_address; +wire [7:0] ram_burstcount; +wire ram_waitrequest; +wire [63:0] ram_readdata; +wire ram_readdatavalid; +wire ram_read; +wire [63:0] ram_writedata; +wire [7:0] ram_byteenable; +wire ram_write; + +wire led_user; +wire [1:0] led_power; +wire [1:0] led_disk; + +wire vs_emu, hs_emu; +sync_fix sync_v(FPGA_CLK3_50, vs_emu, vs); +sync_fix sync_h(FPGA_CLK3_50, hs_emu, hs); + +emu emu +( + .CLK_50M(FPGA_CLK3_50), + .RESET(reset), + .HPS_BUS({ctl_clk, clk_vid, ce_pix, de, hs, vs, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}), + + .CLK_VIDEO(clk_vid), + .CE_PIXEL(ce_pix), + + .VGA_R(r_out), + .VGA_G(g_out), + .VGA_B(b_out), + .VGA_HS(hs_emu), + .VGA_VS(vs_emu), + .VGA_DE(de), + + .LED_USER(led_user), + .LED_POWER(led_power), + .LED_DISK(led_disk), + +`ifndef LITE + .VIDEO_ARX(ARX), + .VIDEO_ARY(ARY), +`endif + + .AUDIO_L(audio_l), + .AUDIO_R(audio_r), + .AUDIO_S(audio_s), + .TAPE_IN(0), + + // SCK -> CLK + // MOSI -> CMD + // MISO <- DAT0 + // Z -> DAT1 + // Z -> DAT2 + // CS -> DAT3 + + .SD_SCK(SDIO_CLK), + .SD_MOSI(SDIO_CMD), + .SD_MISO(SDIO_DAT[0]), + .SD_CS(SDIO_DAT[3]), + + .DDRAM_CLK(ram_clk), + .DDRAM_ADDR(ram_address), + .DDRAM_BURSTCNT(ram_burstcount), + .DDRAM_BUSY(ram_waitrequest), + .DDRAM_DOUT(ram_readdata), + .DDRAM_DOUT_READY(ram_readdatavalid), + .DDRAM_RD(ram_read), + .DDRAM_DIN(ram_writedata), + .DDRAM_BE(ram_byteenable), + .DDRAM_WE(ram_write), + + .SDRAM_DQ(SDRAM_DQ), + .SDRAM_A(SDRAM_A), + .SDRAM_DQML(SDRAM_DQML), + .SDRAM_DQMH(SDRAM_DQMH), + .SDRAM_BA(SDRAM_BA), + .SDRAM_nCS(SDRAM_nCS), + .SDRAM_nWE(SDRAM_nWE), + .SDRAM_nRAS(SDRAM_nRAS), + .SDRAM_nCAS(SDRAM_nCAS), + .SDRAM_CLK(SDRAM_CLK), + .SDRAM_CKE(SDRAM_CKE) +); + +endmodule + +module sync_fix +( + input clk, + + input sync_in, + output sync_out +); + +assign sync_out = sync_in ^ pol; + +reg pol; +always @(posedge clk) begin + integer pos = 0, neg = 0, cnt = 0; + reg s1,s2; + + s1 <= sync_in; + s2 <= s1; + + if(~s2 & s1) neg <= cnt; + if(s2 & ~s1) pos <= cnt; + + cnt <= cnt + 1; + if(s2 != s1) cnt <= 0; + + pol <= pos > neg; +end + +endmodule diff --git a/sys/sysmem.qip b/sys/sysmem.qip new file mode 100644 index 0000000..6f27d09 --- /dev/null +++ b/sys/sysmem.qip @@ -0,0 +1,2 @@ +set_global_assignment -name SYSTEMVERILOG_FILE sys/sysmem.sv +set_global_assignment -name VERILOG_FILE sys/ip/reset_source.v diff --git a/sys/sysmem.sv b/sys/sysmem.sv new file mode 100644 index 0000000..4f38ca0 --- /dev/null +++ b/sys/sysmem.sv @@ -0,0 +1,519 @@ +`timescale 1 ps / 1 ps +module sysmem_lite +( + input ramclk1_clk, // ramclk1.clk + input [28:0] ram1_address, // ram1.address + input [7:0] ram1_burstcount, // .burstcount + output ram1_waitrequest, // .waitrequest + output [63:0] ram1_readdata, // .readdata + output ram1_readdatavalid, // .readdatavalid + input ram1_read, // .read + input [63:0] ram1_writedata, // .writedata + input [7:0] ram1_byteenable, // .byteenable + input ram1_write, // .write + + input ramclk2_clk, // ramclk2.clk + input [28:0] ram2_address, // ram2.address + input [7:0] ram2_burstcount, // .burstcount + output ram2_waitrequest, // .waitrequest + output [63:0] ram2_readdata, // .readdata + output ram2_readdatavalid, // .readdatavalid + input ram2_read, // .read + input [63:0] ram2_writedata, // .writedata + input [7:0] ram2_byteenable, // .byteenable + input ram2_write, // .write + + output ctl_clock, + input reset_cold_req, // reset.cold_req + output reset_reset, // .reset + input reset_reset_req, // .reset_req + input reset_warm_req // .warm_req +); + +assign ctl_clock = clk_vip_clk; + +wire hps_h2f_reset_reset; // HPS:h2f_rst_n -> Reset_Source:reset_hps +wire reset_source_reset_cold_reset; // Reset_Source:reset_cold -> HPS:f2h_cold_rst_req_n +wire reset_source_reset_warm_reset; // Reset_Source:reset_warm -> HPS:f2h_warm_rst_req_n +wire clk_vip_clk; + +sysmem_HPS_fpga_interfaces fpga_interfaces ( + .f2h_cold_rst_req_n (~reset_source_reset_cold_reset), // f2h_cold_reset_req.reset_n + .f2h_warm_rst_req_n (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n + .h2f_user0_clk (clk_vip_clk), // h2f_user0_clock.clk + .h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n + .f2h_sdram0_clk (clk_vip_clk), // f2h_sdram0_clock.clk + .f2h_sdram0_ADDRESS (0), // f2h_sdram0_data.address + .f2h_sdram0_BURSTCOUNT (0), // .burstcount + .f2h_sdram0_WAITREQUEST (), // .waitrequest + .f2h_sdram0_READDATA (), // .readdata + .f2h_sdram0_READDATAVALID (), // .readdatavalid + .f2h_sdram0_READ (0), // .read + .f2h_sdram0_WRITEDATA (0), // .writedata + .f2h_sdram0_BYTEENABLE (0), // .byteenable + .f2h_sdram0_WRITE (0), // .write + .f2h_sdram1_clk (ramclk1_clk), // f2h_sdram1_clock.clk + .f2h_sdram1_ADDRESS (ram1_address), // f2h_sdram1_data.address + .f2h_sdram1_BURSTCOUNT (ram1_burstcount), // .burstcount + .f2h_sdram1_WAITREQUEST (ram1_waitrequest), // .waitrequest + .f2h_sdram1_READDATA (ram1_readdata), // .readdata + .f2h_sdram1_READDATAVALID (ram1_readdatavalid), // .readdatavalid + .f2h_sdram1_READ (ram1_read), // .read + .f2h_sdram1_WRITEDATA (ram1_writedata), // .writedata + .f2h_sdram1_BYTEENABLE (ram1_byteenable), // .byteenable + .f2h_sdram1_WRITE (ram1_write), // .write + .f2h_sdram2_clk (ramclk2_clk), // f2h_sdram2_clock.clk + .f2h_sdram2_ADDRESS (ram2_address), // f2h_sdram2_data.address + .f2h_sdram2_BURSTCOUNT (ram2_burstcount), // .burstcount + .f2h_sdram2_WAITREQUEST (ram2_waitrequest), // .waitrequest + .f2h_sdram2_READDATA (ram2_readdata), // .readdata + .f2h_sdram2_READDATAVALID (ram2_readdatavalid), // .readdatavalid + .f2h_sdram2_READ (ram2_read), // .read + .f2h_sdram2_WRITEDATA (ram2_writedata), // .writedata + .f2h_sdram2_BYTEENABLE (ram2_byteenable), // .byteenable + .f2h_sdram2_WRITE (ram2_write) // .write +); + +reset_source reset_source ( + .clk (clk_vip_clk), // clock.clk + .reset_hps (~hps_h2f_reset_reset), // reset_hps.reset + .reset_sys (), // reset_sys.reset + .cold_req (reset_cold_req), // reset_ctl.cold_req + .reset (reset_reset), // .reset + .reset_req (reset_reset_req), // .reset_req + .warm_req (reset_warm_req), // .warm_req + .reset_warm (reset_source_reset_warm_reset), // reset_warm.reset + .reset_cold (reset_source_reset_cold_reset) // reset_cold.reset +); + +endmodule + +`timescale 1 ps / 1 ps +module sysmem +( + input ramclk1_clk, // ramclk1.clk + input [28:0] ram1_address, // ram1.address + input [7:0] ram1_burstcount, // .burstcount + output ram1_waitrequest, // .waitrequest + output [63:0] ram1_readdata, // .readdata + output ram1_readdatavalid, // .readdatavalid + input ram1_read, // .read + input [63:0] ram1_writedata, // .writedata + input [7:0] ram1_byteenable, // .byteenable + input ram1_write, // .write + + input ramclk2_clk, // ramclk2.clk + input [28:0] ram2_address, // ram2.address + input [7:0] ram2_burstcount, // .burstcount + output ram2_waitrequest, // .waitrequest + output [63:0] ram2_readdata, // .readdata + output ram2_readdatavalid, // .readdatavalid + input ram2_read, // .read + input [63:0] ram2_writedata, // .writedata + input [7:0] ram2_byteenable, // .byteenable + input ram2_write, // .write + + input reset_cold_req, // reset.cold_req + output reset_reset, // .reset + input reset_reset_req, // .reset_req + input reset_warm_req, // .warm_req + + input [27:0] ram_vip_address, // ram_vip.address + input [7:0] ram_vip_burstcount, // .burstcount + output ram_vip_waitrequest, // .waitrequest + output [127:0] ram_vip_readdata, // .readdata + output ram_vip_readdatavalid, // .readdatavalid + input ram_vip_read, // .read + input [127:0] ram_vip_writedata, // .writedata + input [15:0] ram_vip_byteenable, // .byteenable + input ram_vip_write, // .write + + output clk_vip_clk, // clk_vip.clk + output reset_vip_reset // reset_vip.reset +); + +wire hps_h2f_reset_reset; // HPS:h2f_rst_n -> Reset_Source:reset_hps +wire reset_source_reset_cold_reset; // Reset_Source:reset_cold -> HPS:f2h_cold_rst_req_n +wire reset_source_reset_warm_reset; // Reset_Source:reset_warm -> HPS:f2h_warm_rst_req_n + +sysmem_HPS_fpga_interfaces fpga_interfaces ( + .f2h_cold_rst_req_n (~reset_source_reset_cold_reset), // f2h_cold_reset_req.reset_n + .f2h_warm_rst_req_n (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n + .h2f_user0_clk (clk_vip_clk), // h2f_user0_clock.clk + .h2f_rst_n (hps_h2f_reset_reset), // h2f_reset.reset_n + .f2h_sdram0_clk (clk_vip_clk), // f2h_sdram0_clock.clk + .f2h_sdram0_ADDRESS (ram_vip_address), // f2h_sdram0_data.address + .f2h_sdram0_BURSTCOUNT (ram_vip_burstcount), // .burstcount + .f2h_sdram0_WAITREQUEST (ram_vip_waitrequest), // .waitrequest + .f2h_sdram0_READDATA (ram_vip_readdata), // .readdata + .f2h_sdram0_READDATAVALID (ram_vip_readdatavalid), // .readdatavalid + .f2h_sdram0_READ (ram_vip_read), // .read + .f2h_sdram0_WRITEDATA (ram_vip_writedata), // .writedata + .f2h_sdram0_BYTEENABLE (ram_vip_byteenable), // .byteenable + .f2h_sdram0_WRITE (ram_vip_write), // .write + .f2h_sdram1_clk (ramclk1_clk), // f2h_sdram1_clock.clk + .f2h_sdram1_ADDRESS (ram1_address), // f2h_sdram1_data.address + .f2h_sdram1_BURSTCOUNT (ram1_burstcount), // .burstcount + .f2h_sdram1_WAITREQUEST (ram1_waitrequest), // .waitrequest + .f2h_sdram1_READDATA (ram1_readdata), // .readdata + .f2h_sdram1_READDATAVALID (ram1_readdatavalid), // .readdatavalid + .f2h_sdram1_READ (ram1_read), // .read + .f2h_sdram1_WRITEDATA (ram1_writedata), // .writedata + .f2h_sdram1_BYTEENABLE (ram1_byteenable), // .byteenable + .f2h_sdram1_WRITE (ram1_write), // .write + .f2h_sdram2_clk (ramclk2_clk), // f2h_sdram2_clock.clk + .f2h_sdram2_ADDRESS (ram2_address), // f2h_sdram2_data.address + .f2h_sdram2_BURSTCOUNT (ram2_burstcount), // .burstcount + .f2h_sdram2_WAITREQUEST (ram2_waitrequest), // .waitrequest + .f2h_sdram2_READDATA (ram2_readdata), // .readdata + .f2h_sdram2_READDATAVALID (ram2_readdatavalid), // .readdatavalid + .f2h_sdram2_READ (ram2_read), // .read + .f2h_sdram2_WRITEDATA (ram2_writedata), // .writedata + .f2h_sdram2_BYTEENABLE (ram2_byteenable), // .byteenable + .f2h_sdram2_WRITE (ram2_write) // .write +); + +reset_source reset_source ( + .clk (clk_vip_clk), // clock.clk + .reset_hps (~hps_h2f_reset_reset), // reset_hps.reset + .reset_sys (reset_vip_reset), // reset_sys.reset + .cold_req (reset_cold_req), // reset_ctl.cold_req + .reset (reset_reset), // .reset + .reset_req (reset_reset_req), // .reset_req + .warm_req (reset_warm_req), // .warm_req + .reset_warm (reset_source_reset_warm_reset), // reset_warm.reset + .reset_cold (reset_source_reset_cold_reset) // reset_cold.reset +); + +endmodule + +module sysmem_HPS_fpga_interfaces +( + // h2f_reset + output wire [1 - 1 : 0 ] h2f_rst_n + + // f2h_cold_reset_req + ,input wire [1 - 1 : 0 ] f2h_cold_rst_req_n + + // f2h_warm_reset_req + ,input wire [1 - 1 : 0 ] f2h_warm_rst_req_n + + // h2f_user0_clock + ,output wire [1 - 1 : 0 ] h2f_user0_clk + + // f2h_sdram0_data + ,input wire [28 - 1 : 0 ] f2h_sdram0_ADDRESS + ,input wire [8 - 1 : 0 ] f2h_sdram0_BURSTCOUNT + ,output wire [1 - 1 : 0 ] f2h_sdram0_WAITREQUEST + ,output wire [128 - 1 : 0 ] f2h_sdram0_READDATA + ,output wire [1 - 1 : 0 ] f2h_sdram0_READDATAVALID + ,input wire [1 - 1 : 0 ] f2h_sdram0_READ + ,input wire [128 - 1 : 0 ] f2h_sdram0_WRITEDATA + ,input wire [16 - 1 : 0 ] f2h_sdram0_BYTEENABLE + ,input wire [1 - 1 : 0 ] f2h_sdram0_WRITE + + // f2h_sdram0_clock + ,input wire [1 - 1 : 0 ] f2h_sdram0_clk + + // f2h_sdram1_data + ,input wire [29 - 1 : 0 ] f2h_sdram1_ADDRESS + ,input wire [8 - 1 : 0 ] f2h_sdram1_BURSTCOUNT + ,output wire [1 - 1 : 0 ] f2h_sdram1_WAITREQUEST + ,output wire [64 - 1 : 0 ] f2h_sdram1_READDATA + ,output wire [1 - 1 : 0 ] f2h_sdram1_READDATAVALID + ,input wire [1 - 1 : 0 ] f2h_sdram1_READ + ,input wire [64 - 1 : 0 ] f2h_sdram1_WRITEDATA + ,input wire [8 - 1 : 0 ] f2h_sdram1_BYTEENABLE + ,input wire [1 - 1 : 0 ] f2h_sdram1_WRITE + + // f2h_sdram1_clock + ,input wire [1 - 1 : 0 ] f2h_sdram1_clk + + // f2h_sdram2_data + ,input wire [29 - 1 : 0 ] f2h_sdram2_ADDRESS + ,input wire [8 - 1 : 0 ] f2h_sdram2_BURSTCOUNT + ,output wire [1 - 1 : 0 ] f2h_sdram2_WAITREQUEST + ,output wire [64 - 1 : 0 ] f2h_sdram2_READDATA + ,output wire [1 - 1 : 0 ] f2h_sdram2_READDATAVALID + ,input wire [1 - 1 : 0 ] f2h_sdram2_READ + ,input wire [64 - 1 : 0 ] f2h_sdram2_WRITEDATA + ,input wire [8 - 1 : 0 ] f2h_sdram2_BYTEENABLE + ,input wire [1 - 1 : 0 ] f2h_sdram2_WRITE + + // f2h_sdram2_clock + ,input wire [1 - 1 : 0 ] f2h_sdram2_clk +); + + +wire [29 - 1 : 0] intermediate; +assign intermediate[0:0] = ~intermediate[1:1]; +assign intermediate[8:8] = intermediate[4:4]|intermediate[7:7]; +assign intermediate[2:2] = intermediate[9:9]; +assign intermediate[3:3] = intermediate[9:9]; +assign intermediate[5:5] = intermediate[9:9]; +assign intermediate[6:6] = intermediate[9:9]; +assign intermediate[10:10] = intermediate[9:9]; +assign intermediate[11:11] = ~intermediate[12:12]; +assign intermediate[17:17] = intermediate[14:14]|intermediate[16:16]; +assign intermediate[13:13] = intermediate[18:18]; +assign intermediate[15:15] = intermediate[18:18]; +assign intermediate[19:19] = intermediate[18:18]; +assign intermediate[20:20] = ~intermediate[21:21]; +assign intermediate[26:26] = intermediate[23:23]|intermediate[25:25]; +assign intermediate[22:22] = intermediate[27:27]; +assign intermediate[24:24] = intermediate[27:27]; +assign intermediate[28:28] = intermediate[27:27]; +assign f2h_sdram0_WAITREQUEST[0:0] = intermediate[0:0]; +assign f2h_sdram1_WAITREQUEST[0:0] = intermediate[11:11]; +assign f2h_sdram2_WAITREQUEST[0:0] = intermediate[20:20]; +assign intermediate[4:4] = f2h_sdram0_READ[0:0]; +assign intermediate[7:7] = f2h_sdram0_WRITE[0:0]; +assign intermediate[9:9] = f2h_sdram0_clk[0:0]; +assign intermediate[14:14] = f2h_sdram1_READ[0:0]; +assign intermediate[16:16] = f2h_sdram1_WRITE[0:0]; +assign intermediate[18:18] = f2h_sdram1_clk[0:0]; +assign intermediate[23:23] = f2h_sdram2_READ[0:0]; +assign intermediate[25:25] = f2h_sdram2_WRITE[0:0]; +assign intermediate[27:27] = f2h_sdram2_clk[0:0]; + +cyclonev_hps_interface_clocks_resets clocks_resets( + .f2h_warm_rst_req_n({ + f2h_warm_rst_req_n[0:0] // 0:0 + }) +,.f2h_pending_rst_ack({ + 1'b1 // 0:0 + }) +,.f2h_dbg_rst_req_n({ + 1'b1 // 0:0 + }) +,.h2f_rst_n({ + h2f_rst_n[0:0] // 0:0 + }) +,.f2h_cold_rst_req_n({ + f2h_cold_rst_req_n[0:0] // 0:0 + }) +,.h2f_user0_clk({ + h2f_user0_clk[0:0] // 0:0 + }) +); + + +cyclonev_hps_interface_dbg_apb debug_apb( + .DBG_APB_DISABLE({ + 1'b0 // 0:0 + }) +,.P_CLK_EN({ + 1'b0 // 0:0 + }) +); + + +cyclonev_hps_interface_tpiu_trace tpiu( + .traceclk_ctl({ + 1'b1 // 0:0 + }) +); + + +cyclonev_hps_interface_boot_from_fpga boot_from_fpga( + .boot_from_fpga_ready({ + 1'b0 // 0:0 + }) +,.boot_from_fpga_on_failure({ + 1'b0 // 0:0 + }) +,.bsel_en({ + 1'b0 // 0:0 + }) +,.csel_en({ + 1'b0 // 0:0 + }) +,.csel({ + 2'b01 // 1:0 + }) +,.bsel({ + 3'b001 // 2:0 + }) +); + + +cyclonev_hps_interface_fpga2hps fpga2hps( + .port_size_config({ + 2'b11 // 1:0 + }) +); + + +cyclonev_hps_interface_hps2fpga hps2fpga( + .port_size_config({ + 2'b11 // 1:0 + }) +); + + +cyclonev_hps_interface_fpga2sdram f2sdram( + .cfg_rfifo_cport_map({ + 16'b0010000100000000 // 15:0 + }) +,.cfg_wfifo_cport_map({ + 16'b0010000100000000 // 15:0 + }) +,.rd_ready_3({ + 1'b1 // 0:0 + }) +,.cmd_port_clk_2({ + intermediate[28:28] // 0:0 + }) +,.rd_ready_2({ + 1'b1 // 0:0 + }) +,.cmd_port_clk_1({ + intermediate[19:19] // 0:0 + }) +,.rd_ready_1({ + 1'b1 // 0:0 + }) +,.cmd_port_clk_0({ + intermediate[10:10] // 0:0 + }) +,.rd_ready_0({ + 1'b1 // 0:0 + }) +,.wrack_ready_2({ + 1'b1 // 0:0 + }) +,.wrack_ready_1({ + 1'b1 // 0:0 + }) +,.wrack_ready_0({ + 1'b1 // 0:0 + }) +,.cmd_ready_2({ + intermediate[21:21] // 0:0 + }) +,.cmd_ready_1({ + intermediate[12:12] // 0:0 + }) +,.cmd_ready_0({ + intermediate[1:1] // 0:0 + }) +,.cfg_port_width({ + 12'b000000010110 // 11:0 + }) +,.rd_valid_3({ + f2h_sdram2_READDATAVALID[0:0] // 0:0 + }) +,.rd_valid_2({ + f2h_sdram1_READDATAVALID[0:0] // 0:0 + }) +,.rd_valid_1({ + f2h_sdram0_READDATAVALID[0:0] // 0:0 + }) +,.rd_clk_3({ + intermediate[22:22] // 0:0 + }) +,.rd_data_3({ + f2h_sdram2_READDATA[63:0] // 63:0 + }) +,.rd_clk_2({ + intermediate[13:13] // 0:0 + }) +,.rd_data_2({ + f2h_sdram1_READDATA[63:0] // 63:0 + }) +,.rd_clk_1({ + intermediate[3:3] // 0:0 + }) +,.rd_data_1({ + f2h_sdram0_READDATA[127:64] // 63:0 + }) +,.rd_clk_0({ + intermediate[2:2] // 0:0 + }) +,.rd_data_0({ + f2h_sdram0_READDATA[63:0] // 63:0 + }) +,.cfg_axi_mm_select({ + 6'b000000 // 5:0 + }) +,.cmd_valid_2({ + intermediate[26:26] // 0:0 + }) +,.cmd_valid_1({ + intermediate[17:17] // 0:0 + }) +,.cmd_valid_0({ + intermediate[8:8] // 0:0 + }) +,.cfg_cport_rfifo_map({ + 18'b000000000011010000 // 17:0 + }) +,.wr_data_3({ + 2'b00 // 89:88 + ,f2h_sdram2_BYTEENABLE[7:0] // 87:80 + ,16'b0000000000000000 // 79:64 + ,f2h_sdram2_WRITEDATA[63:0] // 63:0 + }) +,.wr_data_2({ + 2'b00 // 89:88 + ,f2h_sdram1_BYTEENABLE[7:0] // 87:80 + ,16'b0000000000000000 // 79:64 + ,f2h_sdram1_WRITEDATA[63:0] // 63:0 + }) +,.wr_data_1({ + 2'b00 // 89:88 + ,f2h_sdram0_BYTEENABLE[15:8] // 87:80 + ,16'b0000000000000000 // 79:64 + ,f2h_sdram0_WRITEDATA[127:64] // 63:0 + }) +,.cfg_cport_type({ + 12'b000000111111 // 11:0 + }) +,.wr_data_0({ + 2'b00 // 89:88 + ,f2h_sdram0_BYTEENABLE[7:0] // 87:80 + ,16'b0000000000000000 // 79:64 + ,f2h_sdram0_WRITEDATA[63:0] // 63:0 + }) +,.cfg_cport_wfifo_map({ + 18'b000000000011010000 // 17:0 + }) +,.wr_clk_3({ + intermediate[24:24] // 0:0 + }) +,.wr_clk_2({ + intermediate[15:15] // 0:0 + }) +,.wr_clk_1({ + intermediate[6:6] // 0:0 + }) +,.wr_clk_0({ + intermediate[5:5] // 0:0 + }) +,.cmd_data_2({ + 18'b000000000000000000 // 59:42 + ,f2h_sdram2_BURSTCOUNT[7:0] // 41:34 + ,3'b000 // 33:31 + ,f2h_sdram2_ADDRESS[28:0] // 30:2 + ,intermediate[25:25] // 1:1 + ,intermediate[23:23] // 0:0 + }) +,.cmd_data_1({ + 18'b000000000000000000 // 59:42 + ,f2h_sdram1_BURSTCOUNT[7:0] // 41:34 + ,3'b000 // 33:31 + ,f2h_sdram1_ADDRESS[28:0] // 30:2 + ,intermediate[16:16] // 1:1 + ,intermediate[14:14] // 0:0 + }) +,.cmd_data_0({ + 18'b000000000000000000 // 59:42 + ,f2h_sdram0_BURSTCOUNT[7:0] // 41:34 + ,4'b0000 // 33:30 + ,f2h_sdram0_ADDRESS[27:0] // 29:2 + ,intermediate[7:7] // 1:1 + ,intermediate[4:4] // 0:0 + }) +); + +endmodule diff --git a/sys/vga_out.sv b/sys/vga_out.sv new file mode 100644 index 0000000..e316000 --- /dev/null +++ b/sys/vga_out.sv @@ -0,0 +1,65 @@ + +module vga_out +( + input ypbpr_full, + input ypbpr_en, + + input [23:0] din, + output [23:0] dout +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +wire [5:0] red = din[23:18]; +wire [5:0] green = din[15:10]; +wire [5:0] blue = din[7:2]; + +// http://marsee101.blog19.fc2.com/blog-entry-2311.html +// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) +// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) +// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign dout[23:16] = ypbpr_en ? {(ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]), 2'b00} : din[23:16]; +assign dout[15:8] = ypbpr_en ? {(ypbpr_full ? yuv_full[y -8'd16] : y[7:2]), 2'b00} : din[15:8]; +assign dout[7:0] = ypbpr_en ? {(ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]), 2'b00} : din[7:0]; + + +endmodule diff --git a/sys/video_mixer.sv b/sys/video_mixer.sv new file mode 100644 index 0000000..6babc3e --- /dev/null +++ b/sys/video_mixer.sv @@ -0,0 +1,167 @@ +// +// +// Copyright (c) 2017 Sorgelig +// +// This program is GPL Licensed. See COPYING for the full license. +// +// +//////////////////////////////////////////////////////////////////////////////////////////////////////// + +`timescale 1ns / 1ps + +// +// LINE_LENGTH: Length of display line in pixels +// Usually it's length from HSync to HSync. +// May be less if line_start is used. +// +// HALF_DEPTH: If =1 then color dept is 4 bits per component +// For half depth 8 bits monochrome is available with +// mono signal enabled and color = {G, R} + +module video_mixer +#( + parameter LINE_LENGTH = 768, + parameter HALF_DEPTH = 0 +) +( + // master clock + // it should be multiple by (ce_pix*4). + input clk_sys, + + // Pixel clock or clock_enable (both are accepted). + input ce_pix, + output ce_pix_out, + + input scandoubler, + + // scanlines (00-none 01-25% 10-50% 11-75%) + input [1:0] scanlines, + + // High quality 2x scaling + input hq2x, + + // color + input [DWIDTH:0] R, + input [DWIDTH:0] G, + input [DWIDTH:0] B, + + // Monochrome mode (for HALF_DEPTH only) + input mono, + + // Positive pulses. + input HSync, + input VSync, + input HBlank, + input VBlank, + + // video output signals + output reg [7:0] VGA_R, + output reg [7:0] VGA_G, + output reg [7:0] VGA_B, + output reg VGA_VS, + output reg VGA_HS, + output reg VGA_DE +); + +localparam DWIDTH = HALF_DEPTH ? 3 : 7; + +wire [DWIDTH:0] R_sd; +wire [DWIDTH:0] G_sd; +wire [DWIDTH:0] B_sd; +wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd; + +scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) sd +( + .*, + .hs_in(HSync), + .vs_in(VSync), + .hb_in(HBlank), + .vb_in(VBlank), + .r_in(R), + .g_in(G), + .b_in(B), + + .ce_pix_out(ce_pix_sd), + .hs_out(hs_sd), + .vs_out(vs_sd), + .hb_out(hb_sd), + .vb_out(vb_sd), + .r_out(R_sd), + .g_out(G_sd), + .b_out(B_sd) +); + +wire [DWIDTH:0] rt = (scandoubler ? R_sd : R); +wire [DWIDTH:0] gt = (scandoubler ? G_sd : G); +wire [DWIDTH:0] bt = (scandoubler ? B_sd : B); + +generate + if(HALF_DEPTH) begin + wire [7:0] r = mono ? {gt,rt} : {rt,rt}; + wire [7:0] g = mono ? {gt,rt} : {gt,gt}; + wire [7:0] b = mono ? {gt,rt} : {bt,bt}; + end else begin + wire [7:0] r = rt; + wire [7:0] g = gt; + wire [7:0] b = bt; + end +endgenerate + +wire hs = (scandoubler ? hs_sd : HSync); +wire vs = (scandoubler ? vs_sd : VSync); + +assign ce_pix_out = scandoubler ? ce_pix_sd : ce_pix; + + +reg scanline = 0; +always @(posedge clk_sys) begin + reg old_hs, old_vs; + + old_hs <= hs; + old_vs <= vs; + + if(old_hs && ~hs) scanline <= ~scanline; + if(old_vs && ~vs) scanline <= 0; +end + +wire hde = scandoubler ? ~hb_sd : ~HBlank; +wire vde = scandoubler ? ~vb_sd : ~VBlank; + +always @(posedge clk_sys) begin + reg old_hde; + + case(scanlines & {scanline, scanline}) + 1: begin // reduce 25% = 1/2 + 1/4 + VGA_R <= {1'b0, r[7:1]} + {2'b00, r[7:2]}; + VGA_G <= {1'b0, g[7:1]} + {2'b00, g[7:2]}; + VGA_B <= {1'b0, b[7:1]} + {2'b00, b[7:2]}; + end + + 2: begin // reduce 50% = 1/2 + VGA_R <= {1'b0, r[7:1]}; + VGA_G <= {1'b0, g[7:1]}; + VGA_B <= {1'b0, b[7:1]}; + end + + 3: begin // reduce 75% = 1/4 + VGA_R <= {2'b00, r[7:2]}; + VGA_G <= {2'b00, g[7:2]}; + VGA_B <= {2'b00, b[7:2]}; + end + + default: begin + VGA_R <= r; + VGA_G <= g; + VGA_B <= b; + end + endcase + + VGA_VS <= vs; + VGA_HS <= hs; + + old_hde <= hde; + if(~old_hde && hde && vde) VGA_DE <= 1; + if(old_hde && ~hde) VGA_DE <= 0; +end + +endmodule diff --git a/sys/vip.qip b/sys/vip.qip new file mode 100644 index 0000000..abbb0dc --- /dev/null +++ b/sys/vip.qip @@ -0,0 +1,2 @@ +set_global_assignment -name SYSTEMVERILOG_FILE sys/vip_config.sv +set_global_assignment -name QIP_FILE sys/vip/synthesis/vip.qip diff --git a/sys/vip.qsys b/sys/vip.qsys new file mode 100644 index 0000000..4a96e70 --- /dev/null +++ b/sys/vip.qsys @@ -0,0 +1,1097 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No + + + + + + + + + + + + + + + + + + + + + Avalon-MM Bidirectional,Avalon-MM Bidirectional,Avalon-MM Bidirectional + + + + + + + + + + + + + + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No + + + + + + + + + + + + + + + + No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + {320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ]]> + + + + + + + + + + + + + + + + + + + + + + + + + ]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sys/vip_config.sv b/sys/vip_config.sv new file mode 100644 index 0000000..d5349b6 --- /dev/null +++ b/sys/vip_config.sv @@ -0,0 +1,169 @@ + +module vip_config +( + input clk, + input reset, + + input [7:0] ARX, + input [7:0] ARY, + + output reg [8:0] address, + output reg write, + output reg [31:0] writedata, + input waitrequest +); + +//Any input video resolution up to 1920x1080 is supported. + +//Output video parameters. +//It's good to keep 1280x720@60 resolution among all cores as most compatible resolution. +parameter WIDTH = 1280; +parameter HEIGHT = 720; +parameter HFP = 110; +parameter HBP = 220; +parameter HS = 40; +parameter VFP = 5; +parameter VBP = 20; +parameter VS = 5; + + +reg [31:0] wcalc; +reg [31:0] hcalc; + +wire [31:0] videow = (wcalc > WIDTH) ? WIDTH : wcalc; +wire [31:0] videoh = (hcalc > HEIGHT) ? HEIGHT : hcalc; + +wire [31:0] posx = (WIDTH - videow)>>1; +wire [31:0] posy = (HEIGHT- videoh)>>1; + + +always @(posedge clk) begin + reg [7:0] state = 0; + reg [7:0] arx, ary; + integer timeout = 0; + + if(reset || (!state && ((arx != ARX) || (ary != ARY)))) begin + arx <= ARX; + ary <= ARY; + timeout <= 0; + write <= 0; + end + else + if(timeout < 1000000) + begin + timeout <= timeout + 1; + write <= 0; + state <= 1; + end + else + if(~waitrequest && state) + begin + state <= state + 1'd1; + write <= 1; + + case(state) + 01: begin + wcalc <= (HEIGHT*arx)/ary; + hcalc <= (WIDTH*ary)/arx; + end + endcase + + if(state&3) write <= 0; + else + case(state>>2) + //scaler + 01: begin + address <= 'h003; //Output Width + writedata <= videow; + end + 02: begin + address <= 'h004; //Output Height + writedata <= videoh; + end + 03: begin + address <= 'h000; //Go + writedata <= 1; + end + + //mixer + 10: begin + address <= 'h083; //Bkg Width + writedata <= WIDTH; + end + 11: begin + address <= 'h084; //Bkg Height + writedata <= HEIGHT; + end + 12: begin + address <= 'h088; //Pos X + writedata <= posx; + end + 13: begin + address <= 'h089; //Pos Y + writedata <= posy; + end + 14: begin + address <= 'h08A; //Enable Video 0 + writedata <= 1; + end + 15: begin + address <= 'h080; //Go + writedata <= 1; + end + + //video mode + 20: begin + address <= 'h104; //Bank + writedata <= 0; + end + 21: begin + address <= 'h105; //Progressive/Interlaced + writedata <= 0; + end + 22: begin + address <= 'h106; //Active pixel count + writedata <= WIDTH; + end + 23: begin + address <= 'h107; //Active line count + writedata <= HEIGHT; + end + 24: begin + address <= 'h109; //Horizontal Front Porch + writedata <= HFP; + end + 25: begin + address <= 'h10A; //Horizontal Sync Length + writedata <= HS; + end + 26: begin + address <= 'h10B; //Horizontal Blanking (HFP+HBP+HSync) + writedata <= HFP+HBP+HS; + end + 27: begin + address <= 'h10C; //Vertical Front Porch + writedata <= VFP; + end + 28: begin + address <= 'h10D; //Vertical Sync Length + writedata <= VS; + end + 29: begin + address <= 'h10E; //Vertical blanking (VFP+VBP+VSync) + writedata <= VFP+VBP+VS; + end + 30: begin + address <= 'h11E; //Valid + writedata <= 1; + end + 31: begin + address <= 'h100; //Go + writedata <= 1; + end + + default: write <= 0; + endcase + end +end + +endmodule diff --git a/timing_generator.vhd b/timing_generator.vhd new file mode 100644 index 0000000..2612b89 --- /dev/null +++ b/timing_generator.vhd @@ -0,0 +1,150 @@ +------------------------------------------------------------------------------- +-- +-- Apple ][ Timing logic +-- +-- Stephen A. Edwards, sedwards@cs.columbia.edu +-- +-- Taken more-or-less verbatim from the schematics in the +-- Apple ][ reference manual +-- +-- This takes a 14.31818 MHz master clock and divides it down to generate +-- the various lower-frequency signals (e.g., 7M, phase 0, colorburst) +-- as well as horizontal and vertical blanking and sync signals for the video +-- and the video addresses. +-- +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity timing_generator is + + port ( + CLK_14M : in std_logic; -- 14.31818 MHz master clock + CLK_7M : buffer std_logic := '0'; + Q3 : buffer std_logic := '0'; -- 2 MHz signal in phase with PHI0 + RAS_N : buffer std_logic := '0'; + CAS_N : buffer std_logic := '0'; + AX : buffer std_logic := '0'; + PHI0 : buffer std_logic := '0'; -- 1.0 MHz processor clock + PRE_PHI0 : buffer std_logic := '0'; -- One 14M cycle before + COLOR_REF : buffer std_logic := '0'; -- 3.579545 MHz colorburst + + TEXT_MODE : in std_logic; + PAGE2 : in std_logic; + HIRES : in std_logic; + + VIDEO_ADDRESS : out unsigned(15 downto 0); + H0 : out std_logic; + VA : out std_logic; -- Character row address + VB : out std_logic; + VC : out std_logic; + V2 : out std_logic; + V4 : out std_logic; + HBL : buffer std_logic; -- Horizontal blanking + VBL : buffer std_logic; -- Vertical blanking + BLANK : out std_logic; -- Composite blanking + LDPS_N : out std_logic; + LD194 : out std_logic + ); + +end timing_generator; + +architecture rtl of timing_generator is + + signal H : unsigned(6 downto 0) := "0000000"; + signal V : unsigned(8 downto 0) := "011111010"; + signal COLOR_DELAY_N : std_logic; + +begin + + -- To generate the once-a-line hiccup: D1 pin 6 + COLOR_DELAY_N <= + not (not COLOR_REF and (not AX and not CAS_N) and PHI0 and not H(6)); + + -- The DRAM signal generator + C2_74S195: process (CLK_14M) + begin + if rising_edge(CLK_14M) then + if Q3 = '1' then -- shift + (Q3, CAS_N, AX, RAS_N) <= + unsigned'(CAS_N, AX, RAS_N, '0'); + else -- load + (Q3, CAS_N, AX, RAS_N) <= + unsigned'(RAS_N, AX, COLOR_DELAY_N, AX); + end if; + end if; + end process; + + -- The main clock signal generator + B1_74S175 : process (CLK_14M) + begin + if rising_edge(CLK_14M) then + COLOR_REF <= CLK_7M xor COLOR_REF; + CLK_7M <= not CLK_7M; + PHI0 <= PRE_PHI0; + if AX = '1' then + PRE_PHI0 <= not (Q3 xor PHI0); -- B1 pin 10 + end if; + end if; + end process; + + LDPS_N <= not (PHI0 and not AX and not CAS_N); + LD194 <= not (PHI0 and not AX and not CAS_N and not CLK_7M); + + -- Four four-bit presettable binary counters + -- Seven-bit horizontal counter counts 0, 40, 41, ..., 7F (65 states) + -- Nine-bit vertical counter counts $FA .. $1FF (262 states) + D11D12D13D14_74LS161 : process (CLK_14M) + begin + if rising_edge(CLK_14M) then + -- True the cycle before the rising edge of LDPS_N: emulates + -- the effects of using LDPS_N as the clock for the video counters + if (PHI0 and not AX and ((Q3 and RAS_N) or + (not Q3 and COLOR_DELAY_N))) = '1' then + if H(6) = '0' then H <= "1000000"; + else + H <= H + 1; + if H = "1111111" then + V <= V + 1; + if V = "111111111" then V <= "011111010"; end if; + end if; + end if; + end if; + end if; + + end process; + + H0 <= H(0); + VA <= V(0); + VB <= V(1); + VC <= V(2); + V2 <= V(5); + V4 <= V(7); + + HBL <= not (H(5) or (H(3) and H(4))); + VBL <= V(6) and V(7); + + BLANK <= HBL or VBL; + + -- V_SYNC <= VBL and V(5) and not V(4) and not V(3) and + -- not V(2) and (H(4) or H(3) or H(5)); + -- H_SYNC <= HBL and H(3) and not H(2); + + -- SYNC <= not (V_SYNC or H_SYNC); + -- COLOR_BURST <= HBL and H(2) and H(3) and (COLOR_REF or TEXT_MODE); + + -- Video address calculation + VIDEO_ADDRESS(2 downto 0) <= H(2 downto 0); + VIDEO_ADDRESS(6 downto 3) <= (not H(5) & V(6) & H(4) & H(3)) + + ( V(7) & not H(5) & V(7) & '1') + + ( "000" & V(6)); + VIDEO_ADDRESS(9 downto 7) <= V(5 downto 3); + VIDEO_ADDRESS(14 downto 10) <= + ( "00" & HBL & PAGE2 & not PAGE2) when HIRES = '0' else + (PAGE2 & not PAGE2 & V(2 downto 0)); + + VIDEO_ADDRESS(15) <= '0'; + +end rtl; diff --git a/vga_controller.vhd b/vga_controller.vhd new file mode 100644 index 0000000..3f871e5 --- /dev/null +++ b/vga_controller.vhd @@ -0,0 +1,314 @@ +------------------------------------------------------------------------------- +-- +-- A VGA line-doubler for an Apple ][ +-- +-- Stephen A. Edwards, sedwards@cs.columbia.edu +-- +-- +-- FIXME: This is all wrong +-- +-- The Apple ][ uses a 14.31818 MHz master clock. It outputs a new +-- horizontal line every 65 * 14 + 2 = 912 14M cycles. The extra two +-- are from the "extended cycle" used to keep the 3.579545 MHz +-- colorburst signal in sync. Of these, 40 * 14 = 560 are active video. +-- +-- In graphics mode, the Apple effectively generates 140 four-bit pixels +-- output serially (i.e., with 3.579545 MHz pixel clock). In text mode, +-- it generates 280 one-bit pixels (i.e., with a 7.15909 MHz pixel clock). +-- +-- We capture 140 four-bit nibbles for each line and interpret them in +-- one of the two modes. In graphics mode, each is displayed as a +-- single pixel of one of 16 colors. In text mode, each is displayed +-- as two black or white pixels. +-- +-- The VGA display is nominally 640 X 480, but we use a 14.31818 MHz +-- dot clock. To stay in sync with the Apple, we generate a new line +-- every 912 / 2 = 456 14M cycles= 31.8 us, a 31.4 kHz horizontal +-- refresh rate. Of these, 280 will be active video. +-- +-- One set of suggested VGA timings: +-- +-- ______________________ ________ +-- ________| VIDEO |________| VIDEO +-- |-C-|----------D-----------|-E-| +-- __ ______________________________ ___________ +-- |_| |_| +-- |B| +-- |---------------A----------------| +-- +-- A = 31.77 us Scanline time +-- B = 3.77 us Horizontal sync time +-- C = 1.89 us Back porch +-- D = 25.17 us Active video +-- E = 0.94 us Front porch +-- +-- We use A = 456 / 14.31818 MHz = 31.84 us +-- B = 54 / 14.31818 MHz = 3.77 us +-- C = 106 / 14.31818 MHz = 7.40 us +-- D = 280 / 14.31818 MHz = 19.56 us +-- E = 16 / 14.31818 MHz = 1.12 us +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vga_controller is + + port ( + CLK_28M : in std_logic; -- 14.31818 MHz master clock + + VIDEO : in std_logic; -- from the Apple video generator + COLOR_LINE : in std_logic; + SCREEN_MODE: in std_logic_vector(1 downto 0); -- 00: Color, 01: B&W, 10: Green, 11: Amber + HBL : in std_logic; + VBL : in std_logic; + LD194 : in std_logic; + + VGA_CLK : out std_logic; + VGA_HS : out std_logic; -- Active low + VGA_VS : out std_logic; -- Active low + VGA_DE : out std_logic; + VGA_R : out unsigned(7 downto 0); + VGA_G : out unsigned(7 downto 0); + VGA_B : out unsigned(7 downto 0) + ); + +end vga_controller; + +architecture rtl of vga_controller is + + -- Double-ported RAM (one read port, one write port) + -- that holds two lines of 560 pixels + type line_memory_t is array (0 to 2047) of std_logic; + signal line_memory : line_memory_t; + + -- RGB values from Linards Ticmanis, + -- http://newsgroups.derkeiler.com/Archive/Comp/comp.sys.apple2/2005-09/msg00534.html + + type basis_color is array(0 to 3) of unsigned(7 downto 0); + constant basis_r : basis_color := ( X"88", X"38", X"07", X"38" ); + constant basis_g : basis_color := ( X"22", X"24", X"67", X"52" ); + constant basis_b : basis_color := ( X"2C", X"A0", X"2C", X"07" ); + + signal ram_write_addr : unsigned(10 downto 0); + signal ram_we : std_logic; + signal ram_read_addr : unsigned(10 downto 0); + signal ram_data_out : std_logic; + + signal shift_reg : unsigned(5 downto 0); -- Last six pixels + + signal last_hbl : std_logic; + signal hcount : unsigned(10 downto 0); + signal hcount2 : unsigned(10 downto 0); + signal vcount : unsigned(5 downto 0); + signal even_line : std_logic; + signal hactive, hactive_early2, hactive_early1 : std_logic; + + constant VGA_SCANLINE : integer := 456*2; -- Must be 456*2 (set by the Apple) + + constant VGA_HSYNC : integer := 54 * 2; + constant VGA_BACK_PORCH : integer := 66 * 2; + constant VGA_ACTIVE : integer := 282 * 2; + constant VGA_FRONT_PORCH : integer := 54 * 2; + + -- VGA_HSYNC + VGA_BACK_PORCH + VGA_ACTIVE + VGA_FRONT_PORCH = VGA_SCANLINE + + constant VBL_TO_VSYNC : integer := 33; + constant VGA_VSYNC_LINES : integer := 3; + + signal VGA_VS_I, VGA_HS_I : std_logic; + + signal video_active : std_logic; + signal vbl_delayed, vbl_delayed2 : std_logic; + signal hbl_delayed : std_logic; + signal color_line_delayed_1, color_line_delayed_2 : std_logic; + +begin + + delay_hbl : process (CLK_28M) + begin + if rising_edge(CLK_28M) then + if LD194 = '0' then + hbl_delayed <= HBL; + end if; + end if; + end process; + + hcount_vcount_control : process (CLK_28M) + begin + if rising_edge(CLK_28M) then + if last_hbl = '1' and hbl_delayed = '0' then -- Falling edge + color_line_delayed_2 <= color_line_delayed_1; + color_line_delayed_1 <= COLOR_LINE; + hcount <= (others => '0'); + vbl_delayed2 <= vbl_delayed; + vbl_delayed <= VBL; + if vbl_delayed = '1' then + even_line <= '0'; + vcount <= vcount + 1; + else + vcount <= (others => '0'); + even_line <= not even_line; + end if; + else + hcount <= hcount + 1; + end if; + last_hbl <= hbl_delayed; + end if; + end process hcount_vcount_control; + + hsync_gen : process (CLK_28M) + begin + if rising_edge(CLK_28M) then + if hcount = VGA_ACTIVE + VGA_FRONT_PORCH or + hcount = VGA_SCANLINE + VGA_ACTIVE + VGA_FRONT_PORCH then + VGA_HS_I <= '0'; + elsif hcount = VGA_ACTIVE + VGA_FRONT_PORCH + VGA_HSYNC or + hcount = VGA_SCANLINE + VGA_ACTIVE + VGA_FRONT_PORCH + VGA_HSYNC then + VGA_HS_I <= '1'; + end if; + + hactive <= hactive_early1; + hactive_early1 <= hactive_early2; + + if hcount = VGA_SCANLINE - 1 or + hcount = VGA_SCANLINE + VGA_SCANLINE - 1 then + hactive_early2 <= '1'; + elsif hcount = VGA_ACTIVE or + hcount = VGA_ACTIVE + VGA_SCANLINE then + hactive_early2 <= '0'; + end if; + end if; + end process hsync_gen; + + VGA_HS <= VGA_HS_I; + + vsync_gen : process (CLK_28M) + begin + if rising_edge(CLK_28M) then + if vcount = VBL_TO_VSYNC then + VGA_VS_I <= '0'; + elsif vcount = VBL_TO_VSYNC + VGA_VSYNC_LINES then + VGA_VS_I <= '1'; + end if; + end if; + end process vsync_gen; + + VGA_VS <= VGA_VS_I; + + hcount2 <= hcount - VGA_SCANLINE; + + ram_read_addr <= + even_line & hcount(9 downto 0) when hcount < VGA_SCANLINE else + even_line & hcount2(9 downto 0); + + shifter: process (CLK_28M) + begin + if rising_edge(CLK_28M) then + shift_reg <= ram_data_out & shift_reg(5 downto 1); + end if; + end process; + + ram_write_addr <= (not even_line) & hcount(10 downto 1); + ram_we <= '1' when hcount(0) = '1' else '0'; + + video_active <= hactive and not vbl_delayed2; + + pixel_generator: process (CLK_28M) + variable r, g, b : unsigned(7 downto 0); + begin + if rising_edge(CLK_28M) then + + r := X"00"; + g := X"00"; + b := X"00"; + + -- alternate background for monochrome modes + case SCREEN_MODE is + when "00" => + r := X"00"; g := X"00"; b := X"00"; -- color mode background + when "01" => + r := X"00"; g := X"00"; b := X"00"; -- B&W mode background + when "10" => + r := X"00"; g := X"0F"; b := X"01"; -- green mode background color + when "11" => + r := X"20"; g := X"08"; b := X"01"; -- amber mode background color + end case; + + if video_active = '1' then + + if color_line_delayed_2 = '0' then -- Monochrome mode + + if shift_reg(2) = '1' then + -- handle green/amber color modes + case SCREEN_MODE is + when "00" => + r := X"FF"; g := X"FF"; b := X"FF"; -- white (color mode) + when "01" => + r := X"FF"; g := X"FF"; b := X"FF"; -- white (B&W mode) + when "10" => + r := X"00"; g := X"C0"; b := X"01"; -- green + when "11" => + r := X"FF"; g := X"80"; b := X"01"; -- amber + end case; + end if; + + elsif shift_reg(0) = shift_reg(4) and shift_reg(5) = shift_reg(1) then + + -- Tint of adjacent pixels is consistent : display the color + + if shift_reg(1) = '1' then + r := r + basis_r(to_integer(hcount + 1)); + g := g + basis_g(to_integer(hcount + 1)); + b := b + basis_b(to_integer(hcount + 1)); + end if; + if shift_reg(2) = '1' then + r := r + basis_r(to_integer(hcount + 2)); + g := g + basis_g(to_integer(hcount + 2)); + b := b + basis_b(to_integer(hcount + 2)); + end if; + if shift_reg(3) = '1' then + r := r + basis_r(to_integer(hcount + 3)); + g := g + basis_g(to_integer(hcount + 3)); + b := b + basis_b(to_integer(hcount + 3)); + end if; + if shift_reg(4) = '1' then + r := r + basis_r(to_integer(hcount)); + g := g + basis_g(to_integer(hcount)); + b := b + basis_b(to_integer(hcount)); + end if; + else + + -- Tint is changing: display only black, gray, or white + + case shift_reg(3 downto 2) is + when "11" => r := X"FF"; g := X"FF"; b := X"FF"; + when "01" | "10" => r := X"80"; g := X"80"; b := X"80"; + when others => r := X"00"; g := X"00"; b := X"00"; + end case; + end if; + + end if; + + VGA_R <= r; + VGA_G <= g; + VGA_B <= b; + + end if; + end process pixel_generator; + + -- The two-port RAM that stores the line data + line_storage : process (CLK_28M) + begin + if rising_edge(CLK_28M) then + if ram_we = '1' then + line_memory(to_integer(ram_write_addr)) <= VIDEO; + end if; + ram_data_out <= line_memory(to_integer(ram_read_addr)); + end if; + end process line_storage; + + VGA_CLK <= CLK_28M; + VGA_DE <= video_active; + +end rtl; diff --git a/video_generator.vhd b/video_generator.vhd new file mode 100644 index 0000000..e24819f --- /dev/null +++ b/video_generator.vhd @@ -0,0 +1,221 @@ +------------------------------------------------------------------------------- +-- +-- Apple ][ Video Generation Logic +-- +-- Stephen A. Edwards, sedwards@cs.columbia.edu +-- +-- This takes data from memory and various mode switches to produce the +-- serial one-bit video data stream. +-- +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity video_generator is + + port ( + CLK_14M : in std_logic; -- 14.31818 MHz master clock + CLK_7M : in std_logic; + AX : in std_logic; + CAS_N : in std_logic; + TEXT_MODE : in std_logic; + PAGE2 : in std_logic; + HIRES_MODE : in std_logic; + MIXED_MODE : in std_logic; + H0 : in std_logic; + VA : in std_logic; + VB : in std_logic; + VC : in std_logic; + V2 : in std_logic; + V4 : in std_logic; + BLANK : in std_logic; + DL : in unsigned(7 downto 0); -- Data from RAM + LDPS_N : in std_logic; + LD194 : in std_logic; + FLASH_CLK : in std_logic; -- Low-frequency flashing text clock + HIRES : out std_logic; + VIDEO : out std_logic; + COLOR_LINE : out std_logic + ); + +end video_generator; + +architecture rtl of video_generator is + + signal char_rom_addr : unsigned(8 downto 0); + signal char_rom_out : unsigned(4 downto 0); + signal text_shiftreg : unsigned(5 downto 0); + signal invert_character : std_logic; + signal text_pixel : std_logic; -- B2 p11 + signal blank_delayed : std_logic; + signal video_sig : std_logic; -- output of B10 p5 + signal graph_shiftreg : unsigned(7 downto 0); + signal graphics_time_1, graphics_time_2, + graphics_time_3 : std_logic; -- B5 p2, B8 p15, B8 p2 + signal lores_time : std_logic; -- A11 p6 + signal pixel_select : std_logic_vector(1 downto 0); -- A10 p14, A10 p15 + signal hires_delayed : std_logic; -- A11 p9 + +begin + + ----------------------------------------------------------------------------- + -- + -- Text Mode Circuitry + -- + -- The character ROM drives a parallel-to-serial shift register + -- whose output is selectively inverted by inverted or flashing text + -- + ----------------------------------------------------------------------------- + + char_rom_addr <= DL(5 downto 0) & VC & VB & VA; + + thecharrom : entity work.character_rom + port map( + addr => char_rom_addr, + clk => CLK_14M, -- FIXME: a lower frequency? + dout => char_rom_out + ); + + -- Parallel-to-serial shifter for text mode + -- The Apple actually used LDPS_N as the clock, not 14M; this is equivalent + A3_74166: process (CLK_14M) + begin + if rising_edge(CLK_14M) then + if CLK_7M = '0' then + if LDPS_N = '0' then -- load + text_shiftreg <= char_rom_out & "0"; + else -- shift + text_shiftreg <= '0' & text_shiftreg(5 downto 1); + end if; + end if; + end if; + end process; + + -- Latch and decoder for flashing/inverted text + -- Comprises part of B11, B13, and A10 + flash_invert : process (CLK_14M) + begin + if rising_edge(CLK_14M) then + if LD194 = '0' then + invert_character <= not (DL(7) or (DL(6) and FLASH_CLK)); + end if; + end if; + end process; + + text_pixel <= text_shiftreg(0) xor invert_character; + + ----------------------------------------------------------------------------- + -- + -- Lores and Hires Mode Circuitry + -- + -- An eight-bit shift register that either shifts (hires mode) or rotates + -- the two nibbles (lores) followed by a mux that selects the video + -- data from the text mode display, the hires shift register (possibly + -- delayed by a 14M clock pulse), or one of the bits in the lores shift + -- register. + -- + ----------------------------------------------------------------------------- + + -- Original Apple clocked this shift register on the rising edge of RAS_N + B5B8_74LS174 : process (CLK_14M) + begin + if rising_edge(CLK_14M) then + if AX = '1' and CAS_N = '0' then + graphics_time_3 <= graphics_time_2; + graphics_time_2 <= graphics_time_1; + graphics_time_1 <= not (TEXT_MODE or (V2 and V4 and MIXED_MODE)); + end if; + end if; + end process; + + COLOR_LINE <= graphics_time_1; + + HIRES <= HIRES_MODE and graphics_time_3; -- to address generator + + lores_time <= not HIRES_MODE and graphics_time_3; + + A8A10_74LS194 : process (CLK_14M) + begin + if rising_edge(CLK_14M) then + if LD194 = '0' then + if lores_time = '1' then -- LORES mode + pixel_select <= VC & H0; + else -- HIRES mode + pixel_select <= graphics_time_1 & DL(7); + end if; + end if; + end if; + end process; + + -- Shift hires pixels by one 14M cycle to get orange and blue + A11_74LS74 : process (CLK_14M) + begin + if rising_edge(CLK_14M) then + hires_delayed <= graph_shiftreg(0); + end if; + end process; + + -- A pair of four-bit universal shift registers that either + -- shift the whole byte (hires mode) or rotate the two nibbles (lores mode) + B4B9_74LS194 : process (CLK_14M) + begin + if rising_edge(CLK_14M) then + if LD194 = '0' then + graph_shiftreg <= DL; + else + if lores_time = '1' then -- LORES configuration + graph_shiftreg <= graph_shiftreg(4) & graph_shiftreg(7 downto 5) & + graph_shiftreg(0) & graph_shiftreg(3 downto 1); + else -- HIRES configuration + if CLK_7M = '0' then + graph_shiftreg <= graph_shiftreg(4) & graph_shiftreg(7 downto 1); + end if; + end if; + end if; + end if; + end process; + + -- Synchronize BLANK to LD194 + A10_74LS194: process (CLK_14M) + begin + if rising_edge(CLK_14M) then + if LD194 = '0' then + blank_delayed <= BLANK; + end if; + end if; + end process; + + -- Video output mux and flip-flop + A9B10_74LS151 : process (CLK_14M) + begin + if rising_edge(CLK_14M) then + if blank_delayed = '0' then + if lores_time = '1' then -- LORES mode + case pixel_select is + when "00" => video_sig <= graph_shiftreg(0); + when "01" => video_sig <= graph_shiftreg(2); + when "10" => video_sig <= graph_shiftreg(4); + when "11" => video_sig <= graph_shiftreg(6); + when others => video_sig <= 'X'; + end case; + else + if pixel_select(1) = '0' then -- TEXT mode + video_sig <= text_pixel; + else -- HIRES mode + if pixel_select(0) = '1' then + video_sig <= hires_delayed; + else + video_sig <= graph_shiftreg(0); + end if; + end if; + end if; + else + video_sig <= '0'; + end if; + end if; + end process; + + VIDEO <= video_sig; + +end rtl;