diff --git a/.gitignore b/.gitignore
index 93fd271..a80016f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -35,3 +35,5 @@ c5_pin_model_dump.txt
 *.bsf
 *~
 *.xml
+*_netlist
+*.cdf
diff --git a/Apple-II-lite.qsf b/Apple-II-lite.qsf
index 7399446..a76a32e 100644
--- a/Apple-II-lite.qsf
+++ b/Apple-II-lite.qsf
@@ -50,7 +50,7 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
 set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
 set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
-set_global_assignment -name FITTER_EFFORT "FAST FIT"
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
 set_global_assignment -name OPTIMIZATION_MODE BALANCED
 set_global_assignment -name SEED 1
 
@@ -353,9 +353,8 @@ set_location_assignment PIN_W20 -to SW[3]
 
 set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
 
-set_global_assignment -name CDF_FILE jtag_lite.cdf
+set_global_assignment -name CDF_FILE jtag.cdf
 set_global_assignment -name QIP_FILE sys/sys.qip
-set_global_assignment -name QIP_FILE sys/sysmem.qip
 set_global_assignment -name VHDL_FILE mockingboard/YM2149_volmix.vhd
 set_global_assignment -name VHDL_FILE mockingboard/vol_table_array.vhd
 set_global_assignment -name VHDL_FILE mockingboard/mockingboard.vhd
@@ -374,5 +373,5 @@ set_global_assignment -name VHDL_FILE vga_controller.vhd
 set_global_assignment -name VHDL_FILE PS2_Ctrl.vhd
 set_global_assignment -name VHDL_FILE roms.vhd
 set_global_assignment -name VHDL_FILE apple2_top.vhd
-set_global_assignment -name SYSTEMVERILOG_FILE Apple-II.sv
+set_global_assignment -name SYSTEMVERILOG_FILE "Apple-II.sv"
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/Apple-II.qsf b/Apple-II.qsf
index b5be6af..127c25e 100644
--- a/Apple-II.qsf
+++ b/Apple-II.qsf
@@ -49,7 +49,7 @@ set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
 set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
 set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
 set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name OPTIMIZATION_MODE BALANCED
+set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
 set_global_assignment -name SEED 1
 
 #============================================================
@@ -353,7 +353,7 @@ set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:sys/build_id.tcl"
 
 set_global_assignment -name CDF_FILE jtag.cdf
 set_global_assignment -name QIP_FILE sys/sys.qip
-set_global_assignment -name QIP_FILE sys/vip.qip
+set_global_assignment -name QSYS_FILE sys/vip.qsys
 set_global_assignment -name VHDL_FILE mockingboard/YM2149_volmix.vhd
 set_global_assignment -name VHDL_FILE mockingboard/vol_table_array.vhd
 set_global_assignment -name VHDL_FILE mockingboard/mockingboard.vhd
diff --git a/Apple-II.srf b/Apple-II.srf
index 04c03cc..35a7eff 100644
--- a/Apple-II.srf
+++ b/Apple-II.srf
@@ -1,51 +1,29 @@
+{ "" "" "" "Vip.Mixer: The MixerII register map changed in ACDS v16.0. Please refer to the VIP User Guide for details." {  } {  } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Vip.Reset_Source.reset_sys: Associated reset sinks not declared" {  } {  } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Vip.Reset_Source.reset_warm: Associated reset sinks not declared" {  } {  } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Vip.Reset_Source.reset_cold: Associated reset sinks not declared" {  } {  } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Vip.Video_Output.control: Interrupt sender control.av_mm_control_interrupt is not connected to an interrupt receiver" {  } {  } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Vip.Video_Output: Interrupt sender Video_Output.status_update_irq is not connected to an interrupt receiver" {  } {  } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Vip.: You have exported the interface HPS.f2h_sdram1_data but not its associated reset interface.  Export the driver(s) of HPS.h2f_reset" {  } {  } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Vip.: You have exported the interface HPS.f2h_sdram2_data but not its associated reset interface.  Export the driver(s) of HPS.h2f_reset" {  } {  } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "Variable or input pin \"data_b\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Found combinational loop of 47 nodes" {  } {  } 0 332125 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" {  } {  } 0 12110 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." {  } {  } 0 17897 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic.  Pass-through logic has been added to match the read-during-write behavior of the original design." {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" {  } {  } 0 10036 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "Variable or input pin \"data_a\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 169085 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 174073 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 332174 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 13009 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "*" {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_cvo_mode_banks" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_pll.sv" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2.  The extra bits will be left dangling without any fan-out logic." {  } {  } 0 12030 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Port \"trs\" on the entity instantiation of \"statemachine\" is connected to a signal of width 2. The formal width of the signal in the module is 1.  The extra bits will be ignored." {  } {  } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Port \"reset_value\" on the entity instantiation of \"h_counter\" is connected to a signal of width 32. The formal width of the signal in the module is 16.  The extra bits will be ignored." {  } {  } 0 12020 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" {  } {  } 0 332043 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Vip.vip: Module dependency loop involving: \"HPS\"" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "alt_vip_common_frame_counter.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_ldc.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "alt_vip_cvo_mode_banks.sv" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "altera_pll.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "altera_cyclonev_pll.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "altera_pll_reconfig_core.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "genlock_enable_sync" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "u_calculate_mode" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "genlock_enable" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "reset_value" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "mode_banks" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "RST port on the PLL is not properly connected" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "alt_vip_cvo_core.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "alt_vip_packet_transfer.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "hps_sdram_p0.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "RST" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_scaler_alg_core" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "cvo_core" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
 { "" "" "" "vip_HPS_fpga_interfaces.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
-{ "" "" "" "alt_vip_dil_scheduler.sdc" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
diff --git a/Apple-II.sv b/Apple-II.sv
index 35f43a6..ff56c3a 100644
--- a/Apple-II.sv
+++ b/Apple-II.sv
@@ -2,7 +2,7 @@
 //  Apple II+
 //
 //  Port to MiSTer
-//  Copyright (C) 2017 Sorgelig
+//  Copyright (C) 2017,2018 Sorgelig
 //
 //  This program is free software; you can redistribute it and/or modify it
 //  under the terms of the GNU General Public License as published by the Free
@@ -29,7 +29,7 @@ module emu
 	input         RESET,
 
 	//Must be passed to hps_io module
-	inout  [43:0] HPS_BUS,
+	inout  [44:0] HPS_BUS,
 
 	//Base video clock. Usually equals to CLK_SYS.
 	output        CLK_VIDEO,
@@ -51,7 +51,7 @@ module emu
 
 	output        LED_USER,  // 1 - ON, 0 - OFF.
 
-	// b[1]: 0 - LED status is system status ORed with b[0]
+	// b[1]: 0 - LED status is system status OR'd with b[0]
 	//       1 - LED status is controled solely by b[0]
 	// hint: supply 2'b00 to let the system control the LED.
 	output  [1:0] LED_POWER,
@@ -60,6 +60,7 @@ module emu
 	output [15:0] AUDIO_L,
 	output [15:0] AUDIO_R,
 	output        AUDIO_S, // 1 - signed audio samples, 0 - unsigned
+	output  [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
 	input         TAPE_IN,
 
 	// SD-SPI
@@ -67,6 +68,7 @@ module emu
 	output        SD_MOSI,
 	input         SD_MISO,
 	output        SD_CS,
+	input         SD_CD,
 
 	//High latency DDR3 RAM interface
 	//Use for non-critical time purposes
@@ -116,6 +118,7 @@ parameter CONF_STR = {
 	"O23,Display,Color,B&W,Green,Amber;",
 	"-;",
 	"O4,Mocking board,Yes,No;",
+	"O78,Stereo mix,none,25%,50%,100%;",
 	"-;",
 	"T6,Reset;",
 	"J,Fire 1,Fire 2;",
@@ -205,6 +208,7 @@ wire speaker;
 assign AUDIO_L = {1'b0, audio_l, 7'd0} + {2'b0, speaker, 13'd0};
 assign AUDIO_R = {1'b0, audio_r, 7'd0} + {2'b0, speaker, 13'd0};
 assign AUDIO_S = 0;
+assign AUDIO_MIX = status[8:7];
 
 assign CLK_VIDEO = clk_vid;
 assign CE_PIXEL = 1;
diff --git a/clean.bat b/clean.bat
index 3c54b34..7ac8e34 100644
--- a/clean.bat
+++ b/clean.bat
@@ -13,8 +13,6 @@ rmdir /s /q .qsys_edit
 rmdir /s /q hps_isw_handoff
 rmdir /s /q sys\.qsys_edit
 rmdir /s /q sys\vip
-rmdir /s /q diskemu\.qsys_edit
-rmdir /s /q diskemu\diskemu
 cd sys
 for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
 cd ..
@@ -33,7 +31,8 @@ del /s *.bsf
 del /s *.f
 del /s *.sopcinfo
 del /s *.xml
+del *.cdf
+del *.rpt
 del /s new_rtl_netlist
 del /s old_rtl_netlist
-
 pause
diff --git a/jtag.cdf b/jtag.cdf
deleted file mode 100644
index 0f00f29..0000000
--- a/jtag.cdf
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition */
-JedecChain;
-	FileRevision(JESD32A);
-	DefaultMfr(6E);
-
-	P ActionCode(Ign)
-		Device PartName(SOCVHPS) MfrSpec(OpMask(0));
-	P ActionCode(Cfg)
-		Device PartName(5CSEBA6U23) Path("output_files/") File("Apple-II.sof") MfrSpec(OpMask(1));
-
-ChainEnd;
-
-AlteraBegin;
-	ChainType(JTAG);
-AlteraEnd;
diff --git a/jtag_lite.cdf b/jtag_lite.cdf
deleted file mode 100644
index 8e64228..0000000
--- a/jtag_lite.cdf
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition */
-JedecChain;
-	FileRevision(JESD32A);
-	DefaultMfr(6E);
-
-	P ActionCode(Ign)
-		Device PartName(SOCVHPS) MfrSpec(OpMask(0));
-	P ActionCode(Cfg)
-		Device PartName(5CSEBA6U23) Path("output_files/") File("Apple-II-lite.sof") MfrSpec(OpMask(1));
-
-ChainEnd;
-
-AlteraBegin;
-	ChainType(JTAG);
-AlteraEnd;
diff --git a/spram.vhd b/spram.vhd
deleted file mode 100644
index 3e306f8..0000000
--- a/spram.vhd
+++ /dev/null
@@ -1,90 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY spram IS
-	GENERIC
-	(
-		init_file			: string := "";
-		widthad_a			: natural;
-		width_a				: natural := 8;
-    outdata_reg_a : string := "UNREGISTERED"
-	);
-	PORT
-	(
-		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
-		clock		: IN STD_LOGIC ;
-		data		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-		wren		: IN STD_LOGIC ;
-		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
-	);
-END spram;
-
-
-ARCHITECTURE SYN OF spram IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-
-
-
-	COMPONENT altsyncram
-	GENERIC (
-		clock_enable_input_a		: STRING;
-		clock_enable_output_a		: STRING;
-		init_file		: STRING;
-		intended_device_family		: STRING;
-		lpm_hint		: STRING;
-		lpm_type		: STRING;
-		numwords_a		: NATURAL;
-		operation_mode		: STRING;
-		outdata_aclr_a		: STRING;
-		outdata_reg_a		: STRING;
-		power_up_uninitialized		: STRING;
-		read_during_write_mode_port_a		: STRING;
-		widthad_a		: NATURAL;
-		width_a		: NATURAL;
-		width_byteena_a		: NATURAL
-	);
-	PORT (
-			wren_a	: IN STD_LOGIC ;
-			clock0	: IN STD_LOGIC ;
-			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
-			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
-			data_a	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
-	);
-	END COMPONENT;
-
-BEGIN
-	q    <= sub_wire0(width_a-1 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		clock_enable_input_a => "BYPASS",
-		clock_enable_output_a => "BYPASS",
-		init_file => init_file,
-		intended_device_family => "Cyclone III",
-		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
-		lpm_type => "altsyncram",
-		numwords_a => 49152,
-		operation_mode => "SINGLE_PORT",
-		outdata_aclr_a => "NONE",
-		outdata_reg_a => outdata_reg_a,
-		power_up_uninitialized => "FALSE",
-		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
-		widthad_a => widthad_a,
-		width_a => width_a,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		wren_a => wren,
-		clock0 => clock,
-		address_a => address,
-		data_a => data,
-		q_a => sub_wire0
-	);
-
-
-
-END SYN;
diff --git a/sys/build_id.tcl b/sys/build_id.tcl
index 7ef0665..3705e4c 100644
--- a/sys/build_id.tcl
+++ b/sys/build_id.tcl
@@ -1,15 +1,6 @@
-# ================================================================================
-#
-# Build ID Verilog Module Script
-# Jeff Wiencrot - 8/1/2011
-#
-# Generates a Verilog module that contains a timestamp,
-# from the current build. These values are available from the build_date, build_time,
-# physical_address, and host_name output ports of the build_id module in the build_id.v
-# Verilog source file.
-#
-# ================================================================================
 
+# Build TimeStamp Verilog Module
+# Jeff Wiencrot - 8/1/2011
 proc generateBuildID_Verilog {} {
 
 	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
@@ -31,5 +22,48 @@ proc generateBuildID_Verilog {} {
 	post_message "Time:             $buildTime"
 }
 
-# Comment out this line to prevent the process from automatically executing when the file is sourced:
-generateBuildID_Verilog
\ No newline at end of file
+# Build CDF file
+# Sorgelig - 17/2/2018
+proc generateCDF {revision device outpath} {
+
+	set outputFileName "jtag.cdf"
+	set outputFile [open $outputFileName "w"]
+
+	puts $outputFile "JedecChain;"
+	puts $outputFile "	FileRevision(JESD32A);"
+	puts $outputFile "	DefaultMfr(6E);"
+	puts $outputFile ""
+	puts $outputFile "	P ActionCode(Ign)"
+	puts $outputFile "		Device PartName(SOCVHPS) MfrSpec(OpMask(0));"
+	puts $outputFile "	P ActionCode(Cfg)"
+	puts $outputFile "		Device PartName($device) Path(\"$outpath/\") File(\"$revision.sof\") MfrSpec(OpMask(1));"
+	puts $outputFile "ChainEnd;"
+	puts $outputFile ""
+	puts $outputFile "AlteraBegin;"
+	puts $outputFile "	ChainType(JTAG);"
+	puts $outputFile "AlteraEnd;"
+}
+
+set project_name [lindex $quartus(args) 1]
+set revision [lindex $quartus(args) 2]
+
+if {[project_exists $project_name]} {
+    if {[string equal "" $revision]} {
+        project_open $project_name -revision [get_current_revision $project_name]
+    } else {
+        project_open $project_name -revision $revision
+    }
+} else {
+    post_message -type error "Project $project_name does not exist"
+    exit
+}
+
+set device  [get_global_assignment -name DEVICE]
+set outpath [get_global_assignment -name PROJECT_OUTPUT_DIRECTORY]
+
+if [is_project_open] {
+    project_close
+}
+
+generateBuildID_Verilog
+generateCDF $revision $device $outpath
diff --git a/sys/ddram.sv b/sys/ddram.sv
deleted file mode 100644
index 21a1ed6..0000000
--- a/sys/ddram.sv
+++ /dev/null
@@ -1,132 +0,0 @@
-//
-// ddram.v
-//
-// DE10-nano DDR3 memory interface
-//
-// Copyright (c) 2017 Sorgelig
-//
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version. 
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-// ------------------------------------------
-//
-
-// 8-bit version
-
-module ddram
-(
-	input         reset,
-	input         DDRAM_CLK,
-
-	input         DDRAM_BUSY,
-	output  [7:0] DDRAM_BURSTCNT,
-	output [28:0] DDRAM_ADDR,
-	input  [63:0] DDRAM_DOUT,
-	input         DDRAM_DOUT_READY,
-	output        DDRAM_RD,
-	output [63:0] DDRAM_DIN,
-	output  [7:0] DDRAM_BE,
-	output        DDRAM_WE,
-
-   input  [27:0] addr,        // 256MB at the end of 1GB
-   output  [7:0] dout,        // data output to cpu
-   input   [7:0] din,         // data input from cpu
-   input         we,          // cpu requests write
-   input         rd,          // cpu requests read
-   output        ready        // dout is valid. Ready to accept new read/write.
-);
-
-assign DDRAM_BURSTCNT = 1;
-assign DDRAM_BE       = (8'd1<<ram_address[2:0]) | {8{ram_read}};
-assign DDRAM_ADDR     = {4'b0011, ram_address[27:3]}; // RAM at 0x30000000
-assign DDRAM_RD       = ram_read;
-assign DDRAM_DIN      = ram_cache;
-assign DDRAM_WE       = ram_write;
-
-assign dout = ram_q;
-assign ready = ~busy;
-
-reg  [7:0] ram_q;
-reg [27:0] ram_address;
-reg        ram_read;
-reg [63:0] ram_cache;
-reg        ram_write;
-reg  [7:0] cached;
-reg        busy;
-
-
-always @(posedge DDRAM_CLK)
-begin
-	reg old_rd, old_we;
-	reg old_reset;
-	reg state;
-
-	old_reset <= reset;
-	if(old_reset && ~reset)
-	begin
-		busy   <= 0;
-		state  <= 0;
-		cached <= 0;
-	end
-
-	if(!DDRAM_BUSY)
-	begin
-		ram_write <= 0;
-		ram_read  <= 0;
-		if(state)
-		begin
-			if(DDRAM_DOUT_READY)
-			begin
-				ram_q     <= DDRAM_DOUT[{ram_address[2:0], 3'b000} +:8];
-				ram_cache <= DDRAM_DOUT;
-				cached    <= 8'hFF;
-				state     <= 0;
-				busy      <= 0;
-			end
-		end
-		else
-		begin
-			old_rd <= rd;
-			old_we <= we;
-			busy   <= 0;
-
-			if(~old_we && we)
-			begin
-				ram_cache[{addr[2:0], 3'b000} +:8] <= din;
-				ram_address <= addr;
-				busy        <= 1;
-				ram_write 	<= 1;
-				cached      <= ((ram_address[27:3] == addr[27:3]) ? cached : 8'h00) | (8'd1<<addr[2:0]);
-			end
-
-			if(~old_rd && rd)
-			begin
-				busy <= 1;
-				if((ram_address[27:3] == addr[27:3]) && (cached & (8'd1<<addr[2:0])))
-				begin
-					ram_q <= ram_cache[{addr[2:0], 3'b000} +:8];
-				end
-				else
-				begin
-					ram_address <= addr;
-					ram_read    <= 1;
-					state       <= 1;
-					cached      <= 0;
-				end
-			end
-		end
-	end
-end
-
-endmodule
diff --git a/sys/hdmi_config.sv b/sys/hdmi_config.sv
index dbc0dfd..0321792 100644
--- a/sys/hdmi_config.sv
+++ b/sys/hdmi_config.sv
@@ -5,19 +5,8 @@ module hdmi_config
 	input			iCLK,
 	input			iRST_N,
 	
-	// 0 - 480i
-	// 1 - 480p
-	// 2 - 576i
-	// 3 - 576p
-	// 4 - 720p
-	// 5-7 - reserved
-	input [2:0] iRES,
-	
-	// 0 - 4:3
-	// 1 - 16:9
-	input       iAR,
-	
-	input       audio_48k,
+	input       dvi_mode,
+	input       audio_96k,
 
 	//	I2C Side
 	output		I2C_SCL,
@@ -31,7 +20,7 @@ wire       mI2C_ACK;
 reg [15:0] LUT_DATA;
 reg  [7:0] LUT_INDEX = 0;
 
-I2C_Controller #(50_000_000, 400_000) i2c_av
+i2c #(50_000_000, 20_000) i2c_av
 (
 	.CLK(iCLK),
 
@@ -72,32 +61,20 @@ always@(posedge iCLK or negedge iRST_N) begin
 	end
 end
 
-wire [15:0] res480i[6] = '{'h35_1D, 'h36_92, 'h37_05, 'h38_A0, 'h39_0F, 'h3A_00};
-wire [15:0] res480p[6] = '{'h35_1F, 'h36_E8, 'h37_05, 'h38_A0, 'h39_1E, 'h3A_00};
-wire [15:0] res576i[6] = '{'h35_20, 'h36_D6, 'h37_05, 'h38_A0, 'h39_12, 'h3A_00};
-wire [15:0] res576p[6] = '{'h35_20, 'h36_EC, 'h37_05, 'h38_A0, 'h39_24, 'h3A_00};
-wire [15:0] res720p[6] = '{'h35_40, 'h36_D9, 'h37_0A, 'h38_00, 'h39_2D, 'h3A_00};
-
-reg  [15:0] resVar[6];
-always_comb begin
-	case(iRES)
-		0: resVar <= res480i;
-		1: resVar <= res480p;
-		2: resVar <= res576i;
-		3: resVar <= res576p;
-		4: resVar <= res720p;
-		default: resVar <= res720p;
-	endcase
-end
-
-
 ////////////////////////////////////////////////////////////////////
-/////////////////////	Config Data LUT	  //////////////////////////
+/////////////////////	Config Data LUT   //////////////////////////
 
 wire [15:0] init_data[58] = 
 '{
-	16'h4110,					// Power Down control
 	16'h9803,					// ADI required Write.
+
+	{8'hD6, 8'b1100_0000},	// [7:6] HPD Control...
+									// 00 = HPD is from both HPD pin or CDC HPD
+									// 01 = HPD is from CDC HPD
+									// 10 = HPD is from HPD pin
+									// 11 = HPD is always high
+
+	16'h4110,					// Power Down control
 	16'h9A70,					// ADI required Write.
 	16'h9C30,					// ADI required Write.
 	{8'h9D, 8'b0110_0001},	// [7:4] must be b0110!.
@@ -108,13 +85,13 @@ wire [15:0] init_data[58] =
 	16'hE0D0,					// ADI required Write.
 
 
-	resVar[0],
-	resVar[1],
-	resVar[2],
-	resVar[3],
-	resVar[4],
-	resVar[5],
-	
+	16'h35_40,
+	16'h36_D9,
+	16'h37_0A,
+	16'h38_00,
+	16'h39_2D,
+	16'h3A_00,
+
 	{8'h16, 8'b0011_1000},	// Output Format 444 [7]=0.
 									// [6] must be 0!
 									// Colour Depth for Input Video data [5:4] b11 = 8-bit.
@@ -122,39 +99,15 @@ wire [15:0] init_data[58] =
 									// DDR Input Edge falling [1]=0 (not using DDR atm).
 									// Output Colour Space RGB [0]=0.
 
-//	{8'h16, 8'b1011_0101},	// Output Format 422 [7]=1.
-									// [6] must be 0!
-									// Colour Depth for Input Video data [5:4] b11 = 8-bit.
-									// Input Style [3:2] b01 = Style 2.
-									// DDR Input Edge falling [1]=0 (not using DDR atm).
-									// Output Colour Space YPrPb [0]=1.
-
-//	{8'h17, 8'b0110_0000},	// Aspect ratio 4:3 [1]=0. DE Generation DISabled [0]=0.
-									// Vsync polarity HIGH [6]=0, LOW [6]=1.
-									// Hsync polarity HIGH [5]=0, LOW [5]=1.
-
-//	{8'h17, 8'b0110_0001},	// Aspect ratio 4:3 [1]=0. DE Generation ENabled [0]=1.
-
-//	{8'h17, 8'b0110_0011},	// Aspect ratio 16:9 [1]=1. DE Generation ENabled [0]=1.
-
-	{8'h17, 6'b011000, iAR, 1'b0}, // Aspect ratio 16:9 [1]=1, 4:3 [1]=0
+	{8'h17, 8'b01100010},   // Aspect ratio 16:9 [1]=1, 4:3 [1]=0
 
 	{8'h18, 8'b0100_0110},	// CSC disabled [7]=0.
 									// CSC Scaling Factor [6:5] b10 = +/- 4.0, -16384 - 16380.
 									// CSC Equation 3 [4:0] b00110.
 
 
-//	{8'h3B, 8'b0000_1010},	// Pixel repetition [6:5] b00 AUTO. [4:3] b01 x2 mult of input clock. [2:1] b01 x2 pixel rep to send to HDMI Rx.
-
 	{8'h3B, 8'b0000_0000},	// Pixel repetition [6:5] b00 AUTO. [4:3] b00 x1 mult of input clock. [2:1] b00 x1 pixel rep to send to HDMI Rx.
 
-//	{8'h3B, 8'b0110_1010},	// Pixel repetition [6:5] b11 MANUAL. [4:3] b01 x2 mult of input clock. [2:1] b01 x2 pixel rep to send to HDMI Rx.
-
-//	{8'h3C, 8'b0000_0110},	// VIC#6 480i-60, 2x clk, 4:3.
-//	{8'h3C, 8'b0000_0001},	// VIC#1 VGA (640x480), 2x clk, 4:3.
-
-//	{8'h3C, 8'b0000_0010},	// VIC#2 480p (720x480), 2x clk, 4:3.
-
 	16'h4000,					// General Control Packet Enable
 
 	{8'h48, 8'b0000_1000},	// [6]=0 Normal bus order!
@@ -165,24 +118,20 @@ wire [15:0] init_data[58] =
 	16'h4C00,					// ADI required Write.
 
 	{8'h55, 8'b0001_0000},	// [7] must be 0!. Set RGB444 in AVinfo Frame [6:5], Set active format [4].
-//	{8'h55, 8'b0101_0000},	// [7] must be 0!. Set YCbCr 444 in AVinfo Frame [6:5], Set active format [4].
-//	{8'h55, 8'b0011_0001},	// [7] must be 0!. Set YCbCr 422 in AVinfo Frame [6:5].
 									// AVI InfoFrame Valid [4].
 									// Bar Info [3:2] b00 Bars invalid. b01 Bars vertical. b10 Bars horizontal. b11 Bars both.
 									// Scan Info [1:0] b00 (No data). b01 TV. b10 PC. b11 None.
 
-//	{8'h94, 8'b1000_0000},	// [7]=1 HPD Interrupt ENabled.
-
 	16'h7301,
 
-	16'h9400,					// HPD Interrupt disabled.
+	{8'h94, 8'b1000_0000},	// [7]=1 HPD Interrupt ENabled.
 
 	16'h9902,					// ADI required Write.
 	16'h9B18,					// ADI required Write.
 
 	16'h9F00,					// ADI required Write.
 
-	{8'hA1, 8'b0100_0000},	// [6]=1 Monitor Sense Power Down DISabled.
+	{8'hA1, 8'b0000_0000},	// [6]=1 Monitor Sense Power Down DISabled.
 	
 	16'hA408,					// ADI required Write.
 	16'hA504,					// ADI required Write.
@@ -193,7 +142,7 @@ wire [15:0] init_data[58] =
 	16'hAA00,					// ADI required Write.
 	16'hAB40,					// ADI required Write.
 	
-	{8'hAF, 8'b0001_0110},	// [7]=0 HDCP Disabled.
+	{8'hAF, 6'b0001_01,~dvi_mode,1'b0},	// [7]=0 HDCP Disabled.
 									// [6:5] must be b00!
 									// [4]=1 Current frame IS HDCP encrypted!??? (HDCP disabled anyway?)
 									// [3:2] must be b01!
@@ -214,12 +163,6 @@ wire [15:0] init_data[58] =
 					
 	16'hBB00,					// ADI required Write.
 	
-	{8'hD6, 8'b1100_0000},	// [7:6] HPD Control...
-									// 00 = HPD is from both HPD pin or CDC HPD
-									// 01 = HPD is from CDC HPD
-									// 10 = HPD is from HPD pin
-									// 11 = HPD is always high
-	
 	16'hDE9C,					// ADI required Write.
 	16'hE460,					// ADI required Write.
 	16'hFA7D,					// Nbr of times to search for good phase
@@ -239,18 +182,12 @@ wire [15:0] init_data[58] =
 									
 	{8'h0D, 8'b0001_0000},	// [4:0] I2S Bit (Word) Width for Right-Justified.
 	{8'h14, 8'b0000_0010},	// [3:0] Audio Word Length. b0010 = 16 bits.
-	{8'h15, ~audio_48k, 7'b010_0000},	// I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
+	{8'h15, audio_96k, 7'b010_0000},	// I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
 									// Input ID [3:1] b000 (0) = 24-bit RGB 444 or YCrCb 444 with Separate Syncs.
-									
-//	{8'h15, 8'b0010_0001},	// I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
-									// Input ID [3:0] b0001 (1) = 16, 20, 24 bit YCbCr 4:2:2 with Separate Syncs.
 
-//	{8'h15, 8'b0010_0011},	// I2S Sampling Rate [7:4]. b0000 = (44.1KHz). b0010 = 48KHz.
-									// Input ID [3:0] b0011 (3) = 16, 20, 24 bit YCbCr 4:2:2 (2x Pixel Clock, with Separate Syncs).
-	
 	// Audio Clock Config
 	16'h0100,					//  
-	audio_48k ? 16'h0218 : 16'h0230,	// Set N Value 12288/6144
+	audio_96k ? 16'h0230 : 16'h0218,	// Set N Value 12288/6144
 	16'h0300,					//
 
 	16'h0701,					//
diff --git a/sys/hdmi_lite.sv b/sys/hdmi_lite.sv
new file mode 100644
index 0000000..96eb441
--- /dev/null
+++ b/sys/hdmi_lite.sv
@@ -0,0 +1,395 @@
+//============================================================================
+//
+//  HDMI Lite output module
+//  Copyright (C) 2017 Sorgelig
+//
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
+//
+//============================================================================
+
+
+module hdmi_lite
+(
+	input          reset,
+
+	input          clk_video,
+	input          ce_pixel,
+	input          video_vs,
+	input          video_de,
+	input   [23:0] video_d,
+
+	input          clk_hdmi,
+	input          hdmi_hde,
+	input          hdmi_vde,
+	output reg     hdmi_de,
+	output  [23:0] hdmi_d,
+
+	input   [11:0] screen_w,
+	input   [11:0] screen_h,
+	input          quadbuf,
+
+	// 0-3 => scale 1-4
+	input    [1:0] scale_x,
+	input    [1:0] scale_y,
+	input          scale_auto,
+
+	input          clk_vbuf,
+	output  [27:0] vbuf_address,
+	input  [127:0] vbuf_readdata,
+	output [127:0] vbuf_writedata,
+	output   [7:0] vbuf_burstcount,
+	output  [15:0] vbuf_byteenable,
+	input          vbuf_waitrequest,
+	input          vbuf_readdatavalid,
+	output reg     vbuf_read,
+	output reg     vbuf_write
+);
+
+localparam  [7:0] burstsz  = 64;
+
+reg   [1:0] nbuf = 0;
+wire [27:0] read_buf  = {4'd2, 3'b000, (quadbuf ? nbuf-2'd1 : 2'b00), 19'd0};
+wire [27:0] write_buf = {4'd2, 3'b000, (quadbuf ? nbuf+2'd1 : 2'b00), 19'd0};
+
+assign vbuf_address    = vbuf_write ? vbuf_waddress    : vbuf_raddress;
+assign vbuf_burstcount = vbuf_write ? vbuf_wburstcount : vbuf_rburstcount;
+
+wire [95:0] hf_out;
+wire  [7:0] hf_usedw;
+reg         hf_reset = 0;
+
+vbuf_fifo out_fifo
+(
+	.aclr(hf_reset),
+
+	.wrclk(clk_vbuf),
+	.wrreq(vbuf_readdatavalid),
+	.data({vbuf_readdata[96+:24],vbuf_readdata[64+:24],vbuf_readdata[32+:24],vbuf_readdata[0+:24]}),
+	.wrusedw(hf_usedw),
+
+	.rdclk(~clk_hdmi),
+	.rdreq(hf_rdreq),
+	.q(hf_out)
+);
+
+reg [11:0] rd_stride;
+wire [7:0] rd_burst = (burstsz < rd_stride) ? burstsz : rd_stride[7:0];
+
+reg [27:0] vbuf_raddress;
+reg  [7:0] vbuf_rburstcount;
+always @(posedge clk_vbuf) begin
+	reg [18:0] rdcnt;
+	reg  [7:0] bcnt;
+	reg        vde1, vde2;
+	reg  [1:0] mcnt;
+	reg  [1:0] my;
+	reg [18:0] fsz; 
+	reg [11:0] strd;
+
+	vde1 <= hdmi_vde;
+	vde2 <= vde1;
+
+	if(vbuf_readdatavalid) begin
+		rdcnt <= rdcnt + 1'd1;
+		if(bcnt) bcnt <= bcnt - 1'd1;
+		vbuf_raddress <= vbuf_raddress + 1'd1;
+	end
+
+	if(!bcnt && reading) reading <= 0;
+
+	vbuf_read <= 0;
+	if(~vbuf_waitrequest) begin
+		if(!hf_reset && rdcnt<fsz && !bcnt && hf_usedw < burstsz && allow_rd) begin
+			vbuf_read <= 1;
+			reading   <= 1;
+			bcnt <= rd_burst;
+			vbuf_rburstcount <= rd_burst;
+			rd_stride <= rd_stride - rd_burst;
+			if(!(rd_stride - rd_burst)) rd_stride <= strd;
+
+			if(!rdcnt) begin
+				vbuf_raddress <= read_buf;
+				mcnt <= my;
+			end
+			else if (rd_stride == strd) begin
+				mcnt <= mcnt - 1'd1;
+				if(!mcnt) mcnt <= my;
+					else vbuf_raddress <= vbuf_raddress - strd;
+			end
+		end
+	end
+
+	hf_reset <= 0;
+	if(vde2 & ~vde1) begin
+		hf_reset <= 1;
+		rdcnt <= 0;
+		bcnt <= 0;
+		rd_stride <= stride;
+		strd <= stride;
+		fsz <= framesz;
+		my <= mult_y;
+	end
+end
+
+
+reg [11:0] off_x, off_y;
+reg [11:0] x, y;
+reg [11:0] vh_height;
+reg [11:0] vh_width;
+reg  [1:0] pcnt;
+reg  [1:0] hload;
+wire       hf_rdreq = (x>=off_x) && (x<(vh_width+off_x)) && (y>=off_y) && (y<(vh_height+off_y)) && !hload && !pcnt;
+wire       de_in = hdmi_hde & hdmi_vde;
+
+always @(posedge clk_hdmi) begin
+	reg [71:0] px_out;
+	reg  [1:0] mx;
+	reg        vde;
+
+	vde <= hdmi_vde;
+
+	if(vde & ~hdmi_vde) begin
+		off_x <= (screen_w>v_width)  ? (screen_w - v_width)>>1  : 12'd0;
+		off_y <= (screen_h>v_height) ? (screen_h - v_height)>>1 : 12'd0;
+		vh_height <= v_height;
+		vh_width  <= v_width;
+		mx <= mult_x;
+	end
+
+	pcnt <= pcnt + 1'd1;
+	if(pcnt == mx) begin
+		pcnt <= 0;
+		hload <= hload + 1'd1;
+	end 
+
+	if(~de_in || x<off_x || y<off_y) begin
+		hload <= 0;
+		pcnt <= 0;
+	end
+
+	hdmi_de <= de_in;
+
+	x <= x + 1'd1;
+	if(~hdmi_de & de_in) x <= 0;
+	if(hdmi_de & ~de_in) y <= y + 1'd1;
+	if(~hdmi_vde) y <= 0;
+
+	if(!pcnt) {px_out, hdmi_d} <= {24'd0, px_out};
+	if(hf_rdreq) {px_out, hdmi_d} <= hf_out;
+end
+
+//////////////////////////////////////////////////////////////////////////////
+
+reg reading = 0;
+reg writing = 0;
+
+reg op_split = 0;
+always @(posedge clk_vbuf) op_split <= ~op_split;
+
+wire allow_rd = ~reading & ~writing &  op_split & ~reset;
+wire allow_wr = ~reading & ~writing & ~op_split & ~reset;
+
+//////////////////////////////////////////////////////////////////////////////
+
+reg         vf_rdreq = 0;
+wire [95:0] vf_out;
+assign      vbuf_writedata = {8'h00, vf_out[95:72], 8'h00, vf_out[71:48], 8'h00, vf_out[47:24], 8'h00, vf_out[23:0]};
+
+vbuf_fifo in_fifo
+(
+	.aclr(video_vs),
+
+	.rdclk(clk_vbuf),
+	.rdreq(vf_rdreq & ~vbuf_waitrequest),
+	.q(vf_out),
+
+	.wrclk(clk_video),
+	.wrreq(infifo_wr),
+	.data({video_de ? video_d : 24'd0, pix_acc})
+);
+
+assign vbuf_byteenable = '1;
+
+reg [35:0] addrque[3:0] = '{0,0,0,0};
+
+reg  [7:0] flush_size;
+reg [27:0] flush_addr;
+reg        flush_req = 0;
+reg        flush_ack = 0;
+
+reg [27:0] vbuf_waddress;
+reg  [7:0] vbuf_wburstcount;
+
+always @(posedge clk_vbuf) begin
+	reg [7:0] ibcnt = 0;
+	reg       reqd = 0;
+	
+	reqd <= flush_req;
+
+	if(~vbuf_waitrequest) begin
+		vbuf_write <= vf_rdreq;
+		if(~vf_rdreq && writing) writing <= 0;
+		if(!vf_rdreq && !vbuf_write && addrque[0] && allow_wr) begin
+			{vbuf_waddress, vbuf_wburstcount} <= addrque[0];
+			ibcnt <= addrque[0][7:0];
+			addrque[0] <= addrque[1];
+			addrque[1] <= addrque[2];
+			addrque[2] <= addrque[3];
+			addrque[3] <= 0;
+			vf_rdreq <= 1;
+			writing <= 1;
+		end
+		else if(flush_ack != reqd) begin
+				  if(!addrque[0]) addrque[0] <= {flush_addr, flush_size};
+			else if(!addrque[1]) addrque[1] <= {flush_addr, flush_size};
+			else if(!addrque[2]) addrque[2] <= {flush_addr, flush_size};
+			else if(!addrque[3]) addrque[3] <= {flush_addr, flush_size};
+			flush_ack <= reqd;
+		end
+
+		if(vf_rdreq) begin
+			if(ibcnt == 1) vf_rdreq <= 0;
+			ibcnt <= ibcnt - 1'd1;
+		end
+	end
+end
+
+reg  [11:0] stride;
+reg  [18:0] framesz;
+reg  [11:0] v_height;
+reg  [11:0] v_width;
+reg   [1:0] mult_x;
+reg   [1:0] mult_y;
+
+reg  [71:0] pix_acc;
+wire        pix_wr = ce_pixel && video_de;
+
+reg  [27:0] cur_addr;
+reg  [11:0] video_x;
+reg  [11:0] video_y;
+
+wire        infifo_tail = ~video_de && video_x[1:0];
+wire        infifo_wr = (pix_wr && &video_x[1:0]) || infifo_tail;
+
+wire  [1:0] tm_y     = (video_y  > (screen_h/2)) ? 2'b00 : (video_y  > (screen_h/3)) ? 2'b01 : (video_y  > (screen_h/4)) ? 2'b10 : 2'b11;
+wire  [1:0] tm_x     = (l1_width > (screen_w/2)) ? 2'b00 : (l1_width > (screen_w/3)) ? 2'b01 : (l1_width > (screen_w/4)) ? 2'b10 : 2'b11;
+wire  [1:0] tm_xy    = (tm_x < tm_y) ? tm_x : tm_y;
+wire  [1:0] tmf_y    = scale_auto ? tm_xy : scale_y;
+wire  [1:0] tmf_x    = scale_auto ? tm_xy : scale_x;
+wire [11:0] t_height = video_y  + (tmf_y[0] ? video_y  : 12'd0) + (tmf_y[1] ? video_y<<1  : 12'd0);
+wire [11:0] t_width  = l1_width + (tmf_x[0] ? l1_width : 12'd0) + (tmf_x[1] ? l1_width<<1 : 12'd0);
+wire [23:0] t_fsz    = l1_stride * t_height;
+
+reg  [11:0] l1_width;
+reg  [11:0] l1_stride;
+always @(posedge clk_video) begin
+	reg  [7:0] loaded = 0;
+	reg [11:0] strd   = 0;
+	reg        old_de = 0;
+	reg        old_vs = 0;
+
+	old_vs <= video_vs;
+	if(~old_vs & video_vs) begin
+		cur_addr<= write_buf;
+		video_x <= 0;
+		video_y <= 0;
+		loaded  <= 0;
+		strd <= 0;
+		nbuf <= nbuf + 1'd1;
+
+		stride  <= l1_stride;
+		framesz <= t_fsz[18:0];
+		v_height<= t_height;
+		v_width <= t_width;
+		mult_x  <= tmf_x;
+		mult_y  <= tmf_y;
+	end
+
+	if(pix_wr) begin
+		case(video_x[1:0])
+			0: pix_acc        <= video_d; // zeroes upper bits too
+			1: pix_acc[47:24] <= video_d;
+			2: pix_acc[71:48] <= video_d;
+			3: loaded <= loaded + 1'd1;
+		endcase
+		if(video_x<screen_w) video_x <= video_x + 1'd1;
+	end
+
+	old_de <= video_de;
+	if((!video_x[1:0] && loaded >= burstsz) || (old_de & ~video_de)) begin
+		if(loaded + infifo_tail) begin
+			flush_size <= loaded + infifo_tail;
+			flush_addr <= cur_addr;
+			flush_req  <= ~flush_req;
+			loaded <= 0;
+			strd   <= strd + loaded;
+		end
+
+		cur_addr <= cur_addr + loaded + infifo_tail;
+		if(~video_de) begin
+			if(video_y<screen_h) video_y <= video_y + 1'd1;
+			video_x <= 0;
+			strd    <= 0;
+
+			// measure width by first line (same as VIP)
+			if(!video_y) begin
+				l1_width <= video_x;
+				l1_stride  <= strd + loaded + infifo_tail;
+			end
+		end
+	end
+end
+
+endmodule
+
+module vbuf_fifo
+(
+	input	        aclr,
+
+	input	        rdclk,
+	input	        rdreq,
+	output [95:0] q,
+
+	input	        wrclk,
+	input	        wrreq,
+	input	 [95:0] data,
+	output  [7:0] wrusedw
+);
+
+dcfifo dcfifo_component
+(
+	.aclr (aclr),
+	.data (data),
+	.rdclk (rdclk),
+	.rdreq (rdreq),
+	.wrclk (wrclk),
+	.wrreq (wrreq),
+	.q (q),
+	.wrusedw (wrusedw),
+	.eccstatus (),
+	.rdempty (),
+	.rdfull (),
+	.rdusedw (),
+	.wrempty (),
+	.wrfull ()
+);
+
+defparam
+	dcfifo_component.intended_device_family = "Cyclone V",
+	dcfifo_component.lpm_numwords = 256,
+	dcfifo_component.lpm_showahead = "OFF",
+	dcfifo_component.lpm_type = "dcfifo",
+	dcfifo_component.lpm_width = 96,
+	dcfifo_component.lpm_widthu = 8,
+	dcfifo_component.overflow_checking = "ON",
+	dcfifo_component.rdsync_delaypipe = 5,
+	dcfifo_component.read_aclr_synch = "OFF",
+	dcfifo_component.underflow_checking = "ON",
+	dcfifo_component.use_eab = "ON",
+	dcfifo_component.write_aclr_synch = "OFF",
+	dcfifo_component.wrsync_delaypipe = 5;
+
+endmodule
diff --git a/sys/hps_io.v b/sys/hps_io.v
index cb6f532..e26ef16 100644
--- a/sys/hps_io.v
+++ b/sys/hps_io.v
@@ -33,7 +33,7 @@
 module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
 (
 	input             clk_sys,
-	inout      [43:0] HPS_BUS,
+	inout      [44:0] HPS_BUS,
 
 	// parameter STRLEN and the actual length of conf_str have to match
 	input [(8*STRLEN)-1:0] conf_str,
@@ -99,7 +99,11 @@ module hps_io #(parameter STRLEN=0, PS2DIV=2000, WIDE=0, VDNUM=1, PS2WE=0)
 	input             ps2_mouse_data_in,
 
 	// ps2 alternative interface.
-	output reg [65:0] ps2_key   = 0, // up to 8 bytes per key (pause)
+
+	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
+	output reg [10:0] ps2_key = 0,
+	
+	// [24] - toggles with every event
 	output reg [24:0] ps2_mouse = 0
 );
 
@@ -151,6 +155,7 @@ wire ce_pix  = HPS_BUS[41];
 wire de      = HPS_BUS[40];
 wire hs      = HPS_BUS[39];
 wire vs      = HPS_BUS[38];
+wire vs_hdmi = HPS_BUS[44];
 
 reg [31:0] vid_hcnt = 0;
 reg [31:0] vid_vcnt = 0;
@@ -222,8 +227,29 @@ always @(posedge clk_100) begin
 	if(old_de2 & ~old_de) calch <= 0;
 end
 
+reg [31:0] vid_vtime_hdmi;
+always @(posedge clk_100) begin
+	integer vtime;
+	reg old_vs, old_vs2;
+
+	old_vs <= vs_hdmi;
+	old_vs2 <= old_vs;
+
+	vtime <= vtime + 1'd1;
+
+	if(~old_vs2 & old_vs) begin
+		vid_vtime_hdmi <= vtime;
+		vtime <= 0;
+	end
+end
+
+
 /////////////////////////////////////////////////////////
 
+reg [31:0] ps2_key_raw = 0;
+wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
+wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
+
 always@(posedge clk_sys) begin
 	reg [15:0] cmd;
 	reg  [9:0] byte_cnt;   // counts bytes
@@ -236,11 +262,15 @@ always@(posedge clk_sys) begin
 	b_wr <= (b_wr<<1);
 
 	{kbd_rd,kbd_we,mouse_rd,mouse_we} <= 0;
-	ps2_key[65] <= kbd_txempty;
 	
 	if(~io_enable) begin
 		if(cmd == 4 && !ps2skip) ps2_mouse[24] <= ~ps2_mouse[24];
-		if(cmd == 5 && !ps2skip) ps2_key[64]   <= ~ps2_key[64];
+		if(cmd == 5 && !ps2skip) begin
+			ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
+			if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
+			if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
+			if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
+		end
 		if(cmd == 'h22) RTC[64] <= ~RTC[64];
 		if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32];
 		cmd <= 0;
@@ -266,7 +296,7 @@ always@(posedge clk_sys) begin
 
 				sd_buff_addr <= 0;
 				img_mounted <= 0;
-				if(io_din == 5) ps2_key[63:0] <= 0;
+				if(io_din == 5) ps2_key_raw <= 0;
 			end else begin
 
 				case(cmd)
@@ -292,7 +322,7 @@ always@(posedge clk_sys) begin
 					// store incoming ps2 keyboard bytes 
 					'h05: begin
 							if(&io_din[15:8]) ps2skip <= 1;
-							if(~&io_din[15:8] & ~ps2skip) ps2_key[63:0] <= {ps2_key[55:0], io_din[7:0]};
+							if(~&io_din[15:8] & ~ps2skip) ps2_key_raw[31:0] <= {ps2_key_raw[23:0], io_din[7:0]};
 							kbd_data <= io_din[7:0];
 							kbd_we <= 1;
 						end
@@ -385,6 +415,8 @@ always@(posedge clk_sys) begin
 									9: io_dout <= vid_vtime[31:16];
 								  10: io_dout <= vid_pix[15:0];
 								  11: io_dout <= vid_pix[31:16];
+								  12: io_dout <= vid_vtime_hdmi[15:0];
+								  13: io_dout <= vid_vtime_hdmi[31:16];
 								endcase
 						end
 
@@ -412,7 +444,6 @@ reg  [7:0] kbd_data;
 reg        kbd_we;
 wire [8:0] kbd_data_host;
 reg        kbd_rd;
-wire       kbd_txempty;
 
 ps2_device keyboard
 (
@@ -424,7 +455,6 @@ ps2_device keyboard
 	.ps2_clk(clk_ps2),
 	.ps2_clk_out(ps2_kbd_clk_out),
 	.ps2_dat_out(ps2_kbd_data_out),
-	.tx_empty(kbd_txempty),
 	
 	.ps2_clk_in(ps2_kbd_clk_in  || !PS2WE),
 	.ps2_dat_in(ps2_kbd_data_in || !PS2WE),
diff --git a/sys/i2c.v b/sys/i2c.v
index 911330f..ace6293 100644
--- a/sys/i2c.v
+++ b/sys/i2c.v
@@ -1,5 +1,5 @@
 
-module I2C_Controller
+module i2c
 (
 	input        CLK,
 
diff --git a/sys/i2s.v b/sys/i2s.v
index 4de12b5..b4c2d95 100644
--- a/sys/i2s.v
+++ b/sys/i2s.v
@@ -22,16 +22,39 @@ localparam WHOLE_CYCLES          = (CLK_RATE) / (AUDIO_RATE*AUDIO_DW*4);
 localparam ERROR_BASE            = 10000;
 localparam [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*AUDIO_DW*4)) - (WHOLE_CYCLES * ERROR_BASE);
 
+reg lpf_ce;
+wire [AUDIO_DW-1:0] al, ar;
+
+lpf_i2s lpf_l
+(
+   .CLK(clk_sys),
+   .CE(lpf_ce),
+   .IDATA(left_chan),
+   .ODATA(al)
+);
+
+lpf_i2s lpf_r
+(
+   .CLK(clk_sys),
+   .CE(lpf_ce),
+
+   .IDATA(right_chan),
+   .ODATA(ar)
+);
+
 always @(posedge clk_sys) begin
-	reg [31:0]  count_q;
-	reg [31:0]  error_q;
-	reg   [7:0] bit_cnt;
+	reg [31:0] count_q;
+	reg [31:0] error_q;
+	reg  [7:0] bit_cnt;
+	reg        skip = 0;
 
 	reg [AUDIO_DW-1:0] left;
 	reg [AUDIO_DW-1:0] right;
 
 	reg msclk;
 	reg ce;
+	
+	lpf_ce <= 0;
 
 	if (reset) begin
 		count_q   <= 0;
@@ -64,12 +87,14 @@ always @(posedge clk_sys) begin
 			if(~half_rate || ce) begin
 				msclk <= ~msclk;
 				if(msclk) begin
+					skip <= ~skip;
+					if(skip) lpf_ce <= 1;
 					if(bit_cnt >= AUDIO_DW) begin
 						bit_cnt <= 1;
 						lrclk <= ~lrclk;
 						if(lrclk) begin
-							left  <= left_chan;
-							right <= right_chan;
+							left  <= al;
+							right <= ar;
 						end
 					end
 					else begin
@@ -83,3 +108,29 @@ always @(posedge clk_sys) begin
 end
 
 endmodule
+
+module lpf_i2s
+(
+   input         CLK,
+   input         CE,
+   input  [15:0] IDATA,
+   output reg [15:0] ODATA
+);
+
+reg [511:0] acc;
+reg [20:0] sum;
+
+always @(*) begin
+	integer i;
+	sum = 0;
+	for (i = 0; i < 32; i = i+1) sum = sum + {{5{acc[(i*16)+15]}}, acc[i*16 +:16]};
+end
+
+always @(posedge CLK) begin
+	if(CE) begin
+		acc <= {acc[495:0], IDATA};
+		ODATA <= sum[20:5];
+	end
+end
+
+endmodule
diff --git a/sys/ip/avalon_combiner_hw.tcl b/sys/ip/avalon_combiner_hw.tcl
index 10e491f..5eede9c 100644
--- a/sys/ip/avalon_combiner_hw.tcl
+++ b/sys/ip/avalon_combiner_hw.tcl
@@ -1,11 +1,11 @@
-# TCL File Generated by Component Editor 16.1
-# Sat Mar 25 22:55:53 CST 2017
+# TCL File Generated by Component Editor 17.0
+# Wed Dec 13 01:40:49 CST 2017
 # DO NOT MODIFY
 
 
 # 
-# avalon_combiner "avalon_combiner" v1.0
-#  2017.03.25.22:55:53
+# avalon_combiner "avalon_combiner" v17.0
+# sorgelig 2017.12.13.01:40:49
 # 
 # 
 
@@ -20,7 +20,7 @@ package require -exact qsys 16.1
 # 
 set_module_property DESCRIPTION ""
 set_module_property NAME avalon_combiner
-set_module_property VERSION 1.0
+set_module_property VERSION 17.0
 set_module_property INTERNAL false
 set_module_property OPAQUE_ADDRESS_MAP true
 set_module_property AUTHOR sorgelig
diff --git a/sys/ip/de10_hps_hw.tcl b/sys/ip/de10_hps_hw.tcl
index 491400a..a166ca0 100644
--- a/sys/ip/de10_hps_hw.tcl
+++ b/sys/ip/de10_hps_hw.tcl
@@ -22,7 +22,7 @@ package require -exact altera_terp 1.0
 package require quartus::advanced_wysiwyg
 
 set_module_property NAME altera_hps_lite
-set_module_property VERSION 16.1
+set_module_property VERSION 17.0
 set_module_property AUTHOR "Altera Corporation/Sorgelig"                
 set_module_property SUPPORTED_DEVICE_FAMILIES {CYCLONEV ARRIAV}
 
diff --git a/sys/ip/in_split.v b/sys/ip/in_split.v
new file mode 100644
index 0000000..9e141e4
--- /dev/null
+++ b/sys/ip/in_split.v
@@ -0,0 +1,52 @@
+// in_split.v
+
+
+`timescale 1 ps / 1 ps
+module in_split (
+		input  wire        clk,                //  input.clk
+		input  wire        ce,                 //       .ce
+		input  wire        de,                 //       .de
+		input  wire        h_sync,             //       .h_sync
+		input  wire        v_sync,             //       .v_sync
+		input  wire        f,                  //       .f
+		input  wire [23:0] data,               //       .data
+		output wire        vid_clk,            // Output.vid_clk
+		output reg         vid_datavalid,      //       .vid_datavalid
+		output reg  [1:0]  vid_de,             //       .vid_de
+		output reg  [1:0]  vid_f,              //       .vid_f
+		output reg  [1:0]  vid_h_sync,         //       .vid_h_sync
+		output reg  [1:0]  vid_v_sync,         //       .vid_v_sync
+		output reg  [47:0] vid_data,           //       .vid_data
+		output wire        vid_locked,         //       .vid_locked
+		output wire [7:0]  vid_color_encoding, //       .vid_color_encoding
+		output wire [7:0]  vid_bit_width,      //       .vid_bit_width
+		input  wire        clipping,           //       .clipping
+		input  wire        overflow,           //       .overflow
+		input  wire        sof,                //       .sof
+		input  wire        sof_locked,         //       .sof_locked
+		input  wire        refclk_div,         //       .refclk_div
+		input  wire        padding             //       .padding
+	);
+
+	assign vid_bit_width = 0;
+	assign vid_color_encoding = 0;
+	assign vid_locked = 1;
+	assign vid_clk = clk;
+
+	always @(posedge clk) begin
+		reg odd = 0;
+		
+		vid_datavalid <= 0;
+		if(ce) begin
+			vid_de[odd] <= de;
+			vid_f[odd] <= f;
+			vid_h_sync[odd] <= h_sync;
+			vid_v_sync[odd] <= v_sync;
+			if(odd) vid_data[47:24] <= data;
+				else vid_data[23:0] <= data;
+			
+			odd <= ~odd;
+			vid_datavalid <= odd;
+		end
+	end
+endmodule
diff --git a/sys/ip/in_split_hw.tcl b/sys/ip/in_split_hw.tcl
new file mode 100644
index 0000000..403555a
--- /dev/null
+++ b/sys/ip/in_split_hw.tcl
@@ -0,0 +1,104 @@
+# TCL File Generated by Component Editor 17.0
+# Thu Jan 25 18:50:29 CST 2018
+# DO NOT MODIFY
+
+
+# 
+# in_split "Input Splitter" v17.0
+# Sorgelig 2018.01.25.18:50:29
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module in_split
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME in_split
+set_module_property VERSION 17.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR Sorgelig
+set_module_property DISPLAY_NAME "Input Splitter"
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL in_split
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
+add_fileset_file in_split.v VERILOG PATH in_split.v TOP_LEVEL_FILE
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point input
+# 
+add_interface input conduit end
+set_interface_property input associatedClock ""
+set_interface_property input associatedReset ""
+set_interface_property input ENABLED true
+set_interface_property input EXPORT_OF ""
+set_interface_property input PORT_NAME_MAP ""
+set_interface_property input CMSIS_SVD_VARIABLES ""
+set_interface_property input SVD_ADDRESS_GROUP ""
+
+add_interface_port input clk clk Input 1
+add_interface_port input ce ce Input 1
+add_interface_port input de de Input 1
+add_interface_port input h_sync h_sync Input 1
+add_interface_port input v_sync v_sync Input 1
+add_interface_port input f f Input 1
+add_interface_port input data data Input 24
+
+
+# 
+# connection point Output
+# 
+add_interface Output conduit end
+set_interface_property Output associatedClock ""
+set_interface_property Output associatedReset ""
+set_interface_property Output ENABLED true
+set_interface_property Output EXPORT_OF ""
+set_interface_property Output PORT_NAME_MAP ""
+set_interface_property Output CMSIS_SVD_VARIABLES ""
+set_interface_property Output SVD_ADDRESS_GROUP ""
+
+add_interface_port Output vid_clk vid_clk Output 1
+add_interface_port Output vid_datavalid vid_datavalid Output 1
+add_interface_port Output vid_de vid_de Output 2
+add_interface_port Output vid_f vid_f Output 2
+add_interface_port Output vid_h_sync vid_h_sync Output 2
+add_interface_port Output vid_v_sync vid_v_sync Output 2
+add_interface_port Output vid_data vid_data Output 48
+add_interface_port Output vid_locked vid_locked Output 1
+add_interface_port Output vid_color_encoding vid_color_encoding Output 8
+add_interface_port Output vid_bit_width vid_bit_width Output 8
+add_interface_port Output clipping clipping Input 1
+add_interface_port Output overflow overflow Input 1
+add_interface_port Output sof sof Input 1
+add_interface_port Output sof_locked sof_locked Input 1
+add_interface_port Output refclk_div refclk_div Input 1
+add_interface_port Output padding padding Input 1
+
diff --git a/sys/ip/out_mix.v b/sys/ip/out_mix.v
new file mode 100644
index 0000000..280a3d5
--- /dev/null
+++ b/sys/ip/out_mix.v
@@ -0,0 +1,44 @@
+// out_mix.v
+
+`timescale 1 ps / 1 ps
+module out_mix (
+		input  wire        clk,             // Output.clk
+		output reg         de,              //       .de
+		output reg         h_sync,          //       .h_sync
+		output reg         v_sync,          //       .v_sync
+		output reg  [23:0] data,            //       .data
+		output reg         vid_clk,         //  input.vid_clk
+		input  wire [1:0]  vid_datavalid,   //       .vid_datavalid
+		input  wire [1:0]  vid_h_sync,      //       .vid_h_sync
+		input  wire [1:0]  vid_v_sync,      //       .vid_v_sync
+		input  wire [47:0] vid_data,        //       .vid_data
+		input  wire        underflow,       //       .underflow
+		input  wire        vid_mode_change, //       .vid_mode_change
+		input  wire [1:0]  vid_std,         //       .vid_std
+		input  wire [1:0]  vid_f,           //       .vid_f
+		input  wire [1:0]  vid_h,           //       .vid_h
+		input  wire [1:0]  vid_v            //       .vid_v
+	);
+
+	reg        r_de;
+	reg        r_h_sync;
+	reg        r_v_sync;
+	reg [23:0] r_data;
+	
+	always @(posedge clk) begin
+		vid_clk <= ~vid_clk;
+		
+		if(~vid_clk) begin
+			{r_de,de} <= vid_datavalid;
+			{r_h_sync, h_sync} <= vid_h_sync;
+			{r_v_sync, v_sync} <= vid_v_sync;
+			{r_data, data} <= vid_data;
+		end else begin
+			de <= r_de;
+			h_sync <= r_h_sync;
+			v_sync <= r_v_sync;
+			data <= r_data;
+		end
+	end
+
+endmodule
diff --git a/sys/ip/out_mix_hw.tcl b/sys/ip/out_mix_hw.tcl
new file mode 100644
index 0000000..b388891
--- /dev/null
+++ b/sys/ip/out_mix_hw.tcl
@@ -0,0 +1,97 @@
+# TCL File Generated by Component Editor 17.0
+# Thu Jan 25 06:51:26 CST 2018
+# DO NOT MODIFY
+
+
+# 
+# out_mix "Output Mixer" v1.0
+# Sorgelig 2018.01.25.06:51:26
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module out_mix
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME out_mix
+set_module_property VERSION 17.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR Sorgelig
+set_module_property DISPLAY_NAME "Output Mixer"
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL out_mix
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
+add_fileset_file out_mix.v VERILOG PATH out_mix.v TOP_LEVEL_FILE
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point Output
+# 
+add_interface Output conduit end
+set_interface_property Output associatedClock ""
+set_interface_property Output associatedReset ""
+set_interface_property Output ENABLED true
+set_interface_property Output EXPORT_OF ""
+set_interface_property Output PORT_NAME_MAP ""
+set_interface_property Output CMSIS_SVD_VARIABLES ""
+set_interface_property Output SVD_ADDRESS_GROUP ""
+
+add_interface_port Output clk clk Input 1
+add_interface_port Output de de Output 1
+add_interface_port Output h_sync h_sync Output 1
+add_interface_port Output v_sync v_sync Output 1
+add_interface_port Output data data Output 24
+
+
+# 
+# connection point input
+# 
+add_interface input conduit end
+set_interface_property input associatedClock ""
+set_interface_property input associatedReset ""
+set_interface_property input ENABLED true
+set_interface_property input EXPORT_OF ""
+set_interface_property input PORT_NAME_MAP ""
+set_interface_property input CMSIS_SVD_VARIABLES ""
+set_interface_property input SVD_ADDRESS_GROUP ""
+
+add_interface_port input vid_clk vid_clk Output 1
+add_interface_port input vid_datavalid vid_datavalid Input 2
+add_interface_port input vid_h_sync vid_h_sync Input 2
+add_interface_port input vid_v_sync vid_v_sync Input 2
+add_interface_port input vid_data vid_data Input 48
+add_interface_port input underflow underflow Input 1
+add_interface_port input vid_mode_change vid_mode_change Input 1
+add_interface_port input vid_std vid_std Input 2
+add_interface_port input vid_f vid_f Input 2
+add_interface_port input vid_h vid_h Input 2
+add_interface_port input vid_v vid_v Input 2
+
diff --git a/sys/ip/reset_source.v b/sys/ip/reset_source.v
index e9f0435..569eb9c 100644
--- a/sys/ip/reset_source.v
+++ b/sys/ip/reset_source.v
@@ -1,32 +1,34 @@
 // reset_source.v
 
-// This file was auto-generated as a prototype implementation of a module
-// created in component editor.  It ties off all outputs to ground and
-// ignores all inputs.  It needs to be edited to make it do something
-// useful.
-// 
-// This file will not be automatically regenerated.  You should check it in
+// This file was auto-generated as a prototype implementation of a module
+// created in component editor.  It ties off all outputs to ground and
+// ignores all inputs.  It needs to be edited to make it do something
+// useful.
+// 
+// This file will not be automatically regenerated.  You should check it in
 // to your version control system if you want to keep it.
 
-`timescale 1 ps / 1 ps
+`timescale 1 ps / 1 ps
 module reset_source
 (
-	input  wire  clk,        //      clock.clk
-	input  wire  reset_hps,  //  reset_hps.reset
-	output wire  reset_sys,  //  reset_sys.reset
-	output wire  reset_cold, // reset_cold.reset
-	input  wire  cold_req,   //  reset_ctl.cold_req
-	output wire  reset,      //           .reset
-	input  wire  reset_req,  //           .reset_req
-	input  wire  warm_req,   //           .warm_req
-	output wire  reset_warm  // reset_warm.reset
+	input  wire  clk,        //      clock.clk
+	input  wire  reset_hps,  //  reset_hps.reset
+	output wire  reset_sys,  //  reset_sys.reset
+	output wire  reset_cold, // reset_cold.reset
+	input  wire  cold_req,   //  reset_ctl.cold_req
+	output wire  reset,      //           .reset
+	input  wire  reset_req,  //           .reset_req
+	input  wire  reset_vip,  //           .reset_vip
+	input  wire  warm_req,   //           .warm_req
+	output wire  reset_warm  // reset_warm.reset
 );
 
 assign reset_cold = cold_req;
 assign reset_warm = warm_req;
 
-assign reset      = reset_sys;
-assign reset_sys  = sys_reset | reset_hps | reset_req;
+wire   reset_m    = sys_reset | reset_hps | reset_req;
+assign reset      = reset_m;
+assign reset_sys  = reset_m | reset_vip;
 
 reg  sys_reset = 1;
 always @(posedge clk) begin
diff --git a/sys/ip/reset_source_hw.tcl b/sys/ip/reset_source_hw.tcl
index 528bdf6..cba39f7 100644
--- a/sys/ip/reset_source_hw.tcl
+++ b/sys/ip/reset_source_hw.tcl
@@ -1,11 +1,11 @@
-# TCL File Generated by Component Editor 16.1
-# Thu Apr 20 14:20:36 CST 2017
+# TCL File Generated by Component Editor 17.0
+# Tue Feb 20 07:55:55 CST 2018
 # DO NOT MODIFY
 
 
 # 
-# reset_source "reset_source" v1.0
-# Sorgelig 2017.04.20.14:20:36
+# reset_source "reset_source" v17.0
+# Sorgelig 2018.02.20.07:55:55
 # 
 # 
 
@@ -20,7 +20,7 @@ package require -exact qsys 16.1
 # 
 set_module_property DESCRIPTION ""
 set_module_property NAME reset_source
-set_module_property VERSION 1.0
+set_module_property VERSION 17.0
 set_module_property INTERNAL false
 set_module_property OPAQUE_ADDRESS_MAP true
 set_module_property AUTHOR Sorgelig
@@ -114,6 +114,7 @@ add_interface_port reset_ctl cold_req cold_req Input 1
 add_interface_port reset_ctl reset reset Output 1
 add_interface_port reset_ctl reset_req reset_req Input 1
 add_interface_port reset_ctl warm_req warm_req Input 1
+add_interface_port reset_ctl reset_vip reset_vip Input 1
 
 
 # 
diff --git a/sys/osd.v b/sys/osd.v
index 87a2eff..f6e8915 100644
--- a/sys/osd.v
+++ b/sys/osd.v
@@ -7,12 +7,13 @@ module osd
 
 	input         io_osd,
 	input         io_strobe,
-	input   [7:0] io_din,
+	input  [15:0] io_din,
 
 	input         clk_video,
 	input  [23:0] din,
 	output [23:0] dout,
-	input         de
+	input         de_in,
+	output reg    de_out
 );
 
 parameter  OSD_COLOR    =  3'd4;
@@ -22,14 +23,16 @@ parameter  OSD_Y_OFFSET = 12'd0;
 localparam OSD_WIDTH    = 12'd256;
 localparam OSD_HEIGHT   = 12'd64;
 
-// this core supports only the display related OSD commands
-// of the minimig v1
 reg osd_enable;
-(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[4096];  // the OSD buffer itself
+(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[4096];
 
-reg highres = 0;
+reg        highres = 0;
+reg        info = 0;
+reg  [8:0] infoh;
+reg  [8:0] infow;
+reg [11:0] infox;
+reg [21:0] infoy;
 
-// the OSD has its own SPI interface to the io controller
 always@(posedge clk_sys) begin
 	reg [11:0] bcnt;
 	reg  [7:0] cmd;
@@ -41,24 +44,37 @@ always@(posedge clk_sys) begin
 	if(~io_osd) begin
 		bcnt <= 0;
 		has_cmd <= 0;
+		cmd <= 0;
+		if(cmd[7:4] == 4) osd_enable <= cmd[0];
 	end else begin
 		if(~old_strobe & io_strobe) begin
 			if(!has_cmd) begin
 				has_cmd <= 1;
-				cmd <= io_din;
+				cmd <= io_din[7:0];
 				// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-				if(io_din[7:4] == 4'b0100) begin
-					osd_enable <= io_din[0];
+				if(io_din[7:4] == 4) begin
 					if(!io_din[0]) highres <= 0;
+					info <= io_din[2];
+					bcnt  <= 0;
 				end
-				bcnt <= {io_din[3:0], 8'h00};
-				if(io_din[7:3] == 5'b00101) highres <= 1;
-			end else begin
 				// command 0x20: OSDCMDWRITE
-				if(cmd[7:4] == 4'b0010) begin
-					osd_buffer[bcnt] <= io_din;
-					bcnt <= bcnt + 1'd1;
+				if(io_din[7:4] == 2) begin
+					if(io_din[3]) highres <= 1;
+					bcnt <= {io_din[3:0], 8'h00};
 				end
+			end else begin
+				// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
+				if(cmd[7:4] == 4) begin
+					if(bcnt == 0) infox <= io_din[11:0];
+					if(bcnt == 1) infoy <= io_din[11:0];
+					if(bcnt == 2) infow <= {io_din[5:0], 3'b000};
+					if(bcnt == 3) infoh <= {io_din[5:0], 3'b000};
+				end
+
+				// command 0x20: OSDCMDWRITE
+				if(cmd[7:4] == 2) osd_buffer[bcnt] <= io_din[7:0];
+
+				bcnt <= bcnt + 1'd1;
 			end
 		end
 	end
@@ -71,15 +87,15 @@ always @(negedge clk_video) begin
 	reg deD;
 
 	cnt <= cnt + 1;
-	deD <= de;
+	deD <= de_in;
 
 	pixcnt <= pixcnt + 1;
 	if(pixcnt == pixsz) pixcnt <= 0;
 	ce_pix <= !pixcnt;
 
-	if(~deD && de) cnt <= 0;
+	if(~deD && de_in) cnt <= 0;
 
-	if(deD && ~de) begin
+	if(deD && ~de_in) begin
 		pixsz  <= (((cnt+1'b1) >> 9) > 1) ? (((cnt+1'b1) >> 9) - 1) : 0;
 		pixcnt <= 0;
 	end
@@ -93,7 +109,8 @@ reg   [7:0] osd_byte;
 reg  [21:0] osd_vcnt;
 reg  [21:0] fheight;
 
-wire [21:0] hrheight = (OSD_HEIGHT<<highres);
+reg  [21:0] finfoy;
+wire [21:0] hrheight = info ? infoh : (OSD_HEIGHT<<highres);
 
 always @(posedge clk_video) begin
 	reg       deD;
@@ -102,34 +119,43 @@ always @(posedge clk_video) begin
 	
 	if(ce_pix) begin
 
-		deD <= de;
+		deD <= de_in;
 		if(~&h_cnt) h_cnt <= h_cnt + 1'd1;
 
 		// falling edge of de
-		if(!de && deD) dsp_width <= h_cnt[21:0];
+		if(!de_in && deD) dsp_width <= h_cnt[21:0];
 
 		// rising edge of de
-		if(de && !deD) begin
+		if(de_in && !deD) begin
 			v_cnt <= v_cnt + 1'd1;
 			if(h_cnt > {dsp_width, 2'b00}) begin
 				v_cnt <= 0;
 				dsp_height <= v_cnt;
-				
-				if(v_cnt<320) begin
-					multiscan <= 0;
-					fheight <= hrheight;
-				end
-				else if(v_cnt<640) begin
-					multiscan <= 1;
-					fheight <= hrheight << 1;
-				end
-				else if(v_cnt<960) begin
-					multiscan <= 2;
-					fheight <= hrheight + (hrheight<<1);
+
+				if(osd_enable) begin
+					if(v_cnt<320) begin
+						multiscan <= 0;
+						fheight <= hrheight;
+						finfoy <= infoy;
+					end
+					else if(v_cnt<640) begin
+						multiscan <= 1;
+						fheight <= hrheight << 1;
+						finfoy <= infoy << 1;
+					end
+					else if(v_cnt<960) begin
+						multiscan <= 2;
+						fheight <= hrheight + (hrheight<<1);
+						finfoy <= infoy + (infoy << 1);
+					end
+					else begin
+						multiscan <= 3;
+						fheight <= hrheight << 2;
+						finfoy <= infoy << 2;
+					end
 				end
 				else begin
-					multiscan <= 3;
-					fheight <= hrheight << 2;
+					fheight <= 0;
 				end
 			end
 			h_cnt <= 0;
@@ -147,22 +173,27 @@ always @(posedge clk_video) begin
 end
 
 // area in which OSD is being displayed
-wire [21:0] h_osd_start = ((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET;
-wire [21:0] h_osd_end   = h_osd_start + OSD_WIDTH;
-wire [21:0] v_osd_start = ((dsp_height- fheight)>>1) + OSD_Y_OFFSET;
+wire [21:0] h_osd_start = info ? infox  : ((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET;
+wire [21:0] h_osd_end   = info ? (h_osd_start + infow) : (h_osd_start + OSD_WIDTH);
+wire [21:0] v_osd_start = info ? finfoy : ((dsp_height- fheight)>>1) + OSD_Y_OFFSET;
 wire [21:0] v_osd_end   = v_osd_start + fheight;
 
 wire [21:0] osd_hcnt    = h_cnt[21:0] - h_osd_start + 1'd1;
 
-wire osd_de = osd_enable &&
+wire osd_de = osd_enable && fheight &&
               (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
               (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
 
 wire osd_pixel = osd_byte[osd_vcnt[2:0]];
 
-
-assign dout = !osd_de ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},
+reg [23:0] rdout;
+assign dout = rdout;
+									 
+always @(posedge clk_video) begin
+	rdout <= !osd_de ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},
                                {osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},
                                {osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}};
+	de_out <= de_in;
+end
 
 endmodule
diff --git a/sys/pll_hdmi.qip b/sys/pll_hdmi.qip
index 2c1e916..be34aeb 100644
--- a/sys/pll_hdmi.qip
+++ b/sys/pll_hdmi.qip
@@ -31,7 +31,9 @@ set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPO
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfY291dA==::MzI=::cGxsX2ZyYWN0aW9uYWxfY291dA=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::cGxsX2RzbV9vdXRfc2Vs"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::ZmFsc2U=::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
@@ -41,11 +43,11 @@ set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPO
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NzQuMjU=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTQ4LjU=::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MzkwODQyMDE1Mw==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Mw==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
@@ -53,7 +55,7 @@ set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPO
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::NjUuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
@@ -65,7 +67,7 @@ set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPO
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MjcuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
@@ -256,7 +258,7 @@ set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPO
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NzQuMjUwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTQ4LjUwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
@@ -312,13 +314,157 @@ set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPO
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::dHJ1ZQ==::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::Q3ljbG9uZSBW::UExMIFRZUEU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::UmVjb25maWd1cmFibGU=::UExMIFNVQlRZUEU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfaGlfZGl2::NA==::bV9jbnRfaGlfZGl2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfbG9fZGl2::NA==::bV9jbnRfbG9fZGl2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfaGlfZGl2::MjU2::bl9jbnRfaGlfZGl2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfbG9fZGl2::MjU2::bl9jbnRfbG9fZGl2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfYnlwYXNzX2Vu::ZmFsc2U=::bV9jbnRfYnlwYXNzX2Vu"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfYnlwYXNzX2Vu::dHJ1ZQ==::bl9jbnRfYnlwYXNzX2Vu"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bV9jbnRfb2RkX2Rpdl9kdXR5X2Vu"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu::ZmFsc2U=::bl9jbnRfb2RkX2Rpdl9kdXR5X2Vu"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MA==::Mg==::Y19jbnRfaGlfZGl2MA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MA==::MQ==::Y19jbnRfbG9fZGl2MA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDA=::MQ==::Y19jbnRfcHJzdDA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qw::MA==::Y19jbnRfcGhfbXV4X3Byc3Qw"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMA==::ZmFsc2U=::Y19jbnRfYnlwYXNzX2VuMA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA==::dHJ1ZQ==::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MQ==::MQ==::Y19jbnRfaGlfZGl2MQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MQ==::MQ==::Y19jbnRfbG9fZGl2MQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE=::MQ==::Y19jbnRfcHJzdDE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qx::MA==::Y19jbnRfcGhfbXV4X3Byc3Qx"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mg==::MQ==::Y19jbnRfaGlfZGl2Mg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mg==::MQ==::Y19jbnRfbG9fZGl2Mg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDI=::MQ==::Y19jbnRfcHJzdDI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qy::MA==::Y19jbnRfcGhfbXV4X3Byc3Qy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Mw==::MQ==::Y19jbnRfaGlfZGl2Mw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Mw==::MQ==::Y19jbnRfbG9fZGl2Mw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDM=::MQ==::Y19jbnRfcHJzdDM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Qz::MA==::Y19jbnRfcGhfbXV4X3Byc3Qz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMw==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NA==::MQ==::Y19jbnRfaGlfZGl2NA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NA==::MQ==::Y19jbnRfbG9fZGl2NA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDQ=::MQ==::Y19jbnRfcHJzdDQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q0::MA==::Y19jbnRfcGhfbXV4X3Byc3Q0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2NQ==::MQ==::Y19jbnRfaGlfZGl2NQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2NQ==::MQ==::Y19jbnRfbG9fZGl2NQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDU=::MQ==::Y19jbnRfcHJzdDU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q1::MA==::Y19jbnRfcGhfbXV4X3Byc3Q1"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Ng==::MQ==::Y19jbnRfaGlfZGl2Ng=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Ng==::MQ==::Y19jbnRfbG9fZGl2Ng=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDY=::MQ==::Y19jbnRfcHJzdDY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q2::MA==::Y19jbnRfcGhfbXV4X3Byc3Q2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNg==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNg==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2Nw==::MQ==::Y19jbnRfaGlfZGl2Nw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2Nw==::MQ==::Y19jbnRfbG9fZGl2Nw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDc=::MQ==::Y19jbnRfcHJzdDc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q3::MA==::Y19jbnRfcGhfbXV4X3Byc3Q3"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjNw==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjNw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuNw==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuNw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuNw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OA==::MQ==::Y19jbnRfaGlfZGl2OA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OA==::MQ==::Y19jbnRfbG9fZGl2OA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDg=::MQ==::Y19jbnRfcHJzdDg="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q4::MA==::Y19jbnRfcGhfbXV4X3Byc3Q4"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOA==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOA==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2OQ==::MQ==::Y19jbnRfaGlfZGl2OQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2OQ==::MQ==::Y19jbnRfbG9fZGl2OQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDk=::MQ==::Y19jbnRfcHJzdDk="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3Q5::MA==::Y19jbnRfcGhfbXV4X3Byc3Q5"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjOQ==::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjOQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuOQ==::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuOQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ==::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuOQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTA=::MQ==::Y19jbnRfaGlfZGl2MTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTA=::MQ==::Y19jbnRfbG9fZGl2MTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEw::MQ==::Y19jbnRfcHJzdDEw"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTA=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTA=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTE=::MQ==::Y19jbnRfaGlfZGl2MTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTE=::MQ==::Y19jbnRfbG9fZGl2MTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEx::MQ==::Y19jbnRfcHJzdDEx"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTE=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTE=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTI=::MQ==::Y19jbnRfaGlfZGl2MTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTI=::MQ==::Y19jbnRfbG9fZGl2MTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEy::MQ==::Y19jbnRfcHJzdDEy"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTI=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTI=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTI="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTM=::MQ==::Y19jbnRfaGlfZGl2MTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTM=::MQ==::Y19jbnRfbG9fZGl2MTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDEz::MQ==::Y19jbnRfcHJzdDEz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxMw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxMw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTM=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTM=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTM="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTQ=::MQ==::Y19jbnRfaGlfZGl2MTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTQ=::MQ==::Y19jbnRfbG9fZGl2MTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE0::MQ==::Y19jbnRfcHJzdDE0"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNA==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTQ=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTQ=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTU=::MQ==::Y19jbnRfaGlfZGl2MTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTU=::MQ==::Y19jbnRfbG9fZGl2MTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE1::MQ==::Y19jbnRfcHJzdDE1"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNQ==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTU=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTU=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTU="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTY=::MQ==::Y19jbnRfaGlfZGl2MTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTY=::MQ==::Y19jbnRfbG9fZGl2MTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE2::MQ==::Y19jbnRfcHJzdDE2"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNg==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTY=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTY=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaGlfZGl2MTc=::MQ==::Y19jbnRfaGlfZGl2MTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfbG9fZGl2MTc=::MQ==::Y19jbnRfbG9fZGl2MTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcHJzdDE3::MQ==::Y19jbnRfcHJzdDE3"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfcGhfbXV4X3Byc3QxNw==::MA==::Y19jbnRfcGhfbXV4X3Byc3QxNw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfaW5fc3JjMTc=::cGhfbXV4X2Nsaw==::Y19jbnRfaW5fc3JjMTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfYnlwYXNzX2VuMTc=::dHJ1ZQ==::Y19jbnRfYnlwYXNzX2VuMTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc=::ZmFsc2U=::Y19jbnRfb2RkX2Rpdl9kdXR5X2VuMTc="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3Zjb19kaXY=::Mg==::cGxsX3Zjb19kaXY="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2NwX2N1cnJlbnQ=::MjA=::cGxsX2NwX2N1cnJlbnQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2J3Y3RybA==::NDAwMA==::cGxsX2J3Y3RybA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5::NDQ1LjQ5OTk5OSBNSHo=::cGxsX291dHB1dF9jbGtfZnJlcXVlbmN5"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24=::MzkwODQyMDE1Mw==::cGxsX2ZyYWN0aW9uYWxfZGl2aXNpb24="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bWltaWNfZmJjbGtfdHlwZQ==::bm9uZQ==::bWltaWNfZmJjbGtfdHlwZQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8x::Z2xi::cGxsX2ZiY2xrX211eF8x"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX2ZiY2xrX211eF8y::bV9jbnQ=::cGxsX2ZiY2xrX211eF8y"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX21fY250X2luX3NyYw==::cGhfbXV4X2Nsaw==::cGxsX21fY250X2luX3NyYw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3NsZl9yc3Q=::dHJ1ZQ==::cGxsX3NsZl9yc3Q="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwzLDMsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMiwyMCw0MDAwLDQ0NS40OTk5OTkgTUh6LDM5MDg0MjAxNTMsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwyLDEsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDIwLDQwMDAsNDQ1LjQ5OTk5OSBNSHosMzkwODQyMDE1Myxub25lLGdsYixtX2NudCxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
diff --git a/sys/pll_hdmi.v b/sys/pll_hdmi.v
index 5ff1175..0cefd25 100644
--- a/sys/pll_hdmi.v
+++ b/sys/pll_hdmi.v
@@ -6,16 +6,20 @@
 
 `timescale 1 ps / 1 ps
 module pll_hdmi (
-		input  wire  refclk,   //  refclk.clk
-		input  wire  rst,      //   reset.reset
-		output wire  outclk_0  // outclk0.clk
+		input  wire        refclk,            //            refclk.clk
+		input  wire        rst,               //             reset.reset
+		output wire        outclk_0,          //           outclk0.clk
+		input  wire [63:0] reconfig_to_pll,   //   reconfig_to_pll.reconfig_to_pll
+		output wire [63:0] reconfig_from_pll  // reconfig_from_pll.reconfig_from_pll
 	);
 
 	pll_hdmi_0002 pll_hdmi_inst (
-		.refclk   (refclk),   //  refclk.clk
-		.rst      (rst),      //   reset.reset
-		.outclk_0 (outclk_0), // outclk0.clk
-		.locked   ()          // (terminated)
+		.refclk            (refclk),            //            refclk.clk
+		.rst               (rst),               //             reset.reset
+		.outclk_0          (outclk_0),          //           outclk0.clk
+		.reconfig_to_pll   (reconfig_to_pll),   //   reconfig_to_pll.reconfig_to_pll
+		.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
+		.locked            ()                   //       (terminated)
 	);
 
 endmodule
@@ -25,7 +29,7 @@ endmodule
 //	************************************************************
 //	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //	************************************************************
-//	Copyright (C) 1991-2017 Altera Corporation
+//	Copyright (C) 1991-2018 Altera Corporation
 //	Any megafunction design, and related net list (encrypted or decrypted),
 //	support information, device programming or simulation file, and any other
 //	associated documentation or information provided by Altera or a partner
@@ -65,7 +69,7 @@ endmodule
 // Retrieval info: 	<generic name="gui_frac_multiply_factor" value="1" />
 // Retrieval info: 	<generic name="gui_divide_factor_n" value="1" />
 // Retrieval info: 	<generic name="gui_cascade_counter0" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency0" value="74.25" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency0" value="148.5" />
 // Retrieval info: 	<generic name="gui_divide_factor_c0" value="1" />
 // Retrieval info: 	<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
 // Retrieval info: 	<generic name="gui_ps_units0" value="ps" />
@@ -74,7 +78,7 @@ endmodule
 // Retrieval info: 	<generic name="gui_actual_phase_shift0" value="0" />
 // Retrieval info: 	<generic name="gui_duty_cycle0" value="50" />
 // Retrieval info: 	<generic name="gui_cascade_counter1" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency1" value="100.0" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency1" value="65.0" />
 // Retrieval info: 	<generic name="gui_divide_factor_c1" value="1" />
 // Retrieval info: 	<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
 // Retrieval info: 	<generic name="gui_ps_units1" value="ps" />
@@ -83,7 +87,7 @@ endmodule
 // Retrieval info: 	<generic name="gui_actual_phase_shift1" value="0" />
 // Retrieval info: 	<generic name="gui_duty_cycle1" value="50" />
 // Retrieval info: 	<generic name="gui_cascade_counter2" value="false" />
-// Retrieval info: 	<generic name="gui_output_clock_frequency2" value="100.0" />
+// Retrieval info: 	<generic name="gui_output_clock_frequency2" value="27.0" />
 // Retrieval info: 	<generic name="gui_divide_factor_c2" value="1" />
 // Retrieval info: 	<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
 // Retrieval info: 	<generic name="gui_ps_units2" value="ps" />
@@ -228,7 +232,7 @@ endmodule
 // Retrieval info: 	<generic name="gui_duty_cycle17" value="50" />
 // Retrieval info: 	<generic name="gui_pll_auto_reset" value="On" />
 // Retrieval info: 	<generic name="gui_pll_bandwidth_preset" value="Auto" />
-// Retrieval info: 	<generic name="gui_en_reconf" value="false" />
+// Retrieval info: 	<generic name="gui_en_reconf" value="true" />
 // Retrieval info: 	<generic name="gui_en_dps_ports" value="false" />
 // Retrieval info: 	<generic name="gui_en_phout_ports" value="false" />
 // Retrieval info: 	<generic name="gui_phout_division" value="1" />
diff --git a/sys/pll_hdmi/pll_hdmi_0002.qip b/sys/pll_hdmi/pll_hdmi_0002.qip
index fb8053d..3cb7073 100644
--- a/sys/pll_hdmi/pll_hdmi_0002.qip
+++ b/sys/pll_hdmi/pll_hdmi_0002.qip
@@ -1,4 +1,2 @@
 set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
-set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
-set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
-set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
diff --git a/sys/pll_hdmi/pll_hdmi_0002.v b/sys/pll_hdmi/pll_hdmi_0002.v
index 6bea229..9347c76 100644
--- a/sys/pll_hdmi/pll_hdmi_0002.v
+++ b/sys/pll_hdmi/pll_hdmi_0002.v
@@ -11,15 +11,23 @@ module  pll_hdmi_0002(
 	output wire outclk_0,
 
 	// interface 'locked'
-	output wire locked
+	output wire locked,
+
+	// interface 'reconfig_to_pll'
+	input wire [63:0] reconfig_to_pll,
+
+	// interface 'reconfig_from_pll'
+	output wire [63:0] reconfig_from_pll
 );
 
 	altera_pll #(
 		.fractional_vco_multiplier("true"),
 		.reference_clock_frequency("50.0 MHz"),
+		.pll_fractional_cout(32),
+		.pll_dsm_out_sel("1st_order"),
 		.operation_mode("direct"),
 		.number_of_clocks(1),
-		.output_clock_frequency0("74.250000 MHz"),
+		.output_clock_frequency0("148.500000 MHz"),
 		.phase_shift0("0 ps"),
 		.duty_cycle0(50),
 		.output_clock_frequency1("0 MHz"),
@@ -73,15 +81,161 @@ module  pll_hdmi_0002(
 		.output_clock_frequency17("0 MHz"),
 		.phase_shift17("0 ps"),
 		.duty_cycle17(50),
-		.pll_type("General"),
-		.pll_subtype("General")
+		.pll_type("Cyclone V"),
+		.pll_subtype("Reconfigurable"),
+		.m_cnt_hi_div(4),
+		.m_cnt_lo_div(4),
+		.n_cnt_hi_div(256),
+		.n_cnt_lo_div(256),
+		.m_cnt_bypass_en("false"),
+		.n_cnt_bypass_en("true"),
+		.m_cnt_odd_div_duty_en("false"),
+		.n_cnt_odd_div_duty_en("false"),
+		.c_cnt_hi_div0(2),
+		.c_cnt_lo_div0(1),
+		.c_cnt_prst0(1),
+		.c_cnt_ph_mux_prst0(0),
+		.c_cnt_in_src0("ph_mux_clk"),
+		.c_cnt_bypass_en0("false"),
+		.c_cnt_odd_div_duty_en0("true"),
+		.c_cnt_hi_div1(1),
+		.c_cnt_lo_div1(1),
+		.c_cnt_prst1(1),
+		.c_cnt_ph_mux_prst1(0),
+		.c_cnt_in_src1("ph_mux_clk"),
+		.c_cnt_bypass_en1("true"),
+		.c_cnt_odd_div_duty_en1("false"),
+		.c_cnt_hi_div2(1),
+		.c_cnt_lo_div2(1),
+		.c_cnt_prst2(1),
+		.c_cnt_ph_mux_prst2(0),
+		.c_cnt_in_src2("ph_mux_clk"),
+		.c_cnt_bypass_en2("true"),
+		.c_cnt_odd_div_duty_en2("false"),
+		.c_cnt_hi_div3(1),
+		.c_cnt_lo_div3(1),
+		.c_cnt_prst3(1),
+		.c_cnt_ph_mux_prst3(0),
+		.c_cnt_in_src3("ph_mux_clk"),
+		.c_cnt_bypass_en3("true"),
+		.c_cnt_odd_div_duty_en3("false"),
+		.c_cnt_hi_div4(1),
+		.c_cnt_lo_div4(1),
+		.c_cnt_prst4(1),
+		.c_cnt_ph_mux_prst4(0),
+		.c_cnt_in_src4("ph_mux_clk"),
+		.c_cnt_bypass_en4("true"),
+		.c_cnt_odd_div_duty_en4("false"),
+		.c_cnt_hi_div5(1),
+		.c_cnt_lo_div5(1),
+		.c_cnt_prst5(1),
+		.c_cnt_ph_mux_prst5(0),
+		.c_cnt_in_src5("ph_mux_clk"),
+		.c_cnt_bypass_en5("true"),
+		.c_cnt_odd_div_duty_en5("false"),
+		.c_cnt_hi_div6(1),
+		.c_cnt_lo_div6(1),
+		.c_cnt_prst6(1),
+		.c_cnt_ph_mux_prst6(0),
+		.c_cnt_in_src6("ph_mux_clk"),
+		.c_cnt_bypass_en6("true"),
+		.c_cnt_odd_div_duty_en6("false"),
+		.c_cnt_hi_div7(1),
+		.c_cnt_lo_div7(1),
+		.c_cnt_prst7(1),
+		.c_cnt_ph_mux_prst7(0),
+		.c_cnt_in_src7("ph_mux_clk"),
+		.c_cnt_bypass_en7("true"),
+		.c_cnt_odd_div_duty_en7("false"),
+		.c_cnt_hi_div8(1),
+		.c_cnt_lo_div8(1),
+		.c_cnt_prst8(1),
+		.c_cnt_ph_mux_prst8(0),
+		.c_cnt_in_src8("ph_mux_clk"),
+		.c_cnt_bypass_en8("true"),
+		.c_cnt_odd_div_duty_en8("false"),
+		.c_cnt_hi_div9(1),
+		.c_cnt_lo_div9(1),
+		.c_cnt_prst9(1),
+		.c_cnt_ph_mux_prst9(0),
+		.c_cnt_in_src9("ph_mux_clk"),
+		.c_cnt_bypass_en9("true"),
+		.c_cnt_odd_div_duty_en9("false"),
+		.c_cnt_hi_div10(1),
+		.c_cnt_lo_div10(1),
+		.c_cnt_prst10(1),
+		.c_cnt_ph_mux_prst10(0),
+		.c_cnt_in_src10("ph_mux_clk"),
+		.c_cnt_bypass_en10("true"),
+		.c_cnt_odd_div_duty_en10("false"),
+		.c_cnt_hi_div11(1),
+		.c_cnt_lo_div11(1),
+		.c_cnt_prst11(1),
+		.c_cnt_ph_mux_prst11(0),
+		.c_cnt_in_src11("ph_mux_clk"),
+		.c_cnt_bypass_en11("true"),
+		.c_cnt_odd_div_duty_en11("false"),
+		.c_cnt_hi_div12(1),
+		.c_cnt_lo_div12(1),
+		.c_cnt_prst12(1),
+		.c_cnt_ph_mux_prst12(0),
+		.c_cnt_in_src12("ph_mux_clk"),
+		.c_cnt_bypass_en12("true"),
+		.c_cnt_odd_div_duty_en12("false"),
+		.c_cnt_hi_div13(1),
+		.c_cnt_lo_div13(1),
+		.c_cnt_prst13(1),
+		.c_cnt_ph_mux_prst13(0),
+		.c_cnt_in_src13("ph_mux_clk"),
+		.c_cnt_bypass_en13("true"),
+		.c_cnt_odd_div_duty_en13("false"),
+		.c_cnt_hi_div14(1),
+		.c_cnt_lo_div14(1),
+		.c_cnt_prst14(1),
+		.c_cnt_ph_mux_prst14(0),
+		.c_cnt_in_src14("ph_mux_clk"),
+		.c_cnt_bypass_en14("true"),
+		.c_cnt_odd_div_duty_en14("false"),
+		.c_cnt_hi_div15(1),
+		.c_cnt_lo_div15(1),
+		.c_cnt_prst15(1),
+		.c_cnt_ph_mux_prst15(0),
+		.c_cnt_in_src15("ph_mux_clk"),
+		.c_cnt_bypass_en15("true"),
+		.c_cnt_odd_div_duty_en15("false"),
+		.c_cnt_hi_div16(1),
+		.c_cnt_lo_div16(1),
+		.c_cnt_prst16(1),
+		.c_cnt_ph_mux_prst16(0),
+		.c_cnt_in_src16("ph_mux_clk"),
+		.c_cnt_bypass_en16("true"),
+		.c_cnt_odd_div_duty_en16("false"),
+		.c_cnt_hi_div17(1),
+		.c_cnt_lo_div17(1),
+		.c_cnt_prst17(1),
+		.c_cnt_ph_mux_prst17(0),
+		.c_cnt_in_src17("ph_mux_clk"),
+		.c_cnt_bypass_en17("true"),
+		.c_cnt_odd_div_duty_en17("false"),
+		.pll_vco_div(2),
+		.pll_cp_current(20),
+		.pll_bwctrl(4000),
+		.pll_output_clk_frequency("445.499999 MHz"),
+		.pll_fractional_division("3908420153"),
+		.mimic_fbclk_type("none"),
+		.pll_fbclk_mux_1("glb"),
+		.pll_fbclk_mux_2("m_cnt"),
+		.pll_m_cnt_in_src("ph_mux_clk"),
+		.pll_slf_rst("true")
 	) altera_pll_i (
 		.rst	(rst),
 		.outclk	({outclk_0}),
 		.locked	(locked),
+		.reconfig_to_pll	(reconfig_to_pll),
 		.fboutclk	( ),
 		.fbclk	(1'b0),
-		.refclk	(refclk)
+		.refclk	(refclk),
+		.reconfig_from_pll	(reconfig_from_pll)
 	);
 endmodule
 
diff --git a/sys/pll_hdmi_cfg.qip b/sys/pll_hdmi_cfg.qip
new file mode 100644
index 0000000..f6447f5
--- /dev/null
+++ b/sys/pll_hdmi_cfg.qip
@@ -0,0 +1,44 @@
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_TOOL_VERSION "17.0"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "pll_hdmi_cfg" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi_cfg.cmp"]
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_NAME "cGxsX2hkbWlfY2Zn"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
+set_global_assignment -entity "pll_hdmi_cfg" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
+
+set_global_assignment -library "pll_hdmi_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi_cfg.v"]
+set_global_assignment -library "pll_hdmi_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi_cfg/altera_pll_reconfig_top.v"]
+set_global_assignment -library "pll_hdmi_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi_cfg/altera_pll_reconfig_core.v"]
+
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_TOOL_VERSION "17.0"
+set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_hdmi_cfg" -name IP_TOOL_ENV "mwpim"
diff --git a/sys/pll_hdmi_cfg.v b/sys/pll_hdmi_cfg.v
new file mode 100644
index 0000000..1ebf6f0
--- /dev/null
+++ b/sys/pll_hdmi_cfg.v
@@ -0,0 +1,86 @@
+// megafunction wizard: %Altera PLL Reconfig v17.0%
+// GENERATION: XML
+// pll_hdmi_cfg.v
+
+// Generated using ACDS version 17.0 598
+
+`timescale 1 ps / 1 ps
+module pll_hdmi_cfg #(
+		parameter ENABLE_BYTEENABLE   = 0,
+		parameter BYTEENABLE_WIDTH    = 4,
+		parameter RECONFIG_ADDR_WIDTH = 6,
+		parameter RECONFIG_DATA_WIDTH = 32,
+		parameter reconf_width        = 64,
+		parameter WAIT_FOR_LOCK       = 1
+	) (
+		input  wire        mgmt_clk,          //          mgmt_clk.clk
+		input  wire        mgmt_reset,        //        mgmt_reset.reset
+		output wire        mgmt_waitrequest,  // mgmt_avalon_slave.waitrequest
+		input  wire        mgmt_read,         //                  .read
+		input  wire        mgmt_write,        //                  .write
+		output wire [31:0] mgmt_readdata,     //                  .readdata
+		input  wire [5:0]  mgmt_address,      //                  .address
+		input  wire [31:0] mgmt_writedata,    //                  .writedata
+		output wire [63:0] reconfig_to_pll,   //   reconfig_to_pll.reconfig_to_pll
+		input  wire [63:0] reconfig_from_pll  // reconfig_from_pll.reconfig_from_pll
+	);
+
+	altera_pll_reconfig_top #(
+		.device_family       ("Cyclone V"),
+		.ENABLE_MIF          (0),
+		.MIF_FILE_NAME       ("sys/pll_hdmi_cfg.mif"),
+		.ENABLE_BYTEENABLE   (ENABLE_BYTEENABLE),
+		.BYTEENABLE_WIDTH    (BYTEENABLE_WIDTH),
+		.RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH),
+		.RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH),
+		.reconf_width        (reconf_width),
+		.WAIT_FOR_LOCK       (WAIT_FOR_LOCK)
+	) pll_hdmi_cfg_inst (
+		.mgmt_clk          (mgmt_clk),          //          mgmt_clk.clk
+		.mgmt_reset        (mgmt_reset),        //        mgmt_reset.reset
+		.mgmt_waitrequest  (mgmt_waitrequest),  // mgmt_avalon_slave.waitrequest
+		.mgmt_read         (mgmt_read),         //                  .read
+		.mgmt_write        (mgmt_write),        //                  .write
+		.mgmt_readdata     (mgmt_readdata),     //                  .readdata
+		.mgmt_address      (mgmt_address),      //                  .address
+		.mgmt_writedata    (mgmt_writedata),    //                  .writedata
+		.reconfig_to_pll   (reconfig_to_pll),   //   reconfig_to_pll.reconfig_to_pll
+		.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
+		.mgmt_byteenable   (4'b0000)            //       (terminated)
+	);
+
+endmodule
+// Retrieval info: <?xml version="1.0"?>
+//<!--
+//	Generated by Altera MegaWizard Launcher Utility version 1.0
+//	************************************************************
+//	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//	************************************************************
+//	Copyright (C) 1991-2018 Altera Corporation
+//	Any megafunction design, and related net list (encrypted or decrypted),
+//	support information, device programming or simulation file, and any other
+//	associated documentation or information provided by Altera or a partner
+//	under Altera's Megafunction Partnership Program may be used only to
+//	program PLD devices (but not masked PLD devices) from Altera.  Any other
+//	use of such megafunction design, net list, support information, device
+//	programming or simulation file, or any other related documentation or
+//	information is prohibited for any other purpose, including, but not
+//	limited to modification, reverse engineering, de-compiling, or use with
+//	any other silicon devices, unless such use is explicitly licensed under
+//	a separate agreement with Altera or a megafunction partner.  Title to
+//	the intellectual property, including patents, copyrights, trademarks,
+//	trade secrets, or maskworks, embodied in any such megafunction design,
+//	net list, support information, device programming or simulation file, or
+//	any other related documentation or information provided by Altera or a
+//	megafunction partner, remains with Altera, the megafunction partner, or
+//	their respective licensors.  No other licenses, including any licenses
+//	needed under any third party's intellectual property, are provided herein.
+//-->
+// Retrieval info: <instance entity-name="altera_pll_reconfig" version="17.0" >
+// Retrieval info: 	<generic name="device_family" value="Cyclone V" />
+// Retrieval info: 	<generic name="ENABLE_MIF" value="false" />
+// Retrieval info: 	<generic name="MIF_FILE_NAME" value="sys/pll_hdmi_cfg.mif" />
+// Retrieval info: 	<generic name="ENABLE_BYTEENABLE" value="false" />
+// Retrieval info: </instance>
+// IPFS_FILES : pll_hdmi_cfg.vo
+// RELATED_FILES: pll_hdmi_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v
diff --git a/sys/pll_hdmi_cfg/altera_pll_reconfig_core.v b/sys/pll_hdmi_cfg/altera_pll_reconfig_core.v
new file mode 100644
index 0000000..4bc1fbb
--- /dev/null
+++ b/sys/pll_hdmi_cfg/altera_pll_reconfig_core.v
@@ -0,0 +1,2184 @@
+// (C) 2001-2017 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1ps/1ps
+
+module altera_pll_reconfig_core
+#(
+    parameter 	reconf_width       	= 64,
+    parameter 	device_family       	= "Stratix V",
+    // MIF Streaming parameters
+    parameter   RECONFIG_ADDR_WIDTH     = 6,
+    parameter   RECONFIG_DATA_WIDTH     = 32,
+    parameter   ROM_ADDR_WIDTH          = 9,
+    parameter   ROM_DATA_WIDTH          = 32,
+    parameter	ROM_NUM_WORDS           = 512
+) ( 
+
+    //input
+    input   wire    mgmt_clk,
+    input   wire    mgmt_reset,
+
+
+    //conduits
+    output  wire [reconf_width-1:0] reconfig_to_pll,
+    input  wire [reconf_width-1:0] reconfig_from_pll,
+
+    // user data (avalon-MM slave interface)
+    output  wire [31:0] mgmt_readdata,
+    output  wire        mgmt_waitrequest,
+    input   wire [5:0]  mgmt_address,
+    input   wire        mgmt_read,
+    input   wire        mgmt_write,
+    input   wire [31:0] mgmt_writedata,
+
+    //other
+    output  wire        mif_start_out,
+    output  reg [ROM_ADDR_WIDTH-1:0]    mif_base_addr
+);
+    localparam mode_WR            = 1'b0;
+    localparam mode_POLL          = 1'b1;
+    localparam MODE_REG           = 6'b000000;
+    localparam STATUS_REG         = 6'b000001;
+    localparam START_REG          = 6'b000010;
+    localparam N_REG              = 6'b000011;
+    localparam M_REG              = 6'b000100;
+    localparam C_COUNTERS_REG     = 6'b000101;
+    localparam DPS_REG            = 6'b000110;
+    localparam DSM_REG            = 6'b000111;
+    localparam BWCTRL_REG         = 6'b001000;
+    localparam CP_CURRENT_REG     = 6'b001001;
+    localparam ANY_DPRIO          = 6'b100000;
+    localparam CNT_BASE           = 5'b001010;
+    localparam VCO_REG              = 6'b011100;
+    localparam MIF_REG            = 6'b011111;
+    
+    //C Counters
+    localparam number_of_counters = 5'd18;
+    localparam  CNT_0 = 1'd0, CNT_1 = 5'd1, CNT_2 = 5'd2,
+                CNT_3 = 5'd3, CNT_4 = 5'd4, CNT_5 = 5'd5,
+                CNT_6 = 5'd6, CNT_7 = 5'd7, CNT_8 = 5'd8,
+                CNT_9 = 5'd9, CNT_10 = 5'd10, CNT_11 = 5'd11,
+                CNT_12 = 5'd12, CNT_13 = 5'd13, CNT_14 = 5'd14,
+                CNT_15 = 5'd15, CNT_16 = 5'd16, CNT_17 = 5'd17;
+    //C counter addresses
+    localparam C_CNT_0_DIV_ADDR = 5'h00;
+    localparam C_CNT_0_DIV_ADDR_DPRIO_1 = 5'h11;
+    localparam C_CNT_0_3_BYPASS_EN_ADDR = 5'h15;
+    localparam C_CNT_0_3_ODD_DIV_EN_ADDR = 5'h17;
+    localparam C_CNT_4_17_BYPASS_EN_ADDR = 5'h14;
+    localparam C_CNT_4_17_ODD_DIV_EN_ADDR = 5'h16;
+    //N counter addresses
+    localparam N_CNT_DIV_ADDR = 5'h13;
+    localparam N_CNT_BYPASS_EN_ADDR = 5'h15;
+    localparam N_CNT_ODD_DIV_EN_ADDR = 5'h17;
+    //M counter addresses
+    localparam M_CNT_DIV_ADDR = 5'h12;
+    localparam M_CNT_BYPASS_EN_ADDR = 5'h15;
+    localparam M_CNT_ODD_DIV_EN_ADDR = 5'h17;
+    
+    //DSM address
+    localparam DSM_K_FRACTIONAL_DIVISION_ADDR_0 = 5'h18;
+    localparam DSM_K_FRACTIONAL_DIVISION_ADDR_1 = 5'h19;
+    localparam DSM_K_READY_ADDR = 5'h17;
+    localparam DSM_K_DITHER_ADDR = 5'h17;
+    localparam DSM_OUT_SEL_ADDR = 6'h30;
+    
+    //Other DSM params
+    localparam DSM_K_READY_BIT_INDEX = 4'd11;
+    //BWCTRL address
+    //Bit 0-3 of addr
+    localparam BWCTRL_ADDR = 6'h30;
+    //CP_CURRENT address
+    //Bit 0-2 of addr
+    localparam CP_CURRENT_ADDR = 6'h31;
+    
+    // VCODIV address
+    localparam VCO_ADDR = 5'h17;
+
+    localparam DPRIO_IDLE = 3'd0, ONE = 3'd1, TWO = 3'd2, THREE = 3'd3, FOUR = 3'd4,
+               FIVE = 3'd5, SIX = 3'd6, SEVEN = 3'd7, EIGHT = 4'd8, NINE = 4'd9, TEN = 4'd10,
+               ELEVEN = 4'd11, TWELVE = 4'd12, THIRTEEN = 4'd13, FOURTEEN = 4'd14, DPRIO_DONE = 4'd15;
+    localparam IDLE = 2'b00, WAIT_ON_LOCK = 2'b01, LOCKED = 2'b10;
+    
+    wire            clk;
+    wire            reset;
+    wire            gnd;
+
+    wire [5: 0]     slave_address;
+    wire            slave_read;
+    wire            slave_write;
+    wire [31: 0]    slave_writedata;
+
+    reg  [31: 0]     slave_readdata_d;
+    reg  [31: 0]     slave_readdata_q;
+    wire            slave_waitrequest;
+    reg             slave_mode;
+
+    assign          clk             = mgmt_clk;
+
+    assign          slave_address       = mgmt_address;
+    assign          slave_read      = mgmt_read;    
+    assign          slave_write     = mgmt_write;
+    assign          slave_writedata     = mgmt_writedata;
+    
+    reg read_waitrequest;
+    // Outputs
+    assign          mgmt_readdata       = slave_readdata_q;
+    assign          mgmt_waitrequest    = slave_waitrequest | read_waitrequest; //Read waitrequest asserted in polling mode
+
+    //internal signals
+    wire            locked_orig;
+    wire            locked;
+   
+    wire            pll_start;
+    wire            pll_start_valid;
+    reg             status_read;
+    wire            read_slave_mode_asserted;
+
+    wire            pll_start_asserted;
+
+    reg  [1:0]      current_state;
+    reg  [1:0]      next_state;
+
+    reg             status;//0=busy, 1=ready
+    //user_mode_init user_mode_init_inst (clk, reset, dprio_mdio_dis, ser_shift_load);
+    //declaring the init wires. These will have 0 on them for 64 clk cycles
+    wire       [ 5:0]  init_dprio_address;
+    wire               init_dprio_read;
+    wire       [ 1:0]  init_dprio_byteen;
+    wire               init_dprio_write;
+    wire       [15:0]  init_dprio_writedata;
+
+    wire               init_atpgmode;
+    wire               init_mdio_dis;
+    wire               init_scanen;
+    wire               init_ser_shift_load;
+    wire               dprio_init_done;
+
+    //DPRIO output signals after initialization is done
+    wire            dprio_clk;
+    reg             avmm_dprio_write;
+    reg             avmm_dprio_read;
+    reg  [5:0]      avmm_dprio_address;
+    reg  [15:0]     avmm_dprio_writedata;
+    reg  [1:0]      avmm_dprio_byteen;
+    wire            avmm_atpgmode;
+    wire            avmm_mdio_dis;
+    wire            avmm_scanen;
+
+    //Final output wires that are muxed between the init and avmm wires.
+    wire            dprio_init_reset;
+    wire [5:0]      dprio_address /*synthesis keep*/;
+    wire            dprio_read/*synthesis keep*/;
+    wire [1:0]      dprio_byteen/*synthesis keep*/;
+    wire            dprio_write/*synthesis keep*/;
+    wire [15:0]     dprio_writedata/*synthesis keep*/;
+    wire            dprio_mdio_dis/*synthesis keep*/;
+    wire            dprio_ser_shift_load/*synthesis keep*/;
+    wire            dprio_atpgmode/*synthesis keep*/;
+    wire            dprio_scanen/*synthesis keep*/;
+
+
+    //other PLL signals for dyn ph shift
+    wire            phase_done/*synthesis keep*/;
+    wire            phase_en/*synthesis keep*/;
+    wire            up_dn/*synthesis keep*/;
+    wire  [4:0]     cnt_sel;
+    
+    //DPRIO input signals
+    wire  [15:0]     dprio_readdata;
+
+    //internal logic signals
+    //storage registers for user sent data
+    reg             dprio_temp_read_1;
+    reg             dprio_temp_read_2;
+    reg             dprio_start;
+    reg             mif_start_assert;
+    reg             dps_start_assert;
+    wire            usr_valid_changes;
+    reg  [3:0]      dprio_cur_state;
+    reg  [3:0]      dprio_next_state;
+    reg  [15:0]     dprio_temp_m_n_c_readdata_1_d;
+    reg  [15:0]     dprio_temp_m_n_c_readdata_2_d;
+    reg  [15:0]     dprio_temp_m_n_c_readdata_1_q;
+    reg  [15:0]     dprio_temp_m_n_c_readdata_2_q;
+	reg 			dprio_write_done;
+    //C counters signals
+    reg  [7:0]      usr_c_cnt_lo;
+    reg  [7:0]      usr_c_cnt_hi;
+    reg             usr_c_cnt_bypass_en;
+    reg             usr_c_cnt_odd_duty_div_en;
+    reg  [7:0]      temp_c_cnt_lo [0:17]; 
+    reg  [7:0]      temp_c_cnt_hi [0:17];
+    reg             temp_c_cnt_bypass_en [0:17];
+    reg      	    temp_c_cnt_odd_duty_div_en [0:17];
+    reg             any_c_cnt_changed;
+    reg             all_c_cnt_done_q;
+    reg             all_c_cnt_done_d;
+    reg  [17:0]     c_cnt_changed;
+    reg  [17:0]     c_cnt_done_d;
+    reg  [17:0]     c_cnt_done_q;
+    //N counter signals
+    reg  [7:0]      usr_n_cnt_lo; 
+    reg  [7:0]      usr_n_cnt_hi;
+    reg             usr_n_cnt_bypass_en;
+    reg             usr_n_cnt_odd_duty_div_en;
+    reg             n_cnt_changed;
+    reg             n_cnt_done_d;
+    reg             n_cnt_done_q;
+    //M counter signals
+    reg  [7:0]      usr_m_cnt_lo; 
+    reg  [7:0]      usr_m_cnt_hi;
+    reg             usr_m_cnt_bypass_en;
+    reg             usr_m_cnt_odd_duty_div_en;
+    reg             m_cnt_changed;
+    reg             m_cnt_done_d;
+    reg             m_cnt_done_q;
+    //dyn phase regs
+    reg  [15:0]     usr_num_shifts;
+    reg  [4:0]      usr_cnt_sel /*synthesis preserve*/;
+    reg             usr_up_dn;
+    reg             dps_changed;
+    wire            dps_changed_valid;
+    wire            dps_done;
+
+    //DSM Signals
+    reg  [31:0]     usr_k_value;
+    reg             dsm_k_changed;
+    reg             dsm_k_done_d;
+    reg             dsm_k_done_q;
+    reg             dsm_k_ready_false_done_d;
+    //BW signals 
+    reg [3:0]       usr_bwctrl_value;
+    reg             bwctrl_changed;
+    reg             bwctrl_done_d;
+    reg             bwctrl_done_q;
+    //CP signals 
+    reg [2:0]       usr_cp_current_value;
+    reg             cp_current_changed;
+    reg             cp_current_done_d;
+    reg             cp_current_done_q;
+    //VCO signals 
+    reg             usr_vco_value;
+    reg             vco_changed;
+    reg             vco_done_d;
+    reg             vco_done_q;
+    //Manual DPRIO signals
+    reg             manual_dprio_done_q;
+    reg             manual_dprio_done_d;
+    reg             manual_dprio_changed;
+    reg  [5:0]      usr_dprio_address;
+    reg  [15:0]     usr_dprio_writedata_0;
+    reg             usr_r_w;
+	 //keeping track of which operation happened last
+	 reg  [5:0]		  operation_address;
+    // Address wires for all C_counter DPRIO registers
+    // These are outputs of LUTS, changing depending
+    // on whether PLL_0 or PLL_1 being used
+
+
+    //Fitter will tell if FPLL1 is being used 
+    wire            fpll_1;
+
+    // other
+    reg             mif_reg_asserted;
+    // MAIN FSM                             
+
+    // Synchronize locked signal
+   altera_std_synchronizer #(
+        .depth(3)
+    ) altera_std_synchronizer_inst (
+        .clk(mgmt_clk),
+        .reset_n(~mgmt_reset), 
+        .din(locked_orig),
+        .dout(locked)
+    );
+   
+    always @(posedge clk)
+    begin
+        if (reset)
+        begin
+            dprio_cur_state <= DPRIO_IDLE;
+            current_state <= IDLE;
+        end
+        else
+        begin
+            current_state <= next_state;
+            dprio_cur_state <= dprio_next_state;
+        end
+    end
+
+    always @(*)
+     begin
+        case(current_state)
+          IDLE:
+            begin
+               if (pll_start & !slave_waitrequest & usr_valid_changes)
+                 next_state = WAIT_ON_LOCK;
+               else
+                 next_state = IDLE;
+            end
+          WAIT_ON_LOCK:
+            begin
+               if (locked & dps_done & dprio_write_done)  // received locked high from PLL
+                 begin
+                    if (slave_mode==mode_WR) //if the mode is waitrequest, then
+                                             // goto IDLE state directly
+                      next_state = IDLE;
+                    else
+                      next_state = LOCKED; //otherwise go the locked state
+                 end
+               else
+                  next_state = WAIT_ON_LOCK;
+            end
+              
+          LOCKED:
+            begin
+               if (status_read) // stay in LOCKED until user reads status 
+                 next_state = IDLE;
+               else
+                 next_state = LOCKED;
+            end
+
+          default: next_state = 2'bxx;
+          
+        endcase
+     end
+
+
+    // ask the pll to start reconfig
+    assign pll_start = (pll_start_asserted & (current_state==IDLE))  ;
+    assign pll_start_valid = (pll_start & (next_state==WAIT_ON_LOCK))  ;
+
+
+
+    // WRITE OPERATIONS
+    assign pll_start_asserted = slave_write & (slave_address == START_REG);
+    assign mif_start_out = pll_start & mif_reg_asserted;
+
+    //reading the mode register to determine what mode the slave will operate
+    //in.
+    always @(posedge clk)
+    begin
+        if (reset)
+          slave_mode <= mode_WR;
+        else if (slave_write & (slave_address == MODE_REG) & !slave_waitrequest)
+          slave_mode <= slave_writedata[0];
+    end
+
+    //record which values user wants to change.
+
+    //reading in the actual values that need to be reconfigged and sending
+    //them to the PLL
+    always @(posedge clk)
+    begin
+        if (reset)
+        begin
+            //reset all regs here
+            //BW signals reset
+            usr_bwctrl_value <= 0;
+            bwctrl_changed <= 0;
+            bwctrl_done_q <= 0;
+            //CP signals reset
+            usr_cp_current_value <= 0;
+            cp_current_changed <= 0;
+            cp_current_done_q <= 0;
+            //VCO signals reset
+            usr_vco_value <= 0;
+            vco_changed <= 0;
+            vco_done_q <= 0;
+            //DSM signals reset
+            usr_k_value <= 0;
+            dsm_k_changed <= 0;
+            dsm_k_done_q <= 0;
+            //N counter signals reset
+            usr_n_cnt_lo <= 0;
+            usr_n_cnt_hi <= 0;
+            usr_n_cnt_bypass_en <= 0;
+            usr_n_cnt_odd_duty_div_en <= 0;
+            n_cnt_changed <= 0;
+            n_cnt_done_q <= 0;
+            //M counter signals reset
+            usr_m_cnt_lo <= 0;
+            usr_m_cnt_hi <= 0;
+            usr_m_cnt_bypass_en <= 0;
+            usr_m_cnt_odd_duty_div_en <= 0;
+            m_cnt_changed <= 0;
+            m_cnt_done_q <= 0;
+            //C counter signals reset
+            usr_c_cnt_lo <= 0;
+            usr_c_cnt_hi <= 0;
+            usr_c_cnt_bypass_en <= 0;
+            usr_c_cnt_odd_duty_div_en <= 0;
+            any_c_cnt_changed <= 0;
+            all_c_cnt_done_q <= 0;
+            c_cnt_done_q <= 0;
+            //generic signals
+            dprio_start <= 0;
+            mif_start_assert <= 0;
+            dps_start_assert <= 0;
+            dprio_temp_m_n_c_readdata_1_q <= 0;
+            dprio_temp_m_n_c_readdata_2_q <= 0;
+            c_cnt_done_q <= 0;
+            //DPS signals
+            usr_up_dn <= 0;
+            usr_cnt_sel <= 0;
+            usr_num_shifts <= 0;
+            dps_changed <= 0;
+            //manual DPRIO signals
+            manual_dprio_changed <= 0;
+            usr_dprio_address <= 0;
+            usr_dprio_writedata_0 <= 0;
+            usr_r_w <= 0;
+	    operation_address <= 0;
+            mif_reg_asserted <= 0;
+            mif_base_addr <= 0;
+        end
+        else
+        begin
+            if (dprio_temp_read_1)
+            begin
+                dprio_temp_m_n_c_readdata_1_q <= dprio_temp_m_n_c_readdata_1_d; 
+            end
+            if (dprio_temp_read_2)
+            begin
+                dprio_temp_m_n_c_readdata_2_q <= dprio_temp_m_n_c_readdata_2_d; 
+            end
+            if ((dps_done)) dps_changed <= 0;
+            if (dsm_k_done_d) dsm_k_done_q <= dsm_k_done_d;
+            if (n_cnt_done_d) n_cnt_done_q <= n_cnt_done_d;
+            if (m_cnt_done_d) m_cnt_done_q <= m_cnt_done_d;
+            if (all_c_cnt_done_d) all_c_cnt_done_q <= all_c_cnt_done_d;
+            if (c_cnt_done_d != 0) c_cnt_done_q <= c_cnt_done_q | c_cnt_done_d;
+            if (bwctrl_done_d) bwctrl_done_q <= bwctrl_done_d;
+            if (cp_current_done_d) cp_current_done_q <= cp_current_done_d;
+            if (vco_done_d) vco_done_q <= vco_done_d;
+            if (manual_dprio_done_d) manual_dprio_done_q <= manual_dprio_done_d;
+
+            if (mif_start_out == 1'b1)
+                mif_start_assert <= 0; // Signaled MIF block to start, so deassert on next cycle
+            
+            if (dps_done != 1'b1)
+                dps_start_assert <= 0; // DPS has started, so dessert its start signal on next cycle
+
+            if (dprio_next_state == ONE)
+                dprio_start <= 0;
+            if (dprio_write_done)
+            begin
+                bwctrl_done_q <= 0;
+                cp_current_done_q <= 0;
+                vco_done_q <= 0;
+                dsm_k_done_q <= 0;
+                dsm_k_done_q <= 0;
+                n_cnt_done_q <= 0;
+                m_cnt_done_q <= 0;
+                all_c_cnt_done_q <= 0;
+                c_cnt_done_q <= 0;
+                dsm_k_changed <= 0;
+                n_cnt_changed <= 0;
+                m_cnt_changed <= 0;
+                any_c_cnt_changed <= 0;
+                bwctrl_changed <= 0;
+                cp_current_changed <= 0;
+                vco_changed <= 0;
+                manual_dprio_changed <= 0;
+                manual_dprio_done_q <= 0;
+                if (dps_changed | dps_changed_valid | !dps_done )
+                begin
+                    usr_cnt_sel <= usr_cnt_sel;
+                end
+                else 
+                begin
+                    usr_cnt_sel <= 0;
+                end
+                mif_reg_asserted <= 0;
+            end
+            else 
+            begin
+                dsm_k_changed <= dsm_k_changed;
+                n_cnt_changed <= n_cnt_changed;
+                m_cnt_changed <= m_cnt_changed;
+                any_c_cnt_changed <= any_c_cnt_changed;
+                manual_dprio_changed <= manual_dprio_changed;
+                mif_reg_asserted <= mif_reg_asserted;
+                usr_cnt_sel <= usr_cnt_sel;
+            end
+
+
+            if(slave_write & !slave_waitrequest)
+            begin
+                case(slave_address)
+                   //read in the values here from the user and act on them
+                DSM_REG:
+                begin
+                    operation_address <= DSM_REG;
+                    usr_k_value <= slave_writedata[31:0]; 
+                    dsm_k_changed <= 1'b1;
+                    dsm_k_done_q <= 0;
+                    dprio_start <= 1'b1;
+                end
+                N_REG:
+                begin
+                    operation_address <= N_REG;
+                    usr_n_cnt_lo <= slave_writedata[7:0]; 
+                    usr_n_cnt_hi <= slave_writedata[15:8];
+                    usr_n_cnt_bypass_en <= slave_writedata[16];
+                    usr_n_cnt_odd_duty_div_en <= slave_writedata[17];
+                    n_cnt_changed <= 1'b1;
+                    n_cnt_done_q <= 0;
+                    dprio_start <= 1'b1;
+                end
+                M_REG:
+                begin
+                    operation_address <= M_REG;
+                    usr_m_cnt_lo <= slave_writedata[7:0]; 
+                    usr_m_cnt_hi <= slave_writedata[15:8];
+                    usr_m_cnt_bypass_en <= slave_writedata[16];
+                    usr_m_cnt_odd_duty_div_en <= slave_writedata[17];
+                    m_cnt_changed <= 1'b1;
+                    m_cnt_done_q <= 0;
+                    dprio_start <= 1'b1;
+                end
+                DPS_REG:
+                begin
+                    operation_address <= DPS_REG;
+                    usr_num_shifts <= slave_writedata[15:0];
+                    usr_cnt_sel <= slave_writedata[20:16];
+                    usr_up_dn <= slave_writedata[21];
+                    dps_changed <= 1;
+                    dps_start_assert <= 1;
+                end
+                C_COUNTERS_REG:
+                begin
+						  operation_address <= C_COUNTERS_REG;
+                    usr_c_cnt_lo <= slave_writedata[7:0]; 
+                    usr_c_cnt_hi <= slave_writedata[15:8];
+                    usr_c_cnt_bypass_en <= slave_writedata[16];
+                    usr_c_cnt_odd_duty_div_en <= slave_writedata[17];
+                    usr_cnt_sel <= slave_writedata[22:18];
+                    any_c_cnt_changed <= 1'b1;
+                    all_c_cnt_done_q <= 0;
+                    dprio_start <= 1'b1;
+                end
+                BWCTRL_REG:
+                begin
+                    usr_bwctrl_value <= slave_writedata[3:0]; 
+                    bwctrl_changed <= 1'b1;
+                    bwctrl_done_q <= 0;
+                    dprio_start <= 1'b1;
+		    	  operation_address <= BWCTRL_REG;
+                end
+                CP_CURRENT_REG:
+                begin
+                    usr_cp_current_value <= slave_writedata[2:0]; 
+                    cp_current_changed <= 1'b1;
+                    cp_current_done_q <= 0;
+                    dprio_start <= 1'b1;
+		    operation_address <= CP_CURRENT_REG;
+                end
+                VCO_REG:
+                begin
+                    usr_vco_value <= slave_writedata[0]; 
+                    vco_changed <= 1'b1;
+                    vco_done_q <= 0;
+                    dprio_start <= 1'b1;
+		    operation_address <= VCO_REG;
+                end
+                ANY_DPRIO:
+                begin
+						  operation_address <= ANY_DPRIO;
+                    manual_dprio_changed <= 1'b1;
+                    usr_dprio_address <= slave_writedata[5:0];
+                    usr_dprio_writedata_0 <= slave_writedata[21:6];
+                    usr_r_w <= slave_writedata[22];
+                    manual_dprio_done_q <= 0;
+                    dprio_start <= 1'b1;
+                end
+                MIF_REG:
+                begin
+                    mif_reg_asserted <= 1'b1;
+                    mif_base_addr <= slave_writedata[ROM_ADDR_WIDTH-1:0];
+                    mif_start_assert <= 1'b1;
+                end                
+                endcase
+             end
+        end 
+    end
+    //C Counter assigning values to the 2-d array of values for each C counter
+   
+    reg [4:0] j;
+    always @(posedge clk)
+    begin
+
+        if (reset)
+        begin
+            c_cnt_changed[17:0] <= 0;
+            for (j = 0; j < number_of_counters; j = j + 1'b1)
+            begin : c_cnt_reset
+                temp_c_cnt_bypass_en[j] <= 0;
+                temp_c_cnt_odd_duty_div_en[j] <= 0;
+                temp_c_cnt_lo[j][7:0] <= 0;
+                temp_c_cnt_hi[j][7:0] <= 0;
+            end
+        end
+        else 
+        begin
+            if (dprio_write_done)
+            begin
+                c_cnt_changed <= 0;
+            end
+            if (any_c_cnt_changed && (operation_address == C_COUNTERS_REG))
+            begin
+                case (cnt_sel)
+                    CNT_0:
+                    begin
+                        temp_c_cnt_lo [0] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [0] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [0] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [0] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [0] <= 1'b1;
+                    end
+                    CNT_1:
+                    begin
+                        temp_c_cnt_lo [1] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [1] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [1] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [1] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [1] <= 1'b1;
+                    end
+                    CNT_2:
+                    begin
+                        temp_c_cnt_lo [2] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [2] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [2] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [2] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [2] <= 1'b1;
+                    end
+                    CNT_3:
+                    begin
+                        temp_c_cnt_lo [3] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [3] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [3] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [3] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [3] <= 1'b1;
+                    end
+                    CNT_4:
+                    begin
+                        temp_c_cnt_lo [4] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [4] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [4] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [4] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [4] <= 1'b1;
+                    end
+                    CNT_5:
+                    begin
+                        temp_c_cnt_lo [5] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [5] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [5] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [5] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [5] <= 1'b1;
+                    end
+                    CNT_6:
+                    begin
+                        temp_c_cnt_lo [6] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [6] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [6] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [6] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [6] <= 1'b1;
+                    end
+                    CNT_7:
+                    begin
+                        temp_c_cnt_lo [7] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [7] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [7] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [7] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [7] <= 1'b1;
+                    end
+                    CNT_8:
+                    begin
+                        temp_c_cnt_lo [8] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [8] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [8] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [8] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [8] <= 1'b1;
+                    end
+                    CNT_9:
+                    begin
+                        temp_c_cnt_lo [9] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [9] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [9] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [9] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [9] <= 1'b1;
+                    end
+                    CNT_10:
+                    begin
+                        temp_c_cnt_lo [10] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [10] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [10] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [10] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [10] <= 1'b1;
+                    end
+                    CNT_11:
+                    begin
+                        temp_c_cnt_lo [11] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [11] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [11] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [11] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [11] <= 1'b1;
+                    end
+                    CNT_12:
+                    begin
+                        temp_c_cnt_lo [12] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [12] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [12] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [12] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [12] <= 1'b1;
+                    end
+                    CNT_13:
+                    begin
+                        temp_c_cnt_lo [13] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [13] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [13] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [13] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [13] <= 1'b1;
+                    end
+                    CNT_14:
+                    begin
+                        temp_c_cnt_lo [14] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [14] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [14] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [14] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [14] <= 1'b1;
+                    end
+                    CNT_15:
+                    begin
+                        temp_c_cnt_lo [15] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [15] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [15] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [15] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [15] <= 1'b1;
+                    end
+                    CNT_16:
+                    begin
+                        temp_c_cnt_lo [16] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [16] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [16] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [16] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [16] <= 1'b1;
+                    end
+                    CNT_17:
+                    begin
+                        temp_c_cnt_lo [17] <= usr_c_cnt_lo;
+                        temp_c_cnt_hi [17] <= usr_c_cnt_hi;
+                        temp_c_cnt_bypass_en [17] <= usr_c_cnt_bypass_en;
+                        temp_c_cnt_odd_duty_div_en [17] <= usr_c_cnt_odd_duty_div_en;
+                        c_cnt_changed [17] <= 1'b1;
+                    end
+                endcase
+
+            end
+        end
+    end
+
+
+    //logic to handle which writes the user indicated and wants to start.
+    assign usr_valid_changes =dsm_k_changed| any_c_cnt_changed |n_cnt_changed | m_cnt_changed | dps_changed_valid |manual_dprio_changed |cp_current_changed|bwctrl_changed|vco_changed;
+
+     
+    //start the reconfig operations by writing to the DPRIO
+    reg break_loop;
+    reg [4:0] i;
+    always @(*)
+    begin 
+        dprio_temp_read_1 = 0;
+        dprio_temp_read_2 = 0;
+        dprio_temp_m_n_c_readdata_1_d = 0;
+        dprio_temp_m_n_c_readdata_2_d = 0;
+        break_loop = 0;
+        dprio_next_state = DPRIO_IDLE;
+        avmm_dprio_write = 0;
+        avmm_dprio_read = 0;
+        avmm_dprio_address = 0;
+        avmm_dprio_writedata = 0;
+        avmm_dprio_byteen = 0;
+        dprio_write_done = 1;
+        manual_dprio_done_d = 0;
+        n_cnt_done_d = 0;
+        dsm_k_done_d = 0;
+        dsm_k_ready_false_done_d = 0;
+        m_cnt_done_d = 0;
+        c_cnt_done_d[17:0] = 0;
+        all_c_cnt_done_d = 0;
+        bwctrl_done_d = 0;
+        cp_current_done_d = 0;
+        vco_done_d = 0;
+        i = 0;
+       
+        // Deassert dprio_write_done so it doesn't reset mif_reg_asserted (toggled writes) 
+        if (dprio_start | mif_start_assert)
+            dprio_write_done = 0;
+
+        if (current_state == WAIT_ON_LOCK)
+        begin
+            case (dprio_cur_state)
+                ONE:
+                begin
+                    if (n_cnt_changed & !n_cnt_done_q) 
+                    begin
+			dprio_write_done = 0;
+                    	avmm_dprio_write = 1'b1;
+                    	avmm_dprio_byteen = 2'b11;
+                    	dprio_next_state = TWO;
+                        avmm_dprio_address = N_CNT_DIV_ADDR;
+                        avmm_dprio_writedata[7:0] = usr_n_cnt_lo;
+                        avmm_dprio_writedata[15:8] = usr_n_cnt_hi;
+                    end
+                    else if (m_cnt_changed & !m_cnt_done_q) 
+                    begin
+		    	dprio_write_done = 0;
+                    	avmm_dprio_write = 1'b1;
+                    	avmm_dprio_byteen = 2'b11;
+                    	dprio_next_state = TWO;
+                        avmm_dprio_address = M_CNT_DIV_ADDR;
+                        avmm_dprio_writedata[7:0] = usr_m_cnt_lo;
+                        avmm_dprio_writedata[15:8] = usr_m_cnt_hi;
+                    end
+                    else if (any_c_cnt_changed & !all_c_cnt_done_q)
+                    begin
+
+                        for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
+                        begin : c_cnt_write_hilo
+                            if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                            begin
+				dprio_write_done = 0;
+	                    	avmm_dprio_write = 1'b1;
+        	            	avmm_dprio_byteen = 2'b11;
+                	    	dprio_next_state = TWO;
+                                if (fpll_1) avmm_dprio_address = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - i;
+                                else avmm_dprio_address = C_CNT_0_DIV_ADDR + i;
+                                avmm_dprio_writedata[7:0] = temp_c_cnt_lo[i];
+                                avmm_dprio_writedata[15:8] = temp_c_cnt_hi[i];
+                                //To break from the loop, since only one counter
+                                //is addressed at a time
+                                break_loop = 1'b1;
+                            end
+                        end
+                    end
+                    else if (dsm_k_changed & !dsm_k_done_q) 
+                    begin
+		    	dprio_write_done = 0;
+                        avmm_dprio_write = 0;
+                        dprio_next_state = TWO;
+                    end
+                    else if (bwctrl_changed & !bwctrl_done_q) 
+                    begin
+		    	dprio_write_done = 0;
+                        avmm_dprio_write = 0;
+                        dprio_next_state = TWO;
+                    end
+                    else if (cp_current_changed & !cp_current_done_q) 
+                    begin
+		    	dprio_write_done = 0;		    
+                        avmm_dprio_write = 0;
+                        dprio_next_state = TWO;
+                    end
+                    else if (vco_changed & !vco_done_q) 
+                    begin
+		    	dprio_write_done = 0;		    
+                        avmm_dprio_write = 0;
+                        dprio_next_state = TWO;
+                    end
+                    else if (manual_dprio_changed & !manual_dprio_done_q)
+                    begin
+		    	dprio_write_done = 0;
+                    	avmm_dprio_byteen = 2'b11;
+                    	dprio_next_state = TWO;		    
+                        avmm_dprio_write = usr_r_w;
+                        avmm_dprio_address = usr_dprio_address;
+                        avmm_dprio_writedata[15:0] = usr_dprio_writedata_0;
+                    end
+                    else dprio_next_state = DPRIO_IDLE;
+                end
+            
+                TWO:
+                begin
+                    //handle reading the two setting bits on n_cnt, then
+                    //writing them back while preserving other bits.
+                    //Issue two consecutive reads then wait; readLatency=3
+                    dprio_write_done = 0;
+                    dprio_next_state = THREE;
+                    avmm_dprio_byteen = 2'b11;
+                    avmm_dprio_read = 1'b1;
+                    if (n_cnt_changed & !n_cnt_done_q)
+                    begin
+                        avmm_dprio_address = N_CNT_BYPASS_EN_ADDR;
+                    end
+                    else if (m_cnt_changed & !m_cnt_done_q)
+                    begin
+                        avmm_dprio_address = M_CNT_BYPASS_EN_ADDR;
+                    end
+                   
+                    else if (any_c_cnt_changed & !all_c_cnt_done_q)
+                    begin
+                        for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
+                        begin : c_cnt_read_bypass
+                            if (fpll_1)
+                            begin
+                                if (i > 13)
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                            end
+                            else
+                            begin
+                                if (i < 4)
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                            end
+                        end
+                    end
+                    //reading the K ready 16 bit word. Need to write 0 to it
+                    //afterwards to indicate that K has not been done writing
+                    else if (dsm_k_changed & !dsm_k_done_q) 
+                    begin
+                        avmm_dprio_address = DSM_K_READY_ADDR;
+                        dprio_next_state = FOUR;
+                    end
+                    else if (bwctrl_changed & !bwctrl_done_q) 
+                    begin
+                        avmm_dprio_address = BWCTRL_ADDR;
+                        dprio_next_state = FOUR;
+                    end
+                    else if (cp_current_changed & !cp_current_done_q) 
+                    begin
+                        avmm_dprio_address = CP_CURRENT_ADDR;
+                        dprio_next_state = FOUR;
+                    end
+                    else if (vco_changed & !vco_done_q) 
+                    begin
+                        avmm_dprio_address = VCO_ADDR;
+                        dprio_next_state = FOUR;
+                    end
+                    else if (manual_dprio_changed & !manual_dprio_done_q)
+                    begin
+                        avmm_dprio_read = ~usr_r_w;
+                        avmm_dprio_address = usr_dprio_address;
+                        dprio_next_state = DPRIO_DONE;
+                    end
+                    else dprio_next_state = DPRIO_IDLE;
+                end       
+                THREE:
+                begin
+                    dprio_write_done = 0;
+                    avmm_dprio_byteen = 2'b11;
+                    avmm_dprio_read = 1'b1;
+                    dprio_next_state = FOUR;
+                    if (n_cnt_changed & !n_cnt_done_q)
+                    begin
+                        avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR;
+                    end
+                    else if (m_cnt_changed & !m_cnt_done_q)
+                    begin
+                        avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR;
+                    end
+                    else if (any_c_cnt_changed & !all_c_cnt_done_q)
+                    begin
+                        for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
+                        begin : c_cnt_read_odd_div
+                            if (fpll_1)
+                            begin
+                                if (i > 13)
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                            end
+                            else
+                            begin
+                                if (i < 4)
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                            end
+                        end
+                    end   
+                    else dprio_next_state = DPRIO_IDLE;
+                end
+                FOUR:
+                begin
+                    dprio_temp_read_1 = 1'b1;
+                    dprio_write_done = 0;
+                    if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed)
+                    begin
+                        dprio_temp_m_n_c_readdata_1_d = dprio_readdata;
+                        dprio_next_state = FIVE;
+                    end
+                    else dprio_next_state = DPRIO_IDLE;
+                end
+                FIVE:
+                begin
+                    dprio_write_done = 0;
+                    dprio_temp_read_2 = 1'b1;
+                    if (vco_changed|cp_current_changed|bwctrl_changed|dsm_k_changed|n_cnt_changed|m_cnt_changed|any_c_cnt_changed)
+                    begin
+                        //this is where DSM ready value comes.
+                        //Need to store in a register to be used later
+                        dprio_temp_m_n_c_readdata_2_d = dprio_readdata;
+                        dprio_next_state = SIX;
+                    end
+                    else dprio_next_state = DPRIO_IDLE;
+                end
+                SIX:
+                begin
+                    dprio_write_done = 0;
+                    avmm_dprio_write = 1'b1;
+                    avmm_dprio_byteen = 2'b11;
+                    dprio_next_state = SEVEN;
+                    avmm_dprio_writedata = dprio_temp_m_n_c_readdata_1_q;
+                    if (n_cnt_changed & !n_cnt_done_q)
+                    begin
+                        avmm_dprio_address = N_CNT_BYPASS_EN_ADDR;
+                        avmm_dprio_writedata[5] = usr_n_cnt_bypass_en;
+                    end
+                    else if (m_cnt_changed & !m_cnt_done_q)
+                    begin
+                        avmm_dprio_address = M_CNT_BYPASS_EN_ADDR;
+                        avmm_dprio_writedata[4] = usr_m_cnt_bypass_en;
+                    end
+                    else if (any_c_cnt_changed & !all_c_cnt_done_q)
+                    begin
+                        for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
+                        begin : c_cnt_write_bypass
+                            if (fpll_1)
+                            begin
+                                if (i > 13)
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
+                                        avmm_dprio_writedata[i-14] = temp_c_cnt_bypass_en[i];
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
+                                        avmm_dprio_writedata[i] = temp_c_cnt_bypass_en[i];
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                            end
+                            else
+                            begin
+                                if (i < 4)
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_0_3_BYPASS_EN_ADDR;
+                                        avmm_dprio_writedata[3-i] = temp_c_cnt_bypass_en[i];
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_4_17_BYPASS_EN_ADDR;
+                                        avmm_dprio_writedata[17-i] = temp_c_cnt_bypass_en[i];
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                            end
+                        end
+                    end    
+                    else if (dsm_k_changed & !dsm_k_done_q)
+                    begin
+                        avmm_dprio_write = 0;
+                    end
+                    else if (bwctrl_changed & !bwctrl_done_q) 
+                    begin
+                        avmm_dprio_write = 0;
+                    end
+                    else if (cp_current_changed & !cp_current_done_q) 
+                    begin
+                        avmm_dprio_write = 0;
+                    end
+                    else if (vco_changed & !vco_done_q) 
+                    begin
+                        avmm_dprio_write = 0;
+                    end
+                    else dprio_next_state = DPRIO_IDLE;
+                end
+                SEVEN:
+                begin
+                    dprio_write_done = 0;
+                    dprio_next_state = EIGHT;
+                    avmm_dprio_write = 1'b1;
+                    avmm_dprio_byteen = 2'b11;
+                    avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q;
+                    if (n_cnt_changed & !n_cnt_done_q)
+                    begin
+                        avmm_dprio_address = N_CNT_ODD_DIV_EN_ADDR;
+                        avmm_dprio_writedata[5] = usr_n_cnt_odd_duty_div_en;
+                        n_cnt_done_d = 1'b1;
+                    end
+                    else if (m_cnt_changed & !m_cnt_done_q)
+                    begin
+                        avmm_dprio_address = M_CNT_ODD_DIV_EN_ADDR;
+                        avmm_dprio_writedata[4] = usr_m_cnt_odd_duty_div_en;
+                        m_cnt_done_d = 1'b1;
+                    end
+                         
+                    else if (any_c_cnt_changed & !all_c_cnt_done_q)
+                    begin
+                        for (i = 0; (i < number_of_counters) & !break_loop; i = i + 1'b1)
+                        begin : c_cnt_write_odd_div
+                            if (fpll_1)
+                            begin
+                                if (i > 13)
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
+                                        avmm_dprio_writedata[i-14] = temp_c_cnt_odd_duty_div_en[i];
+                                        c_cnt_done_d[i] = 1'b1;
+                                        //have to OR the signals to prevent
+                                        //overwriting of previous dones
+                                        c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
+                                        avmm_dprio_writedata[i] = temp_c_cnt_odd_duty_div_en[i];
+                                        c_cnt_done_d[i] = 1'b1;
+                                        c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                            end
+                            else
+                            begin
+                                if (i < 4)
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_0_3_ODD_DIV_EN_ADDR;
+                                        avmm_dprio_writedata[3-i] = temp_c_cnt_odd_duty_div_en[i];
+                                        c_cnt_done_d[i] = 1'b1;
+                                        //have to OR the signals to prevent
+                                        //overwriting of previous dones
+                                        c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                                else
+                                begin
+                                    if (c_cnt_changed[i] & !c_cnt_done_q[i])
+                                    begin
+                                        avmm_dprio_address = C_CNT_4_17_ODD_DIV_EN_ADDR;
+                                        avmm_dprio_writedata[17-i] = temp_c_cnt_odd_duty_div_en[i];
+                                        c_cnt_done_d[i] = 1'b1;
+                                        c_cnt_done_d = c_cnt_done_d | c_cnt_done_q;
+                                        break_loop = 1'b1;
+                                    end
+                                end
+                            end
+                        end
+                    end
+                    else if (dsm_k_changed & !dsm_k_done_q)
+                    begin
+                        avmm_dprio_address = DSM_K_READY_ADDR;
+                        avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b0;
+                        dsm_k_ready_false_done_d = 1'b1;
+                    end
+                    else if (bwctrl_changed & !bwctrl_done_q) 
+                    begin
+                        avmm_dprio_address = BWCTRL_ADDR;
+                        avmm_dprio_writedata[3:0] = usr_bwctrl_value;
+                        bwctrl_done_d = 1'b1;
+                    end
+                    else if (cp_current_changed & !cp_current_done_q) 
+                    begin
+                        avmm_dprio_address = CP_CURRENT_ADDR;
+                        avmm_dprio_writedata[2:0] = usr_cp_current_value;
+                        cp_current_done_d = 1'b1;
+                    end
+                    else if (vco_changed & !vco_done_q) 
+                    begin
+                        avmm_dprio_address = VCO_ADDR;
+                        avmm_dprio_writedata[8] = usr_vco_value;
+                        vco_done_d = 1'b1;
+                    end
+
+                   
+                    //if all C_cnt that were changed are done, then assert all_c_cnt_done
+                    if (c_cnt_done_d == c_cnt_changed)
+                        all_c_cnt_done_d = 1'b1;
+                    if (n_cnt_changed & n_cnt_done_d)
+                        dprio_next_state = DPRIO_DONE;
+                    if (any_c_cnt_changed & !all_c_cnt_done_d & !all_c_cnt_done_q)
+                        dprio_next_state = ONE;
+                    else if (m_cnt_changed & !m_cnt_done_d & !m_cnt_done_q)
+                        dprio_next_state = ONE;
+                    else if (dsm_k_changed & !dsm_k_ready_false_done_d)
+                        dprio_next_state = TWO;
+                    else if (dsm_k_changed & !dsm_k_done_q)
+                        dprio_next_state = EIGHT;
+                    else if (bwctrl_changed & !bwctrl_done_d)
+                        dprio_next_state = TWO;
+                    else if (cp_current_changed & !cp_current_done_d)
+                        dprio_next_state = TWO;
+                    else if (vco_changed & !vco_done_d)
+                        dprio_next_state = TWO;
+                    else 
+                    begin
+                        dprio_next_state = DPRIO_DONE;
+                        dprio_write_done = 1'b1;
+                    end
+                end
+                //finish the rest of the DSM reads/writes
+                //writing k value, writing k_ready to 1.
+                EIGHT: 
+                begin
+                    dprio_write_done = 0;
+                    dprio_next_state = NINE;
+                    avmm_dprio_write = 1'b1;
+                    avmm_dprio_byteen = 2'b11;
+                    if (dsm_k_changed & !dsm_k_done_q)
+                    begin
+                        avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_0;
+                        avmm_dprio_writedata[15:0] = usr_k_value[15:0];
+                    end
+                end
+                NINE: 
+                begin
+                    dprio_write_done = 0;
+                    dprio_next_state = TEN;
+                    avmm_dprio_write = 1'b1;
+                    avmm_dprio_byteen = 2'b11;
+                    if (dsm_k_changed & !dsm_k_done_q)
+                    begin
+                        avmm_dprio_address = DSM_K_FRACTIONAL_DIVISION_ADDR_1;
+                        avmm_dprio_writedata[15:0] = usr_k_value[31:16];
+                    end
+                end
+                TEN:
+                begin
+                    dprio_write_done = 0;
+                    dprio_next_state = ONE;
+                    avmm_dprio_write = 1'b1;
+                    avmm_dprio_byteen = 2'b11;
+                    if (dsm_k_changed & !dsm_k_done_q)
+                    begin
+                        avmm_dprio_address = DSM_K_READY_ADDR;
+                        //already have the readdata for DSM_K_READY_ADDR since we read it
+                        //earlier. Just reuse here 
+                        avmm_dprio_writedata = dprio_temp_m_n_c_readdata_2_q;
+                        avmm_dprio_writedata[DSM_K_READY_BIT_INDEX] = 1'b1;
+                        dsm_k_done_d = 1'b1;
+                    end
+                end
+                DPRIO_DONE:
+                begin
+                    dprio_write_done = 1'b1;
+                    if (dprio_start) dprio_next_state = DPRIO_IDLE;
+                    else dprio_next_state = DPRIO_DONE;
+                end
+                DPRIO_IDLE:
+                begin
+                    if (dprio_start) dprio_next_state = ONE;
+                    else dprio_next_state = DPRIO_IDLE;
+                end 
+                default:    dprio_next_state = 4'bxxxx;
+            endcase
+        end
+
+    end
+
+
+    //assert the waitreq signal according to the state of the slave
+    assign slave_waitrequest = (slave_mode==mode_WR) ? ((locked === 1'b1) ? (((current_state==WAIT_ON_LOCK) & !dprio_write_done) | !dps_done |reset|!dprio_init_done) : 1'b1) : 1'b0;
+        
+    // Read operations
+    always @(*)
+    begin
+    status = 0;
+    if (slave_mode == mode_POLL)
+        //asserting status to 1 if the slave is done.
+       status = (current_state == LOCKED);
+    end
+    //************************************************************//
+    //************************************************************//
+    //******************** READ STATE MACHINE ********************//
+    //************************************************************//
+    //************************************************************//
+    reg  [1:0]      current_read_state;
+    reg  [1:0]      next_read_state;
+    reg  [5:0]      slave_address_int_d;
+    reg  [5:0]      slave_address_int_q;
+    reg             dprio_read_1;
+    reg  [5:0]      dprio_address_1;
+    reg  [1:0]      dprio_byteen_1;
+    reg  [4:0]      usr_cnt_sel_1;
+    localparam READ = 2'b00, READ_WAIT = 2'b01, READ_IDLE = 2'b10, READ_POST_WAIT = 2'b11; 
+    
+    always @(*)
+    begin
+      if(next_read_state == READ_IDLE)
+        begin
+          read_waitrequest <= 1'b0;
+        end
+      else
+        begin
+          read_waitrequest <= 1'b1;
+        end
+    end
+    
+    always @(posedge clk)
+    begin
+        if (reset)
+        begin
+            current_read_state <= READ_IDLE;
+            slave_address_int_q <= 0;
+            slave_readdata_q <= 0;
+        end
+        else
+        begin
+            current_read_state <= next_read_state;
+            slave_address_int_q <= slave_address_int_d;
+            slave_readdata_q <= slave_readdata_d;
+        end
+    end
+    always @(*)
+    begin
+        dprio_read_1 = 0;
+        dprio_address_1 = 0;
+        dprio_byteen_1 = 0;
+        slave_address_int_d = 0;
+        slave_readdata_d = 0;
+        status_read = 0;
+        usr_cnt_sel_1 = 0;
+        case(current_read_state)
+        READ_IDLE:
+        begin
+            slave_address_int_d = 0;
+            next_read_state = READ_IDLE;
+            if ((current_state != WAIT_ON_LOCK) && slave_read)
+            begin
+                slave_address_int_d = slave_address;
+                if ((slave_address >= CNT_BASE) && (slave_address < CNT_BASE+18))
+                begin
+                    next_read_state = READ_WAIT;
+                    dprio_byteen_1 = 2'b11;
+                    dprio_read_1 = 1'b1;
+                    usr_cnt_sel_1 = (slave_address[4:0] - CNT_BASE);
+                    if (fpll_1) dprio_address_1 = C_CNT_0_DIV_ADDR + C_CNT_0_DIV_ADDR_DPRIO_1 - cnt_sel;
+                    else dprio_address_1 = C_CNT_0_DIV_ADDR + cnt_sel;
+                end
+                else
+                begin
+                case (slave_address)
+                MODE_REG:
+                begin
+                    next_read_state = READ_WAIT;
+                    slave_readdata_d = slave_mode;
+                end
+                STATUS_REG:
+                begin
+                    next_read_state = READ_WAIT;
+                    status_read = 1'b1;
+                    slave_readdata_d = status;
+                end
+                N_REG:
+                begin
+                    dprio_byteen_1 = 2'b11;
+                    dprio_read_1 = 1'b1;
+                    dprio_address_1 = N_CNT_DIV_ADDR;
+                    next_read_state = READ_WAIT;
+                end
+                M_REG:
+                begin
+                    dprio_byteen_1 = 2'b11;
+                    dprio_read_1 = 1'b1;
+                    dprio_address_1 = M_CNT_DIV_ADDR;
+                    next_read_state = READ_WAIT;
+                end
+                BWCTRL_REG:
+                begin
+                    dprio_byteen_1 = 2'b11;
+                    dprio_read_1 = 1'b1;
+                    dprio_address_1 = BWCTRL_ADDR;
+                    next_read_state = READ_WAIT;
+                end
+                CP_CURRENT_REG:
+                begin
+                    dprio_byteen_1 = 2'b11;
+                    dprio_read_1 = 1'b1;
+                    dprio_address_1 = CP_CURRENT_ADDR;
+                    next_read_state = READ_WAIT;
+                end
+                VCO_REG:
+                begin
+                    dprio_byteen_1 = 2'b11;
+                    dprio_read_1 = 1'b1;
+                    dprio_address_1 = VCO_ADDR;
+                    next_read_state = READ_WAIT;
+                end
+                ANY_DPRIO:
+                begin
+                    dprio_byteen_1 = 2'b11;
+                    dprio_read_1 = ~slave_writedata[22];
+                    dprio_address_1 = slave_writedata[5:0];
+                    next_read_state = READ_WAIT;
+                end
+                default : next_read_state = READ_IDLE;
+                endcase
+            end
+            end
+            else
+                next_read_state = READ_IDLE;
+        end
+        READ_WAIT:
+        begin
+            next_read_state = READ;
+            slave_address_int_d = slave_address_int_q;
+            case (slave_address_int_q)
+            MODE_REG:
+            begin
+                slave_readdata_d = slave_readdata_q;
+            end
+            STATUS_REG:
+            begin
+                slave_readdata_d = slave_readdata_q;
+            end
+    	    endcase
+        end
+        READ:
+        begin
+            next_read_state = READ_POST_WAIT;
+            slave_address_int_d = slave_address_int_q;
+            slave_readdata_d = dprio_readdata;
+            case (slave_address_int_q)
+            MODE_REG:
+            begin
+                slave_readdata_d = slave_readdata_q;
+            end
+            STATUS_REG:
+            begin
+                slave_readdata_d = slave_readdata_q;
+            end
+            BWCTRL_REG:
+            begin
+                slave_readdata_d = dprio_readdata[3:0];
+            end
+            CP_CURRENT_REG:
+            begin
+                slave_readdata_d = dprio_readdata[2:0];
+            end
+            VCO_REG:
+            begin
+                slave_readdata_d = dprio_readdata[8];
+            end
+            ANY_DPRIO:
+            begin
+                slave_readdata_d = dprio_readdata;
+            end
+    	    endcase
+        end
+        READ_POST_WAIT:
+        begin
+            next_read_state = READ_IDLE;
+        end
+        default: next_read_state = 2'bxx;
+        endcase
+     end
+
+
+    dyn_phase_shift dyn_phase_shift_inst (
+        .clk(clk), 
+        .reset(reset),
+        .phase_done(phase_done),
+        .pll_start_valid(pll_start_valid),
+        .dps_changed(dps_changed),
+        .dps_changed_valid(dps_changed_valid),
+        .dprio_write_done(dprio_write_done),
+        .usr_num_shifts(usr_num_shifts),
+        .usr_cnt_sel(usr_cnt_sel|usr_cnt_sel_1),
+        .usr_up_dn(usr_up_dn),
+        .locked(locked),
+        .dps_done(dps_done),
+        .phase_en(phase_en),
+        .up_dn(up_dn),
+        .cnt_sel(cnt_sel));
+    defparam dyn_phase_shift_inst.device_family = device_family;
+
+    assign dprio_clk = clk;
+    self_reset self_reset_inst (mgmt_reset, clk, reset, dprio_init_reset);
+    
+    dprio_mux dprio_mux_inst (
+    .init_dprio_address(init_dprio_address),
+    .init_dprio_read(init_dprio_read),
+    .init_dprio_byteen(init_dprio_byteen),
+    .init_dprio_write(init_dprio_write),
+    .init_dprio_writedata(init_dprio_writedata),
+
+
+    .init_atpgmode(init_atpgmode),
+    .init_mdio_dis(init_mdio_dis),
+    .init_scanen(init_scanen),
+    .init_ser_shift_load(init_ser_shift_load),
+    .dprio_init_done(dprio_init_done),
+
+    // Inputs from avmm master
+    .avmm_dprio_address(avmm_dprio_address | dprio_address_1),
+    .avmm_dprio_read(avmm_dprio_read | dprio_read_1),
+    .avmm_dprio_byteen(avmm_dprio_byteen | dprio_byteen_1),
+    .avmm_dprio_write(avmm_dprio_write),
+    .avmm_dprio_writedata(avmm_dprio_writedata),
+
+    .avmm_atpgmode(avmm_atpgmode),
+    .avmm_mdio_dis(avmm_mdio_dis),
+    .avmm_scanen(avmm_scanen),
+
+    // Outputs to fpll
+    .dprio_address(dprio_address),
+    .dprio_read(dprio_read),
+    .dprio_byteen(dprio_byteen),
+    .dprio_write(dprio_write),
+    .dprio_writedata(dprio_writedata),
+
+    .atpgmode(dprio_atpgmode),
+    .mdio_dis(dprio_mdio_dis),
+    .scanen(dprio_scanen),
+    .ser_shift_load(dprio_ser_shift_load)
+    );
+
+
+    fpll_dprio_init fpll_dprio_init_inst (
+    .clk(clk),
+    .reset_n(~reset),
+    .locked(locked),
+
+    //outputs
+    .dprio_address(init_dprio_address),
+    .dprio_read(init_dprio_read),
+    .dprio_byteen(init_dprio_byteen),
+    .dprio_write(init_dprio_write),
+    .dprio_writedata(init_dprio_writedata),
+
+    .atpgmode(init_atpgmode),
+    .mdio_dis(init_mdio_dis),
+    .scanen(init_scanen),
+    .ser_shift_load(init_ser_shift_load),
+    .dprio_init_done(dprio_init_done));
+
+    //address luts, to be reconfigged by the Fitter
+    //FPLL_1 or 0 address lut
+    generic_lcell_comb lcell_fpll_0_1 (
+		.dataa(1'b0),
+        .combout (fpll_1));
+    defparam lcell_fpll_0_1.lut_mask = 64'hAAAAAAAAAAAAAAAA;
+	 defparam lcell_fpll_0_1.dont_touch = "on";
+	 defparam lcell_fpll_0_1.family = device_family;
+
+
+    wire dprio_read_combout;
+     generic_lcell_comb lcell_dprio_read (
+		.dataa(fpll_1),
+        .datab(dprio_read),
+        .datac(1'b0),
+        .datad(1'b0),
+        .datae(1'b0),
+        .dataf(1'b0),
+      .combout (dprio_read_combout));
+    defparam lcell_dprio_read.lut_mask = 64'hCCCCCCCCCCCCCCCC;
+	 defparam lcell_dprio_read.dont_touch = "on";
+	 defparam lcell_dprio_read.family = device_family;
+
+   
+    
+
+
+    //assign reconfig_to_pll signals
+    assign reconfig_to_pll[0] = dprio_clk;
+    assign reconfig_to_pll[1] = ~dprio_init_reset;
+    assign reconfig_to_pll[2] = dprio_write;
+    assign reconfig_to_pll[3] = dprio_read_combout;
+    assign reconfig_to_pll[9:4] = dprio_address;
+    assign reconfig_to_pll[25:10] = dprio_writedata;
+    assign reconfig_to_pll[27:26] = dprio_byteen;
+    assign reconfig_to_pll[28] = dprio_ser_shift_load;
+    assign reconfig_to_pll[29] = dprio_mdio_dis;
+    assign reconfig_to_pll[30] = phase_en;
+    assign reconfig_to_pll[31] = up_dn;
+    assign reconfig_to_pll[36:32] = cnt_sel;
+    assign reconfig_to_pll[37] = dprio_scanen;
+    assign reconfig_to_pll[38] = dprio_atpgmode;
+    //assign reconfig_to_pll[40:37] = clken;
+    assign reconfig_to_pll[63:39] = 0;
+
+    //assign reconfig_from_pll signals
+    assign dprio_readdata = reconfig_from_pll [15:0]; 
+    assign locked_orig    = reconfig_from_pll [16];
+    assign phase_done     = reconfig_from_pll [17];
+
+endmodule
+module self_reset (input wire mgmt_reset, input wire clk, output wire reset, output wire init_reset);
+
+    localparam RESET_COUNTER_VALUE = 3'd2;
+    localparam INITIAL_WAIT_VALUE = 9'd340;
+    reg [9:0]counter;
+    reg local_reset;
+    reg usr_mode_init_wait;
+    initial 
+    begin
+        local_reset = 1'b1;
+        counter = 0;
+        usr_mode_init_wait = 0;
+    end
+
+    always @(posedge clk)
+    begin
+        if (mgmt_reset)
+        begin
+            counter <= 0;
+        end
+        else
+        begin
+            if (!usr_mode_init_wait)
+            begin
+                if (counter == INITIAL_WAIT_VALUE)
+                begin
+                    local_reset <= 0;
+                    usr_mode_init_wait <= 1'b1;
+                    counter <= 0;
+                end
+                else 
+                begin
+                counter <= counter + 1'b1;
+                end
+            end
+            else
+            begin
+                if (counter == RESET_COUNTER_VALUE)
+                    local_reset <= 0;
+                else 
+                    counter <= counter + 1'b1;
+            end
+        end
+    end
+    assign reset = mgmt_reset | local_reset;
+    assign init_reset = local_reset;
+endmodule
+
+module dprio_mux (
+    // Inputs from init block
+    input       [ 5:0]  init_dprio_address,
+    input               init_dprio_read,
+    input       [ 1:0]  init_dprio_byteen,
+    input               init_dprio_write,
+    input       [15:0]  init_dprio_writedata,
+
+    input               init_atpgmode,
+    input               init_mdio_dis,
+    input               init_scanen,
+    input               init_ser_shift_load,
+    input               dprio_init_done,
+
+    // Inputs from avmm master
+    input       [ 5:0]  avmm_dprio_address,
+    input               avmm_dprio_read,
+    input       [ 1:0]  avmm_dprio_byteen,
+    input               avmm_dprio_write,
+    input       [15:0]  avmm_dprio_writedata,
+
+    input               avmm_atpgmode,
+    input               avmm_mdio_dis,
+    input               avmm_scanen,
+    input               avmm_ser_shift_load,
+
+    // Outputs to fpll
+    output      [ 5:0]  dprio_address,
+    output              dprio_read,
+    output      [ 1:0]  dprio_byteen,
+    output              dprio_write,
+    output      [15:0]  dprio_writedata,
+
+    output              atpgmode,
+    output              mdio_dis,
+    output              scanen,
+    output              ser_shift_load
+);
+
+    assign  dprio_address   = dprio_init_done ? avmm_dprio_address    : init_dprio_address;
+    assign  dprio_read      = dprio_init_done ? avmm_dprio_read       : init_dprio_read;
+    assign  dprio_byteen    = dprio_init_done ? avmm_dprio_byteen     : init_dprio_byteen;
+    assign  dprio_write     = dprio_init_done ? avmm_dprio_write      : init_dprio_write;
+    assign  dprio_writedata = dprio_init_done ? avmm_dprio_writedata  : init_dprio_writedata;
+
+    assign  atpgmode        = init_atpgmode;
+    assign  scanen          = init_scanen;
+    assign  mdio_dis        = init_mdio_dis;
+    assign  ser_shift_load  = init_ser_shift_load ;
+endmodule
+module fpll_dprio_init (
+    input               clk,
+    input               reset_n,
+    input               locked,
+
+    output      [ 5:0]  dprio_address,
+    output              dprio_read,
+    output      [ 1:0]  dprio_byteen,
+    output              dprio_write,
+    output      [15:0]  dprio_writedata,
+
+    output  reg         atpgmode,
+    output  reg         mdio_dis,
+    output  reg         scanen,
+    output  reg         ser_shift_load,
+    output  reg         dprio_init_done
+);
+
+    reg [1:0] rst_n = 2'b00;
+    reg [6:0] count = 7'd0;
+    reg init_done_forever;
+
+    // Internal versions of control signals
+    wire  int_mdio_dis;
+    wire  int_ser_shift_load;
+    wire  int_dprio_init_done;
+    wire  int_atpgmode/*synthesis keep*/;
+    wire  int_scanen/*synthesis keep*/;
+
+
+    assign  dprio_address   = count[6] ? 5'b0 : count[5:0] ;
+    assign  dprio_byteen    = 2'b11;      // always enabled
+    assign  dprio_write     = ~count[6] & reset_n ;  // write for first 64 cycles
+    assign  dprio_read      = 1'b0;
+    assign  dprio_writedata = 16'd0;
+
+    assign  int_ser_shift_load  = count[6] ? |count[2:1]  : 1'b1; 
+    assign  int_mdio_dis        = count[6] ? ~count[2]    : 1'b1;
+    assign  int_dprio_init_done = ~init_done_forever ? (count[6] ? &count[2:0]  : 1'b0)
+                                                    : 1'b1;
+    assign  int_atpgmode        = 0;
+    assign  int_scanen          = 0;
+
+    initial begin
+        count             = 7'd0;
+        init_done_forever = 0;
+        mdio_dis          = 1'b1;
+        ser_shift_load    = 1'b1;
+        dprio_init_done   = 1'b0;
+        scanen            = 1'b0;
+        atpgmode          = 1'b0;
+    end
+
+    // reset synch.
+    always @(posedge clk or negedge reset_n)
+        if(!reset_n)  rst_n <= 2'b00;
+        else          rst_n <= {rst_n[0],1'b1};
+
+    // counter
+    always @(posedge clk)
+    begin
+        if (!rst_n[1])
+            init_done_forever <= 1'b0;
+        else
+        begin
+        if (count[6] && &count[1:0])
+            init_done_forever <= 1'b1;
+        end
+    end
+    always @(posedge clk or negedge rst_n[1])
+    begin
+        if(!rst_n[1])
+        begin
+            count <= 7'd0;
+        end
+        else if(~int_dprio_init_done) 
+        begin
+            count <= count + 7'd1;
+        end
+        else
+        begin
+            count <= count;
+        end
+    end
+
+    // outputs
+    always @(posedge clk) begin
+        mdio_dis        <= int_mdio_dis;
+        ser_shift_load  <= int_ser_shift_load;
+        dprio_init_done <= int_dprio_init_done;
+        atpgmode        <= int_atpgmode;
+        scanen          <= int_scanen;
+    end
+
+endmodule
+module dyn_phase_shift
+#(
+    parameter device_family       = "Stratix V"
+) ( 
+
+    input   wire        clk,
+    input   wire        reset,
+    input   wire        phase_done,
+    input   wire        pll_start_valid,
+    input   wire        dps_changed,
+    input   wire        dprio_write_done,
+    input   wire [15:0] usr_num_shifts,
+    input   wire [4:0]  usr_cnt_sel,
+    input   wire        usr_up_dn,
+    input   wire        locked,
+
+    //output
+    output  wire        dps_done,
+    output  reg         phase_en,
+    output  wire        up_dn,
+    output  wire        dps_changed_valid,
+    output  wire [4:0]  cnt_sel);
+    
+	
+
+    reg        first_phase_shift_d;
+    reg        first_phase_shift_q;
+    reg [15:0] phase_en_counter;
+    reg [3:0]       dps_current_state;
+    reg [3:0]       dps_next_state;
+    localparam DPS_START = 4'd0, DPS_WAIT_PHASE_DONE = 4'd1, DPS_DONE = 4'd2, DPS_WAIT_PHASE_EN = 4'd3, DPS_WAIT_DPRIO_WRITING = 4'd4, DPS_CHANGED = 4'd5; 
+    localparam PHASE_EN_WAIT_COUNTER = 5'd1;
+
+    reg [15:0] shifts_done_counter;
+    reg        phase_done_final;
+	 wire 		gnd /*synthesis keep*/;
+	 
+    //fsm
+    //always block controlling the state regs
+    always @(posedge clk)
+    begin
+        if (reset)
+        begin
+            dps_current_state <= DPS_DONE;
+        end
+        else
+        begin
+            dps_current_state <= dps_next_state;
+        end
+    end
+    //the combinational part. assigning the next state
+    //this turns on the phase_done_final signal when phase_done does this:
+    //_____         ______
+    //      |______|
+    always @(*)
+    begin
+        phase_done_final = 0;
+        first_phase_shift_d = 0;
+        phase_en = 0;
+        dps_next_state = DPS_DONE;
+        case (dps_current_state)
+            DPS_START:
+            begin
+                phase_en = 1'b1;
+                dps_next_state = DPS_WAIT_PHASE_EN;
+            end
+            DPS_WAIT_PHASE_EN:
+            begin
+                phase_en = 1'b1;
+                if (first_phase_shift_q)
+                begin
+                    first_phase_shift_d = 1'b1;
+                    dps_next_state = DPS_WAIT_PHASE_EN;
+                end
+                else
+                begin
+                    if (phase_en_counter == PHASE_EN_WAIT_COUNTER)
+                        dps_next_state = DPS_WAIT_PHASE_DONE;
+                    else dps_next_state = DPS_WAIT_PHASE_EN;
+                end
+            end
+            DPS_WAIT_PHASE_DONE:
+            begin
+                if (!phase_done | !locked)
+                begin
+                    dps_next_state = DPS_WAIT_PHASE_DONE;
+                end
+                else
+                begin
+                    if ((usr_num_shifts != shifts_done_counter) & (usr_num_shifts != 0))
+                    begin
+                        dps_next_state = DPS_START;
+                        phase_done_final = 1'b1;
+                    end
+                    else
+                    begin
+                        dps_next_state = DPS_DONE;
+                    end
+
+                end
+            end
+            DPS_DONE:
+            begin
+                phase_done_final = 0;            
+                if (dps_changed) 
+                    dps_next_state = DPS_CHANGED;
+                else dps_next_state = DPS_DONE;
+
+            end
+			DPS_CHANGED:
+            begin
+                if (pll_start_valid)
+                    dps_next_state = DPS_WAIT_DPRIO_WRITING;
+                else
+                    dps_next_state = DPS_CHANGED;
+            end
+            DPS_WAIT_DPRIO_WRITING:
+            begin
+                if (dprio_write_done)
+                    dps_next_state = DPS_START;
+                else
+                    dps_next_state = DPS_WAIT_DPRIO_WRITING;
+            end
+
+            default: dps_next_state = 4'bxxxx;
+        endcase
+    
+    
+    end
+
+    always @(posedge clk)
+    begin
+
+        
+        if (dps_current_state == DPS_WAIT_PHASE_DONE)
+            phase_en_counter <= 0;
+        else if (dps_current_state == DPS_WAIT_PHASE_EN)
+            phase_en_counter <= phase_en_counter + 1'b1;
+
+        if (reset)
+        begin
+            phase_en_counter <= 0;
+            shifts_done_counter <= 1'b1;
+            first_phase_shift_q <= 1;
+        end
+        else
+        begin
+            if (first_phase_shift_d)
+                first_phase_shift_q <= 0;
+            if (dps_done)
+            begin
+                shifts_done_counter <= 1'b1;
+            end
+            else
+            begin
+                if (phase_done_final & (dps_next_state!= DPS_DONE))
+                    shifts_done_counter <= shifts_done_counter + 1'b1;
+                else
+                    shifts_done_counter <= shifts_done_counter;
+            end
+        end
+    end
+
+    assign dps_changed_valid = (dps_current_state == DPS_CHANGED);
+    assign dps_done =(dps_current_state == DPS_DONE) | (dps_current_state == DPS_CHANGED);
+    assign up_dn = usr_up_dn;
+	 assign gnd = 1'b0;
+	
+    //cnt select luts (5)
+    generic_lcell_comb lcell_cnt_sel_0 (
+        .dataa(usr_cnt_sel[0]),
+        .datab(usr_cnt_sel[1]),
+        .datac(usr_cnt_sel[2]),
+        .datad(usr_cnt_sel[3]),
+        .datae(usr_cnt_sel[4]),
+        .dataf(gnd),
+        .combout (cnt_sel[0]));
+    defparam lcell_cnt_sel_0.lut_mask = 64'hAAAAAAAAAAAAAAAA;
+    defparam lcell_cnt_sel_0.dont_touch = "on";
+    defparam lcell_cnt_sel_0.family = device_family;
+    generic_lcell_comb lcell_cnt_sel_1 (
+        .dataa(usr_cnt_sel[0]),
+        .datab(usr_cnt_sel[1]),
+        .datac(usr_cnt_sel[2]),
+        .datad(usr_cnt_sel[3]),
+        .datae(usr_cnt_sel[4]),
+        .dataf(gnd),
+        .combout (cnt_sel[1]));
+    defparam lcell_cnt_sel_1.lut_mask = 64'hCCCCCCCCCCCCCCCC;
+    defparam lcell_cnt_sel_1.dont_touch = "on";
+    defparam lcell_cnt_sel_1.family = device_family;
+    generic_lcell_comb lcell_cnt_sel_2 (
+        .dataa(usr_cnt_sel[0]),
+        .datab(usr_cnt_sel[1]),
+        .datac(usr_cnt_sel[2]),
+        .datad(usr_cnt_sel[3]),
+        .datae(usr_cnt_sel[4]),
+        .dataf(gnd),
+        .combout (cnt_sel[2]));
+    defparam lcell_cnt_sel_2.lut_mask = 64'hF0F0F0F0F0F0F0F0;
+    defparam lcell_cnt_sel_2.dont_touch = "on";
+    defparam lcell_cnt_sel_2.family = device_family;
+    generic_lcell_comb lcell_cnt_sel_3 (
+        .dataa(usr_cnt_sel[0]),
+        .datab(usr_cnt_sel[1]),
+        .datac(usr_cnt_sel[2]),
+        .datad(usr_cnt_sel[3]),
+        .datae(usr_cnt_sel[4]),
+        .dataf(gnd),
+        .combout (cnt_sel[3]));
+    defparam lcell_cnt_sel_3.lut_mask = 64'hFF00FF00FF00FF00;
+    defparam lcell_cnt_sel_3.dont_touch = "on";
+    defparam lcell_cnt_sel_3.family = device_family;
+    generic_lcell_comb lcell_cnt_sel_4 (
+        .dataa(usr_cnt_sel[0]),
+        .datab(usr_cnt_sel[1]),
+        .datac(usr_cnt_sel[2]),
+        .datad(usr_cnt_sel[3]),
+        .datae(usr_cnt_sel[4]),
+        .dataf(gnd),
+        .combout (cnt_sel[4]));
+    defparam lcell_cnt_sel_4.lut_mask = 64'hFFFF0000FFFF0000;
+    defparam lcell_cnt_sel_4.dont_touch = "on";
+    defparam lcell_cnt_sel_4.family = device_family;
+   
+    
+endmodule
+
+module generic_lcell_comb
+#(
+    //parameter
+    parameter family             = "Stratix V",
+    parameter lut_mask           = 64'hAAAAAAAAAAAAAAAA,
+    parameter dont_touch         = "on"
+) ( 
+
+    input    dataa,
+    input    datab,
+    input    datac,
+    input    datad,
+    input    datae,
+    input    dataf,
+
+    output   combout
+);
+
+    generate
+        if (family == "Stratix V")
+        begin
+            stratixv_lcell_comb lcell_inst (
+                    .dataa(dataa),
+                    .datab(datab),
+                    .datac(datac),
+                    .datad(datad),
+                    .datae(datae),
+                    .dataf(dataf),
+                    .combout (combout));
+            defparam lcell_inst.lut_mask = lut_mask;
+            defparam lcell_inst.dont_touch = dont_touch;
+        end
+        else if (family == "Arria V")
+        begin
+            arriav_lcell_comb lcell_inst (
+                    .dataa(dataa),
+                    .datab(datab),
+                    .datac(datac),
+                    .datad(datad),
+                    .datae(datae),
+                    .dataf(dataf),
+                    .combout (combout));
+            defparam lcell_inst.lut_mask = lut_mask;
+            defparam lcell_inst.dont_touch = dont_touch;
+        end
+        else if (family == "Arria V GZ")
+        begin
+            arriavgz_lcell_comb lcell_inst (
+                    .dataa(dataa),
+                    .datab(datab),
+                    .datac(datac),
+                    .datad(datad),
+                    .datae(datae),
+                    .dataf(dataf),
+                    .combout (combout));
+            defparam lcell_inst.lut_mask = lut_mask;
+            defparam lcell_inst.dont_touch = dont_touch;
+        end
+        else if (family == "Cyclone V")
+        begin
+            cyclonev_lcell_comb lcell_inst (
+                    .dataa(dataa),
+                    .datab(datab),
+                    .datac(datac),
+                    .datad(datad),
+                    .datae(datae),
+                    .dataf(dataf),
+                    .combout (combout));
+            defparam lcell_inst.lut_mask = lut_mask;
+            defparam lcell_inst.dont_touch = dont_touch;
+        end
+        endgenerate
+endmodule
diff --git a/sys/pll_hdmi_cfg/altera_pll_reconfig_top.v b/sys/pll_hdmi_cfg/altera_pll_reconfig_top.v
new file mode 100644
index 0000000..c1bfa8b
--- /dev/null
+++ b/sys/pll_hdmi_cfg/altera_pll_reconfig_top.v
@@ -0,0 +1,428 @@
+// (C) 2001-2017 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel MegaCore Function License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1ps/1ps
+
+module altera_pll_reconfig_top
+#(
+    parameter   reconf_width            = 64,
+    parameter   device_family           = "Stratix V",
+    parameter   RECONFIG_ADDR_WIDTH     = 6,
+    parameter   RECONFIG_DATA_WIDTH     = 32,
+    
+	parameter   ROM_ADDR_WIDTH          = 9,
+    parameter   ROM_DATA_WIDTH          = 32,
+	parameter	ROM_NUM_WORDS           = 512,
+
+    parameter   ENABLE_MIF              = 0,    
+    parameter   MIF_FILE_NAME           = "",
+	
+	parameter 	ENABLE_BYTEENABLE		= 0,
+	parameter	BYTEENABLE_WIDTH		= 4,
+    parameter   WAIT_FOR_LOCK           = 1
+) ( 
+
+    //input
+    input   wire    mgmt_clk,
+    input   wire    mgmt_reset,
+
+
+    //conduits
+    output  wire [reconf_width-1:0] reconfig_to_pll,
+    input  wire [reconf_width-1:0] reconfig_from_pll,
+
+    // user data (avalon-MM slave interface)
+    output  wire [RECONFIG_DATA_WIDTH-1:0] mgmt_readdata,
+    output  wire        mgmt_waitrequest,
+    input   wire [RECONFIG_ADDR_WIDTH-1:0]  mgmt_address,
+    input   wire        mgmt_read,
+    input   wire        mgmt_write,
+    input   wire [RECONFIG_DATA_WIDTH-1:0] mgmt_writedata,
+	
+	//conditional input 
+	input 	wire [BYTEENABLE_WIDTH-1:0] mgmt_byteenable
+);
+
+localparam  NM28_START_REG 		= 6'b000010;
+localparam  NM20_START_REG 		= 9'b000000000;
+localparam 	NM20_MIFSTART_ADDR	= 9'b000010000;
+
+localparam MIF_STATE_DONE = 2'b00;
+localparam MIF_STATE_START = 2'b01;
+localparam MIF_STATE_BUSY = 2'b10;
+
+wire mgmt_byteenable_write;
+assign mgmt_byteenable_write = (ENABLE_BYTEENABLE == 1) ? 
+										((mgmt_byteenable == {BYTEENABLE_WIDTH{1'b1}}) ? mgmt_write : 1'b0) : 
+										mgmt_write;
+										
+generate
+if (device_family == "Arria 10")
+begin:nm20_reconfig
+	if(ENABLE_MIF == 1)
+	begin:mif_reconfig_20nm // Generate Reconfig with MIF
+	
+		// MIF-related regs/wires
+        reg [RECONFIG_ADDR_WIDTH-1:0]   reconfig_mgmt_addr; 
+        reg                             reconfig_mgmt_read;
+        reg                             reconfig_mgmt_write;
+        reg [RECONFIG_DATA_WIDTH-1:0]   reconfig_mgmt_writedata;
+        wire                            reconfig_mgmt_waitrequest;
+        wire [RECONFIG_DATA_WIDTH-1:0]   reconfig_mgmt_readdata;
+
+        wire [RECONFIG_ADDR_WIDTH-1:0]   mif2reconfig_addr;
+        wire							 mif_busy;
+        wire                             mif2reconfig_read;
+        wire                             mif2reconfig_write;
+        wire [RECONFIG_DATA_WIDTH-1:0]   mif2reconfig_writedata;
+        wire [ROM_ADDR_WIDTH-1:0]        mif_base_addr;
+        reg mif_select;
+		//wire 							mif_user_start; // start signal provided by user to start mif
+        //reg user_start;
+
+		reg [1:0] mif_curstate;
+		reg [1:0] mif_nextstate;
+
+        wire mif_start; //start signal to mif reader
+
+        assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif_busy;// | user_start;
+        // Don't output readdata if MIF streaming is taking place
+        assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
+
+		//user must lower this by the time mif streaming is done - suggest to lower after 1 cycle
+		assign mif_start = mgmt_byteenable_write & (mgmt_address == NM20_MIFSTART_ADDR);
+		
+		//mif base addr is initially specified by the user
+		assign mif_base_addr = mgmt_writedata[ROM_ADDR_WIDTH-1:0];
+		
+		//MIF statemachine
+		always @(posedge mgmt_clk)
+		begin
+			if(mgmt_reset)
+				mif_curstate <= MIF_STATE_DONE;
+			else
+				mif_curstate <= mif_nextstate;
+		end
+		
+		always @(*)
+		begin
+			case (mif_curstate)
+				MIF_STATE_DONE:
+				begin
+					if(mif_start)
+						mif_nextstate <= MIF_STATE_START;
+					else
+						mif_nextstate <= MIF_STATE_DONE;
+				end
+				MIF_STATE_START:
+				begin
+					mif_nextstate <= MIF_STATE_BUSY;
+				end				
+				MIF_STATE_BUSY:
+				begin
+					if(mif_busy)
+						mif_nextstate <= MIF_STATE_BUSY;
+					else
+						mif_nextstate <= MIF_STATE_DONE;
+				end
+			endcase
+		end
+		
+		//Mif muxes
+        always @(*)
+        begin
+            if (mgmt_reset)
+            begin
+                reconfig_mgmt_addr      <= 0;
+                reconfig_mgmt_read      <= 0;
+                reconfig_mgmt_write     <= 0;
+                reconfig_mgmt_writedata <= 0;
+                //user_start              <= 0;
+            end
+            else
+            begin
+                reconfig_mgmt_addr      <= (mif_select) ? mif2reconfig_addr : mgmt_address;
+                reconfig_mgmt_read      <= (mif_select) ? mif2reconfig_read : mgmt_read;
+                reconfig_mgmt_write     <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
+                reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
+                //user_start              <= (mgmt_address == NM20_START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0;
+            end
+        end
+
+        always @(*)
+        begin
+            if (mgmt_reset)
+            begin
+                mif_select <= 0;
+            end
+            else 
+            begin
+                mif_select <= (mif_start || mif_busy) ? 1'b1 : 1'b0;
+            end
+        end
+	
+        twentynm_pll_reconfig_mif_reader  
+        #(
+            .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
+            .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
+            .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
+            .ROM_DATA_WIDTH(ROM_DATA_WIDTH),
+            .ROM_NUM_WORDS(ROM_NUM_WORDS),
+            .DEVICE_FAMILY(device_family),
+            .ENABLE_MIF(ENABLE_MIF),
+            .MIF_FILE_NAME(MIF_FILE_NAME)
+        ) twentynm_pll_reconfig_mif_reader_inst0 (
+            .mif_clk(mgmt_clk),
+            .mif_rst(mgmt_reset),
+            
+            //Altera_PLL Reconfig interface
+            //inputs
+            .reconfig_waitrequest(reconfig_mgmt_waitrequest),
+			//.reconfig_read_data(reconfig_mgmt_readdata),
+            //outputs
+            .reconfig_write_data(mif2reconfig_writedata),
+            .reconfig_addr(mif2reconfig_addr),
+            .reconfig_write(mif2reconfig_write),
+            .reconfig_read(mif2reconfig_read),
+
+            //MIF Ctrl Interface
+            //inputs
+            .mif_base_addr(mif_base_addr),
+            .mif_start(mif_start),
+            //outputs
+            .mif_busy(mif_busy)
+        );
+		
+        // ------ END MIF-RELATED MANAGEMENT ------	
+		
+		twentynm_iopll_reconfig_core 
+        #(
+            .WAIT_FOR_LOCK(WAIT_FOR_LOCK)
+        ) twentynm_iopll_reconfig_core_inst	(
+			// Inputs
+			.mgmt_clk(mgmt_clk),
+			.mgmt_rst_n(~mgmt_reset),
+			.mgmt_read(reconfig_mgmt_read),
+			.mgmt_write(reconfig_mgmt_write),
+			.mgmt_address(reconfig_mgmt_addr),
+			.mgmt_writedata(reconfig_mgmt_writedata),
+
+			// Outputs
+			.mgmt_readdata(reconfig_mgmt_readdata),
+			.mgmt_waitrequest(reconfig_mgmt_waitrequest),
+			
+			// PLL Conduits
+			.reconfig_to_pll(reconfig_to_pll),
+			.reconfig_from_pll(reconfig_from_pll)
+		);
+		
+	end // End generate reconfig with MIF
+	else 
+	begin:reconfig_core_20nm
+		twentynm_iopll_reconfig_core 
+        #(
+            .WAIT_FOR_LOCK(WAIT_FOR_LOCK)
+        ) twentynm_iopll_reconfig_core_inst	(
+			// Inputs
+			.mgmt_clk(mgmt_clk),
+			.mgmt_rst_n(~mgmt_reset),
+			.mgmt_read(mgmt_read),
+			.mgmt_write(mgmt_byteenable_write),
+			.mgmt_address(mgmt_address),
+			.mgmt_writedata(mgmt_writedata),
+
+			// Outputs
+			.mgmt_readdata(mgmt_readdata),
+			.mgmt_waitrequest(mgmt_waitrequest),
+			
+			// PLL Conduits
+			.reconfig_to_pll(reconfig_to_pll),
+			.reconfig_from_pll(reconfig_from_pll)
+		);
+	end
+end // 20nm reconfig
+else
+begin:NM28_reconfig
+    if (ENABLE_MIF == 1)
+    begin:mif_reconfig // Generate Reconfig with MIF
+
+        // MIF-related regs/wires
+        reg [RECONFIG_ADDR_WIDTH-1:0]   reconfig_mgmt_addr;
+        reg                             reconfig_mgmt_read;
+        reg                             reconfig_mgmt_write;
+        reg [RECONFIG_DATA_WIDTH-1:0]   reconfig_mgmt_writedata;
+        wire                            reconfig_mgmt_waitrequest;
+        wire [RECONFIG_DATA_WIDTH-1:0]   reconfig_mgmt_readdata;
+
+        wire [RECONFIG_ADDR_WIDTH-1:0]   mif2reconfig_addr;
+        wire										mif2reconfig_busy;
+        wire                             mif2reconfig_read;
+        wire                             mif2reconfig_write;
+        wire [RECONFIG_DATA_WIDTH-1:0]   mif2reconfig_writedata;
+        wire  [ROM_ADDR_WIDTH-1:0]        mif_base_addr;
+        reg mif_select;
+        reg user_start;
+
+        wire reconfig2mif_start_out;
+
+        assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start;
+        // Don't output readdata if MIF streaming is taking place
+        assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
+
+        always @(posedge mgmt_clk)
+        begin
+            if (mgmt_reset)
+            begin
+                reconfig_mgmt_addr      <= 0;
+                reconfig_mgmt_read      <= 0;
+                reconfig_mgmt_write     <= 0;
+                reconfig_mgmt_writedata <= 0;
+                user_start              <= 0;
+            end
+            else
+            begin
+                reconfig_mgmt_addr      <= (mif_select) ? mif2reconfig_addr : mgmt_address;
+                reconfig_mgmt_read      <= (mif_select) ? mif2reconfig_read : mgmt_read;
+                reconfig_mgmt_write     <= (mif_select) ? mif2reconfig_write : mgmt_byteenable_write;
+                reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
+                user_start              <= (mgmt_address == NM28_START_REG && mgmt_byteenable_write == 1'b1) ? 1'b1 : 1'b0;
+            end
+        end
+
+        always @(*)
+        begin
+            if (mgmt_reset)
+            begin
+                mif_select <= 0;
+            end
+            else 
+            begin
+                mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0;
+            end
+        end
+
+        altera_pll_reconfig_mif_reader 
+        #(
+            .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
+            .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
+            .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
+            .ROM_DATA_WIDTH(ROM_DATA_WIDTH),
+            .ROM_NUM_WORDS(ROM_NUM_WORDS),
+            .DEVICE_FAMILY(device_family),
+            .ENABLE_MIF(ENABLE_MIF),
+            .MIF_FILE_NAME(MIF_FILE_NAME)
+        ) altera_pll_reconfig_mif_reader_inst0 (
+            .mif_clk(mgmt_clk),
+            .mif_rst(mgmt_reset),
+            
+            //Altera_PLL Reconfig interface
+            //inputs
+            .reconfig_busy(reconfig_mgmt_waitrequest),
+            .reconfig_read_data(reconfig_mgmt_readdata),
+            //outputs
+            .reconfig_write_data(mif2reconfig_writedata),
+            .reconfig_addr(mif2reconfig_addr),
+            .reconfig_write(mif2reconfig_write),
+            .reconfig_read(mif2reconfig_read),
+
+            //MIF Ctrl Interface
+            //inputs
+            .mif_base_addr(mif_base_addr),
+            .mif_start(reconfig2mif_start_out),
+            //outputs
+            .mif_busy(mif2reconfig_busy)
+        );
+
+        // ------ END MIF-RELATED MANAGEMENT ------
+
+
+        altera_pll_reconfig_core
+        #(
+            .reconf_width(reconf_width),
+            .device_family(device_family),
+            .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
+            .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
+            .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
+            .ROM_DATA_WIDTH(ROM_DATA_WIDTH),
+            .ROM_NUM_WORDS(ROM_NUM_WORDS)
+        ) altera_pll_reconfig_core_inst0 (
+            //inputs
+            .mgmt_clk(mgmt_clk),
+            .mgmt_reset(mgmt_reset),
+
+            //PLL interface conduits
+            .reconfig_to_pll(reconfig_to_pll),
+            .reconfig_from_pll(reconfig_from_pll),
+
+            //User data outputs
+            .mgmt_readdata(reconfig_mgmt_readdata),
+            .mgmt_waitrequest(reconfig_mgmt_waitrequest),
+            
+            //User data inputs
+            .mgmt_address(reconfig_mgmt_addr),
+            .mgmt_read(reconfig_mgmt_read),
+            .mgmt_write(reconfig_mgmt_write),
+            .mgmt_writedata(reconfig_mgmt_writedata),
+
+            // other
+            .mif_start_out(reconfig2mif_start_out),
+            .mif_base_addr(mif_base_addr)
+        );
+
+    end // End generate reconfig with MIF
+    else
+    begin:reconfig_core // Generate Reconfig core only
+
+        wire reconfig2mif_start_out;
+        wire  [ROM_ADDR_WIDTH-1:0]        mif_base_addr;
+
+        altera_pll_reconfig_core
+        #(
+            .reconf_width(reconf_width),
+            .device_family(device_family),
+            .RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
+            .RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
+            .ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
+            .ROM_DATA_WIDTH(ROM_DATA_WIDTH),
+            .ROM_NUM_WORDS(ROM_NUM_WORDS)
+        ) altera_pll_reconfig_core_inst0 (
+            //inputs
+            .mgmt_clk(mgmt_clk),
+            .mgmt_reset(mgmt_reset),
+
+            //PLL interface conduits
+            .reconfig_to_pll(reconfig_to_pll),
+            .reconfig_from_pll(reconfig_from_pll),
+
+            //User data outputs
+            .mgmt_readdata(mgmt_readdata),
+            .mgmt_waitrequest(mgmt_waitrequest),
+            
+            //User data inputs
+            .mgmt_address(mgmt_address),
+            .mgmt_read(mgmt_read),
+            .mgmt_write(mgmt_byteenable_write),
+            .mgmt_writedata(mgmt_writedata),
+
+            // other
+            .mif_start_out(reconfig2mif_start_out),
+            .mif_base_addr(mif_base_addr)
+        );
+
+        
+    end // End generate reconfig core only
+end // End 28nm Reconfig
+endgenerate
+
+endmodule
+
diff --git a/sys/sdram.sv b/sys/sdram.sv
deleted file mode 100644
index 7828cd8..0000000
--- a/sys/sdram.sv
+++ /dev/null
@@ -1,262 +0,0 @@
-//
-// sdram.v
-//
-// Static RAM controller implementation using SDRAM MT48LC16M16A2
-//
-// Copyright (c) 2015,2016 Sorgelig
-//
-// Some parts of SDRAM code used from project:
-// http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version. 
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of 
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License 
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-// ------------------------------------------
-//
-// v2.1 - Add universal 8/16 bit mode.
-//
-
-module sdram
-(
-   input             init,        // reset to initialize RAM
-   input             clk,         // clock ~100MHz
-                                  //
-                                  // SDRAM_* - signals to the MT48LC16M16 chip
-   inout  reg [15:0] SDRAM_DQ,    // 16 bit bidirectional data bus
-   output reg [12:0] SDRAM_A,     // 13 bit multiplexed address bus
-   output reg        SDRAM_DQML,  // two byte masks
-   output reg        SDRAM_DQMH,  // 
-   output reg  [1:0] SDRAM_BA,    // two banks
-   output            SDRAM_nCS,   // a single chip select
-   output            SDRAM_nWE,   // write enable
-   output            SDRAM_nRAS,  // row address select
-   output            SDRAM_nCAS,  // columns address select
-   output            SDRAM_CKE,   // clock enable
-                                  //
-   input       [1:0] wtbt,        // 16bit mode:  bit1 - write high byte, bit0 - write low byte,
-                                  // 8bit mode:  2'b00 - use addr[0] to decide which byte to write
-                                  // Ignored while reading.
-                                  //
-   input      [24:0] addr,        // 25 bit address for 8bit mode. addr[0] = 0 for 16bit mode for correct operations.
-   output     [15:0] dout,        // data output to cpu
-   input      [15:0] din,         // data input from cpu
-   input             we,          // cpu requests write
-   input             rd,          // cpu requests read
-   output reg        ready        // dout is valid. Ready to accept new read/write.
-);
-
-assign SDRAM_nCS  = command[3];
-assign SDRAM_nRAS = command[2];
-assign SDRAM_nCAS = command[1];
-assign SDRAM_nWE  = command[0];
-assign SDRAM_CKE  = cke;
-assign dout       = latched ? data_l : data_d;
-
-// no burst configured
-localparam BURST_LENGTH        = 3'b000;   // 000=1, 001=2, 010=4, 011=8
-localparam ACCESS_TYPE         = 1'b0;     // 0=sequential, 1=interleaved
-localparam CAS_LATENCY         = 3'd2;     // 2 for < 100MHz, 3 for >100MHz
-localparam OP_MODE             = 2'b00;    // only 00 (standard operation) allowed
-localparam NO_WRITE_BURST      = 1'b1;     // 0= write burst enabled, 1=only single access write
-localparam MODE                = {3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
-
-localparam sdram_startup_cycles= 14'd12100;// 100us, plus a little more, @ 100MHz
-localparam cycles_per_refresh  = 14'd780;  // (64000*100)/8192-1 Calc'd as (64ms @ 100MHz)/8192 rose
-localparam startup_refresh_max = 14'b11111111111111;
-
-// SDRAM commands
-localparam CMD_INHIBIT         = 4'b1111;
-localparam CMD_NOP             = 4'b0111;
-localparam CMD_ACTIVE          = 4'b0011;
-localparam CMD_READ            = 4'b0101;
-localparam CMD_WRITE           = 4'b0100;
-localparam CMD_BURST_TERMINATE = 4'b0110;
-localparam CMD_PRECHARGE       = 4'b0010;
-localparam CMD_AUTO_REFRESH    = 4'b0001;
-localparam CMD_LOAD_MODE       = 4'b0000;
-
-reg [13:0] refresh_count = startup_refresh_max - sdram_startup_cycles;
-reg  [3:0] command = CMD_INHIBIT;
-reg        cke     = 0;
-reg [24:0] save_addr;
-
-reg        latched;
-reg [15:0] data;
-wire[15:0] data_l = save_addr[0] ? {data[7:0],     data[15:8]}     : {data[15:8],     data[7:0]};
-wire[15:0] data_d = save_addr[0] ? {SDRAM_DQ[7:0], SDRAM_DQ[15:8]} : {SDRAM_DQ[15:8], SDRAM_DQ[7:0]};
-
-typedef enum
-{
-	STATE_STARTUP,
-	STATE_OPEN_1, STATE_OPEN_2,
-	STATE_WRITE,
-	STATE_READ,
-	STATE_IDLE,	  STATE_IDLE_1, STATE_IDLE_2, STATE_IDLE_3,
-	STATE_IDLE_4, STATE_IDLE_5, STATE_IDLE_6, STATE_IDLE_7
-} state_t;
-
-always @(posedge clk) begin
-	reg old_we, old_rd;
-	reg [CAS_LATENCY:0] data_ready_delay;
-
-	reg [15:0] new_data;
-	reg  [1:0] new_wtbt;
-	reg        new_we;
-	reg        new_rd;
-	reg        save_we = 1;
-
-	state_t state = STATE_STARTUP;
-
-	command <= CMD_NOP;
-	refresh_count  <= refresh_count+1'b1;
-
-	data_ready_delay <= {1'b0, data_ready_delay[CAS_LATENCY:1]};
-
-	// make it ready 1T in advance
-	if(data_ready_delay[1]) {latched, ready} <= {1'b0, 1'b1};
-	if(data_ready_delay[0]) {latched, data}  <= {1'b1, SDRAM_DQ};
-
-	case(state)
-		STATE_STARTUP: begin
-			//------------------------------------------------------------------------
-			//-- This is the initial startup state, where we wait for at least 100us
-			//-- before starting the start sequence
-			//-- 
-			//-- The initialisation is sequence is 
-			//--  * de-assert SDRAM_CKE
-			//--  * 100us wait, 
-			//--  * assert SDRAM_CKE
-			//--  * wait at least one cycle, 
-			//--  * PRECHARGE
-			//--  * wait 2 cycles
-			//--  * REFRESH, 
-			//--  * tREF wait
-			//--  * REFRESH, 
-			//--  * tREF wait 
-			//--  * LOAD_MODE_REG 
-			//--  * 2 cycles wait
-			//------------------------------------------------------------------------
-			cke        <= 1;
-			SDRAM_DQ   <= 16'bZZZZZZZZZZZZZZZZ;
-			SDRAM_DQML <= 1;
-			SDRAM_DQMH <= 1;
-			SDRAM_A    <= 0;
-			SDRAM_BA   <= 0;
-
-			// All the commands during the startup are NOPS, except these
-			if(refresh_count == startup_refresh_max-31) begin
-				// ensure all rows are closed
-				command     <= CMD_PRECHARGE;
-				SDRAM_A[10] <= 1;  // all banks
-				SDRAM_BA    <= 2'b00;
-			end else if (refresh_count == startup_refresh_max-23) begin
-				// these refreshes need to be at least tREF (66ns) apart
-				command     <= CMD_AUTO_REFRESH;
-			end else if (refresh_count == startup_refresh_max-15) 
-				command     <= CMD_AUTO_REFRESH;
-			else if (refresh_count == startup_refresh_max-7) begin
-				// Now load the mode register
-				command     <= CMD_LOAD_MODE;
-				SDRAM_A     <= MODE;
-			end
-
-			//------------------------------------------------------
-			//-- if startup is complete then go into idle mode,
-			//-- get prepared to accept a new command, and schedule
-			//-- the first refresh cycle
-			//------------------------------------------------------
-			if(!refresh_count) begin
-				state   <= STATE_IDLE;
-				ready   <= 1;
-				refresh_count <= 0;
-			end
-		end
-
-		STATE_IDLE_7: state <= STATE_IDLE_6;
-		STATE_IDLE_6: state <= STATE_IDLE_5;
-		STATE_IDLE_5: state <= STATE_IDLE_4;
-		STATE_IDLE_4: state <= STATE_IDLE_3;
-		STATE_IDLE_3: state <= STATE_IDLE_2;
-		STATE_IDLE_2: state <= STATE_IDLE_1;
-		STATE_IDLE_1: begin
-			SDRAM_DQ   <= 16'bZZZZZZZZZZZZZZZZ;
-			state      <= STATE_IDLE;
-			// mask possible refresh to reduce colliding.
-			if(refresh_count > cycles_per_refresh) begin
-            //------------------------------------------------------------------------
-            //-- Start the refresh cycle. 
-            //-- This tasks tRFC (66ns), so 6 idle cycles are needed @ 100MHz
-            //------------------------------------------------------------------------
-				state    <= STATE_IDLE_7;
-				command  <= CMD_AUTO_REFRESH;
-				refresh_count <= refresh_count - cycles_per_refresh + 1'd1;
-			end
-		end
-
-		STATE_IDLE: begin
-			// Priority is to issue a refresh if one is outstanding
-			if(refresh_count > (cycles_per_refresh<<1)) state <= STATE_IDLE_1;
-			else if(new_rd | new_we) begin
-				new_we   <= 0;
-				new_rd   <= 0;
-				save_addr<= addr;
-				save_we  <= new_we;
-				state    <= STATE_OPEN_1;
-				command  <= CMD_ACTIVE;
-				SDRAM_A  <= addr[13:1];
-				SDRAM_BA <= addr[24:23];
-			end
-		end
-
-		// ACTIVE-to-READ or WRITE delay >20ns (-75)
-		STATE_OPEN_1: state <= STATE_OPEN_2;
-		STATE_OPEN_2: begin
-			SDRAM_A     <= {4'b0010, save_addr[22:14]}; 
-			SDRAM_DQML  <= save_we & (new_wtbt ? ~new_wtbt[0] :  save_addr[0]);
-			SDRAM_DQMH  <= save_we & (new_wtbt ? ~new_wtbt[1] : ~save_addr[0]);
-			state       <= save_we ? STATE_WRITE : STATE_READ;
-		end
-
-		STATE_READ: begin
-			state       <= STATE_IDLE_5;
-			command     <= CMD_READ;
-			SDRAM_DQ    <= 16'bZZZZZZZZZZZZZZZZ;
-
-			// Schedule reading the data values off the bus
-			data_ready_delay[CAS_LATENCY] <= 1;
-		end
-
-		STATE_WRITE: begin
-			state       <= STATE_IDLE_5;
-			command     <= CMD_WRITE;
-			SDRAM_DQ    <= new_wtbt ? new_data : {new_data[7:0], new_data[7:0]};
-			ready       <= 1;
-		end
-	endcase
-
-	if(init) begin
-		state <= STATE_STARTUP;
-		refresh_count <= startup_refresh_max - sdram_startup_cycles;
-	end
-
-	old_we <= we;
-	if(we & ~old_we) {ready, new_we, new_data, new_wtbt} <= {1'b0, 1'b1, din, wtbt};
-
-	old_rd <= rd;
-	if(rd & ~old_rd) begin
-		if(ready & ~save_we & (save_addr[24:1] == addr[24:1])) save_addr <= addr;
-			else {ready, new_rd} <= {1'b0, 1'b1};
-	end
-end
-
-endmodule
diff --git a/sys/spdif.v b/sys/spdif.v
index d4e711e..671dcb2 100644
--- a/sys/spdif.v
+++ b/sys/spdif.v
@@ -62,6 +62,40 @@ module spdif
     output       sample_req_o
 );
 
+reg lpf_ce;
+always @(negedge clk_i) begin
+	reg [3:0] div;
+
+	div <= div + 1'd1;
+	if(div == 13) div <= 0;
+
+	lpf_ce <= !div;
+end
+
+wire [15:0] al, ar;
+
+lpf48k #(15) lpf_l
+(
+   .RESET(rst_i),
+   .CLK(clk_i),
+   .CE(lpf_ce),
+	.ENABLE(1),
+
+   .IDATA(audio_l),
+   .ODATA(al)
+);
+
+lpf48k #(15) lpf_r
+(
+   .RESET(rst_i),
+   .CLK(clk_i),
+   .CE(lpf_ce),
+	.ENABLE(1),
+
+   .IDATA(audio_r),
+   .ODATA(ar)
+);
+
 reg         bit_clk_q;
 
 // Clock pulse generator
@@ -104,7 +138,7 @@ end
 // Core SPDIF
 //-----------------------------------------------------------------
 
-wire [31:0] sample_i = {audio_r, audio_l};
+wire [31:0] sample_i = {ar, al};
 
 spdif_core
 u_core
diff --git a/sys/sync_vg.v b/sys/sync_vg.v
index c54ba2f..54fc614 100644
--- a/sys/sync_vg.v
+++ b/sys/sync_vg.v
@@ -1,48 +1,33 @@
 module sync_vg
 #(
-	parameter X_BITS=12,
-	Y_BITS=12
+	parameter X_BITS=12, Y_BITS=12
 )
 (
 	input wire clk,
 	input wire reset,
-	input wire interlaced,
-	input wire [Y_BITS-1:0] v_total_0,
-	input wire [Y_BITS-1:0] v_fp_0,
-	input wire [Y_BITS-1:0] v_bp_0,
-	input wire [Y_BITS-1:0] v_sync_0,
-	input wire [Y_BITS-1:0] v_total_1,
-	input wire [Y_BITS-1:0] v_fp_1,
-	input wire [Y_BITS-1:0] v_bp_1,
-	input wire [Y_BITS-1:0] v_sync_1,
+
+	input wire [Y_BITS-1:0] v_total,
+	input wire [Y_BITS-1:0] v_fp,
+	input wire [Y_BITS-1:0] v_bp,
+	input wire [Y_BITS-1:0] v_sync,
 	input wire [X_BITS-1:0] h_total,
 	input wire [X_BITS-1:0] h_fp,
 	input wire [X_BITS-1:0] h_bp,
 	input wire [X_BITS-1:0] h_sync,
-	input wire [X_BITS-1:0] hv_offset_0,
-	input wire [X_BITS-1:0] hv_offset_1,
+	input wire [X_BITS-1:0] hv_offset,
+
 	output reg vs_out,
 	output reg hs_out,
 	output reg hde_out,
 	output reg vde_out,
-	output reg [Y_BITS:0] v_count_out,
+	output reg [Y_BITS-1:0] v_count_out,
 	output reg [X_BITS-1:0] h_count_out,
 	output reg [X_BITS-1:0] x_out,
-	output reg [Y_BITS:0] y_out,
-	output reg field_out,
-	output wire clk_out
+	output reg [Y_BITS-1:0] y_out
 );
 
 reg [X_BITS-1:0] h_count;
 reg [Y_BITS-1:0] v_count;
-reg field;
-reg [Y_BITS-1:0] v_total;
-reg [Y_BITS-1:0] v_fp;
-reg [Y_BITS-1:0] v_bp;
-reg [Y_BITS-1:0] v_sync;
-reg [X_BITS-1:0] hv_offset;
-
-assign clk_out = !clk;
 
 /* horizontal counter */
 always @(posedge clk)
@@ -67,31 +52,9 @@ always @(posedge clk)
 			v_count <= v_count + 1'd1;
 	end
 
-/* field */
 always @(posedge clk)
 	if (reset)
-	begin
-		field <= 0;
-		v_total <= v_total_0;
-		v_fp <= interlaced ? v_fp_1 : v_fp_0; // In the interlaced mode this value must be inverted as v_fp_1 is still in field0
-		v_bp <= v_bp_0;
-		v_sync <= v_sync_0;
-		hv_offset <= hv_offset_0;
-	end 
-	else 
-	if ((interlaced) && ((v_count == v_total - 1) && (h_count == h_total - 1)))
-	begin
-		field <= field + interlaced;
-		v_total <= field ? v_total_0 : v_total_1;
-		v_fp <= field ? v_fp_1 : v_fp_0; // This order is inverted as v_fp_1 is still in field0
-		v_bp <= field ? v_bp_0 : v_bp_1;
-		v_sync <= field ? v_sync_0 : v_sync_1;
-		hv_offset <= field ? hv_offset_0 : hv_offset_1;
-	end
-
-always @(posedge clk)
-	if (reset)
-		{ vs_out, hs_out, hde_out, vde_out, field_out } <= 4'b0;
+		{ vs_out, hs_out, hde_out, vde_out } <= 0;
 	else begin
 		hs_out <= ((h_count < h_sync));
 
@@ -105,19 +68,11 @@ always @(posedge clk)
 
 		/* H_COUNT_OUT and V_COUNT_OUT */
 		h_count_out <= h_count;
-		if (field)
-			v_count_out <= v_count + v_total_0;
-		else
-			v_count_out <= v_count;
+		v_count_out <= v_count;
 
-		/* X and Y coords � for a backend pattern generator */
+		/* X and Y coords for a backend pattern generator */
 		x_out <= h_count - (h_sync + h_bp);
-		if (interlaced)
-			y_out <= { (v_count - (v_sync + v_bp)) , field };
-		else
-			y_out <= { 1'b0, (v_count - (v_sync + v_bp)) };
-			field_out <= field;
-
+		y_out <= v_count - (v_sync + v_bp);
 	end
 
 endmodule
diff --git a/sys/sys.qip b/sys/sys.qip
index 0697df2..5b397f4 100644
--- a/sys/sys.qip
+++ b/sys/sys.qip
@@ -2,8 +2,8 @@ set_global_assignment -name VERILOG_FILE sys/sys_top.v
 set_global_assignment -name SDC_FILE sys/sys_top.sdc
 set_global_assignment -name QIP_FILE sys/pll.qip
 set_global_assignment -name QIP_FILE sys/pll_hdmi.qip
-set_global_assignment -name SYSTEMVERILOG_FILE sys/sdram.sv
-set_global_assignment -name SYSTEMVERILOG_FILE sys/ddram.sv
+set_global_assignment -name QIP_FILE sys/pll_hdmi_cfg.qip
+set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_lite.sv
 set_global_assignment -name SYSTEMVERILOG_FILE sys/hq2x.sv
 set_global_assignment -name VERILOG_FILE sys/scandoubler.v
 set_global_assignment -name SYSTEMVERILOG_FILE sys/video_mixer.sv
@@ -17,4 +17,7 @@ set_global_assignment -name VERILOG_FILE sys/spdif.v
 set_global_assignment -name VERILOG_FILE sys/sigma_delta_dac.v
 set_global_assignment -name SYSTEMVERILOG_FILE sys/lpf48k.sv
 set_global_assignment -name SYSTEMVERILOG_FILE sys/hdmi_config.sv
+set_global_assignment -name SYSTEMVERILOG_FILE sys/sysmem.sv
+set_global_assignment -name VERILOG_FILE sys/ip/reset_source.v
+set_global_assignment -name SYSTEMVERILOG_FILE sys/vip_config.sv
 set_global_assignment -name VERILOG_FILE sys/hps_io.v
diff --git a/sys/sys_top.sdc b/sys/sys_top.sdc
index c445ee5..8d7a795 100644
--- a/sys/sys_top.sdc
+++ b/sys/sys_top.sdc
@@ -1,15 +1,26 @@
+# Specify root clocks
 create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
 create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
 create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
-create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk]
+create_clock -period "100.0 MHz" [get_pins -compatibility_mode *|h2f_user0_clk] 
 
 derive_pll_clocks
 
+# Specify PLL-generated clock(s)
 #create_generated_clock -source [get_pins -compatibility_mode {*|pll|pll_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}] \
-                      -name SDRAM_CLK [get_ports {SDRAM_CLK}]
+                       -name SDRAM_CLK [get_ports {SDRAM_CLK}]
+
+create_generated_clock -source [get_pins -compatibility_mode {pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
+                       -name HDMI_CLK [get_ports HDMI_TX_CLK]
+
+create_generated_clock -source [get_pins { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk}] \
+                       -name VID_CLK -divide_by 2 -duty_cycle 50 [get_nets {vip|output_inst|vid_clk}]
+
 
 derive_clock_uncertainty
 
+
+# Set acceptable delays for SDRAM chip (See correspondent chip datasheet) 
 #set_input_delay -max -clock SDRAM_CLK 6.4ns [get_ports SDRAM_DQ[*]]
 #set_input_delay -min -clock SDRAM_CLK 3.7ns [get_ports SDRAM_DQ[*]]
 
@@ -20,8 +31,23 @@ derive_clock_uncertainty
 #set_output_delay -max -clock SDRAM_CLK 1.6ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
 #set_output_delay -min -clock SDRAM_CLK -0.9ns [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
 
+# Decouple different clock groups (to simplify routing)
+set_clock_groups -asynchronous \
+   -group [get_clocks { *|pll|pll_inst|altera_pll_i|general[*].gpll~PLL_OUTPUT_COUNTER|divclk}] \
+   -group [get_clocks { pll_hdmi|pll_hdmi_inst|altera_pll_i|cyclonev_pll|counter[0].output_counter|divclk VID_CLK}] \
+   -group [get_clocks { *|h2f_user0_clk}] \
+   -group [get_clocks { FPGA_CLK1_50 FPGA_CLK2_50 FPGA_CLK3_50}]
+
+set_output_delay -max -clock HDMI_CLK 2.0ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
+set_output_delay -min -clock HDMI_CLK -1.5ns [get_ports {HDMI_TX_D[*] HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
+
+# Put constraints on input ports
+set_false_path -from [get_ports {KEY*}] -to *
+set_false_path -from [get_ports {BTN_*}] -to *
+
+# Put constraints on output ports
 set_false_path -from * -to [get_ports {LED_*}]
-set_false_path -from * -to [get_ports {BTN_*}]
 set_false_path -from * -to [get_ports {VGA_*}]
+set_false_path -from * -to [get_ports {AUDIO_SPDIF}]
 set_false_path -from * -to [get_ports {AUDIO_L}]
 set_false_path -from * -to [get_ports {AUDIO_R}]
diff --git a/sys/sys_top.v b/sys/sys_top.v
index 596d84c..6545ef1 100644
--- a/sys/sys_top.v
+++ b/sys/sys_top.v
@@ -1,7 +1,7 @@
 //============================================================================
 //
-//  DE10-nano HAL top module
-//  (c)2017 Sorgelig
+//  MiSTer hardware abstraction module
+//  (c)2017,2018 Sorgelig
 //
 //  This program is free software; you can redistribute it and/or modify it
 //  under the terms of the GNU General Public License as published by the Free
@@ -30,9 +30,9 @@ module sys_top
 	output  [5:0] VGA_R,
 	output  [5:0] VGA_G,
 	output  [5:0] VGA_B,
-	output		  VGA_HS,
+	inout         VGA_HS,  // VGA_HS is secondary SD card detect when VGA_EN = 1 (inactive)
 	output		  VGA_VS,
-	input         VGA_EN,
+	input         VGA_EN,  // active low
 
 	/////////// AUDIO //////////
 	output		  AUDIO_L,
@@ -53,6 +53,8 @@ module sys_top
 	output [23:0] HDMI_TX_D,
 	output        HDMI_TX_HS,
 	output        HDMI_TX_VS,
+	
+	input         HDMI_TX_INT,
 
 	//////////// SDR ///////////
 	output [12:0] SDRAM_A,
@@ -84,6 +86,9 @@ module sys_top
 	////////// MB KEY ///////////
 	input   [1:0] KEY,
 
+	////////// MB SWITCH ////////
+	input   [3:0] SW,
+
 	////////// MB LED ///////////
 	output  [7:0] LED
 );
@@ -91,8 +96,12 @@ module sys_top
 
 assign SDIO_DAT[2:1] = 2'bZZ;
 
+
 //////////////////////////  LEDs  ///////////////////////////////////////
 
+reg [7:0] led_overtake = 0;
+reg [7:0] led_state    = 0;
+
 wire led_p =  led_power[1] ? ~led_power[0] : 1'b0;
 wire led_d =  led_disk[1]  ? ~led_disk[0]  : ~(led_disk[0] | gp_out[29]);
 wire led_u = ~led_user;
@@ -102,7 +111,7 @@ assign LED_HDD   = led_d ? 1'bZ : 1'b0;
 assign LED_USER  = led_u ? 1'bZ : 1'b0;
 
 //LEDs on main board
-assign LED = {3'b000, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u};
+assign LED = (led_overtake & led_state) | (~led_overtake & {3'b000, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u});
 
 
 //////////////////////////  Buttons  ///////////////////////////////////
@@ -180,18 +189,29 @@ cyclonev_hps_interface_mpu_general_purpose h2f_gp
 
 reg [15:0] cfg;
 
-reg  cfg_ready = 0;
-wire audio_96k = cfg[6];
-wire ypbpr_en  = cfg[5];
-wire csync     = cfg[3];
+reg        cfg_got   = 0;
+reg        cfg_set   = 0;
+//wire [2:0] hdmi_res  = cfg[10:8];
+wire       dvi_mode  = cfg[7];
+wire       audio_96k = cfg[6];
+wire       ypbpr_en  = cfg[5];
+wire       csync     = cfg[3];
 `ifndef LITE
 wire vga_scaler= cfg[2];
 `endif
 
+reg        cfg_custom_t = 0;
+reg  [5:0] cfg_custom_p1;
+reg [31:0] cfg_custom_p2;
+
+reg  [4:0] vol_att = 0;
+
+reg        vip_newcfg = 0;
 always@(posedge clk_sys) begin
 	reg  [7:0] cmd;
 	reg        has_cmd;
 	reg        old_strobe;
+	reg  [7:0] cnt = 0;
 
 	old_strobe <= io_strobe;
 
@@ -201,15 +221,60 @@ always@(posedge clk_sys) begin
 		if(!has_cmd) begin
 			has_cmd <= 1;
 			cmd <= io_din[7:0];
+			cnt <= 0;
 		end
-		else
-		if(cmd == 1) begin
-			cfg <= io_din;
-			cfg_ready <= 1;
+		else begin
+			if(cmd == 1) begin
+				cfg <= io_din;
+				cfg_set <= 1;
+			end
+			if(cmd == 'h20) begin
+				cfg_set <= 0;
+				cnt <= cnt + 1'd1;
+				if(cnt<8) begin
+					if(!cnt) vip_newcfg <= ~cfg_ready;
+					case(cnt)
+						0: if(WIDTH  != io_din[11:0]) begin WIDTH  <= io_din[11:0]; vip_newcfg <= 1; end
+						1: if(HFP    != io_din[11:0]) begin HFP    <= io_din[11:0]; vip_newcfg <= 1; end
+						2: if(HS     != io_din[11:0]) begin HS     <= io_din[11:0]; vip_newcfg <= 1; end
+						3: if(HBP    != io_din[11:0]) begin HBP    <= io_din[11:0]; vip_newcfg <= 1; end
+						4: if(HEIGHT != io_din[11:0]) begin HEIGHT <= io_din[11:0]; vip_newcfg <= 1; end
+						5: if(VFP    != io_din[11:0]) begin VFP    <= io_din[11:0]; vip_newcfg <= 1; end
+						6: if(VS     != io_din[11:0]) begin VS     <= io_din[11:0]; vip_newcfg <= 1; end
+						7: if(VBP    != io_din[11:0]) begin VBP    <= io_din[11:0]; vip_newcfg <= 1; end
+					endcase
+					if(cnt == 1) begin
+						cfg_custom_p1 <= 0;
+						cfg_custom_p2 <= 0;
+						cfg_custom_t <= ~cfg_custom_t;
+					end
+				end
+				else begin
+					if(cnt[1:0]==0) cfg_custom_p1 <= io_din[5:0];
+					if(cnt[1:0]==1) cfg_custom_p2[15:0]  <= io_din;
+					if(cnt[1:0]==2) begin
+						cfg_custom_p2[31:16] <= io_din;
+						cfg_custom_t <= ~cfg_custom_t;
+						cnt[1:0] <= 0;
+					end
+				end
+			end
+			if(cmd == 'h25) {led_overtake, led_state} <= io_din;
+			if(cmd == 'h26) vol_att <= io_din[4:0];
+			if(cmd == 'h27) VSET    <= io_din[11:0];
 		end
 	end
 end
 
+always @(posedge clk_sys) begin
+	reg vsd, vsd2;
+	if(~cfg_ready || ~cfg_set) cfg_got <= cfg_set;
+	else begin
+		vsd  <= HDMI_TX_VS;
+		vsd2 <= vsd;
+		if(~vsd2 & vsd) cfg_got <= cfg_set;
+	end
+end
 
 ///////////////////////////  RESET  ///////////////////////////////////
 
@@ -231,19 +296,21 @@ always @(posedge FPGA_CLK2_50) begin
 	resetd2 <= resetd;
 end
 
-// 100MHz
-wire ctl_clk;
+wire clk_ctl;
 
 ///////////////////////// VIP version  ///////////////////////////////
 
+wire iHdmiClk = ~HDMI_TX_CLK;			// Internal HDMI clock, inverted in relation to external clock
+
 `ifndef LITE
 
 wire reset;
 vip vip
 (
 	//Reset/Clock
-	.reset_reset_req(reset_req),
+	.reset_reset_req(reset_req | ~cfg_ready),
 	.reset_reset(reset),
+	.reset_reset_vip(0),
 
 	//DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button.
 	.reset_cold_req(~btn_reset),
@@ -254,7 +321,7 @@ vip vip
 	.ctl_write(ctl_write),
 	.ctl_writedata(ctl_writedata),
 	.ctl_waitrequest(ctl_waitrequest),
-	.ctl_clock(ctl_clk),
+	.ctl_clock(clk_ctl),
 	.ctl_reset(ctl_reset),
 
 	//64-bit DDR3 RAM access
@@ -284,23 +351,20 @@ vip vip
 	.ram2_write(0),
 
 	//Video input
-	.in_vid_clk(clk_vid),
-	.in_vid_data({r_out, g_out, b_out}),
-	.in_vid_de(de),
-	.in_vid_v_sync(vs),
-	.in_vid_h_sync(hs),
-	.in_vid_datavalid(ce_pix),
-	.in_vid_locked(1),
-	.in_vid_f(0),
-	.in_vid_color_encoding(0),
-	.in_vid_bit_width(0),
+	.in_clk(clk_vid),
+	.in_data({r_out, g_out, b_out}),
+	.in_de(de),
+	.in_v_sync(vs),
+	.in_h_sync(hs),
+	.in_ce(ce_pix),
+	.in_f(0),
 
 	//HDMI output
-	.hdmi_vid_clk(~HDMI_TX_CLK),
-	.hdmi_vid_data(hdmi_data),
-	.hdmi_vid_datavalid(HDMI_TX_DE),
-	.hdmi_vid_v_sync(HDMI_TX_VS),
-	.hdmi_vid_h_sync(HDMI_TX_HS)
+	.hdmi_clk(iHdmiClk),
+	.hdmi_data(hdmi_data),
+	.hdmi_de(hdmi_de),
+	.hdmi_v_sync(HDMI_TX_VS),
+	.hdmi_h_sync(HDMI_TX_HS)
 );
 
 wire  [8:0] ctl_address;
@@ -312,11 +376,22 @@ wire  [7:0] ARX, ARY;
 
 vip_config vip_config
 (
-	.clk(ctl_clk),
+	.clk(clk_ctl),
 	.reset(ctl_reset),
 
 	.ARX(ARX),
 	.ARY(ARY),
+	.CFG_SET(vip_newcfg & cfg_got),
+
+	.WIDTH(WIDTH),
+	.HFP(HFP),
+	.HBP(HBP),
+	.HS(HS),
+	.HEIGHT(HEIGHT),
+	.VFP(VFP),
+	.VBP(VBP),
+	.VS(VS),
+	.VSET(VSET),
 
 	.address(ctl_address),
 	.write(ctl_write),
@@ -330,45 +405,22 @@ vip_config vip_config
 
 `ifdef LITE
 
-wire        INTERLACED = 0;
-wire [11:0] V_TOTAL_0 = 750;
-wire [11:0] V_FP_0 = 5;
-wire [11:0] V_BP_0 = 20;
-wire [11:0] V_SYNC_0 = 5;
-wire [11:0] V_TOTAL_1 = 0;
-wire [11:0] V_FP_1 = 0;
-wire [11:0] V_BP_1 = 0;
-wire [11:0] V_SYNC_1 = 0;
-wire [11:0] H_TOTAL = 1650;
-wire [11:0] H_FP = 110;
-wire [11:0] H_BP = 220;
-wire [11:0] H_SYNC = 40;
-wire [11:0] HV_OFFSET_0 = 0;
-wire [11:0] HV_OFFSET_1 = 0;
-
 wire [11:0] x;
-wire [12:0] y;
+wire [11:0] y;
 
 sync_vg #(.X_BITS(12), .Y_BITS(12)) sync_vg
 (
-	.clk(HDMI_TX_CLK),
+	.clk(iHdmiClk),
 	.reset(reset),
-	.interlaced(INTERLACED),
-	.clk_out(), // inverted output clock - unconnected
-	.v_total_0(V_TOTAL_0),
-	.v_fp_0(V_FP_0),
-	.v_bp_0(V_BP_0),
-	.v_sync_0(V_SYNC_0),
-	.v_total_1(V_TOTAL_1),
-	.v_fp_1(V_FP_1),
-	.v_bp_1(V_BP_1),
-	.v_sync_1(V_SYNC_1),
-	.h_total(H_TOTAL),
-	.h_fp(H_FP),
-	.h_bp(H_BP),
-	.h_sync(H_SYNC),
-	.hv_offset_0(HV_OFFSET_0),
-	.hv_offset_1(HV_OFFSET_1),
+	.v_total(HEIGHT+VFP+VBP+VS),
+	.v_fp(VFP),
+	.v_bp(VBP),
+	.v_sync(VS),
+	.h_total(WIDTH+HFP+HBP+HS),
+	.h_fp(HFP),
+	.h_bp(HBP),
+	.h_sync(HS),
+	.hv_offset(0),
 	.vde_out(vde),
 	.hde_out(hde),
 	.vs_out(vs_hdmi),
@@ -376,14 +428,13 @@ sync_vg #(.X_BITS(12), .Y_BITS(12)) sync_vg
 	.h_count_out(),
 	.x_out(x),
 	.y_out(y),
-	.hs_out(hs_hdmi),
-	.field_out(field)
+	.hs_out(hs_hdmi)
 );
 
 wire vde, hde;
 wire vs_hdmi;
 wire hs_hdmi;
-wire field;
+
 
 pattern_vg
 #(
@@ -395,9 +446,9 @@ pattern_vg
 pattern_vg
 (
 	.reset(reset),
-	.clk_in(HDMI_TX_CLK),
+	.clk_in(iHdmiClk),
 	.x(x),
-	.y(y[11:0]),
+	.y(y),
 	.vn_in(vs_hdmi),
 	.hn_in(hs_hdmi),
 	.dn_in(vde & hde),
@@ -406,23 +457,24 @@ pattern_vg
 	.b_in(0),
 	.vn_out(HDMI_TX_VS),
 	.hn_out(HDMI_TX_HS),
-	.den_out(HDMI_TX_DE),
+	.den_out(hdmi_de),
 	.r_out(hdmi_data[23:16]),
 	.g_out(hdmi_data[15:8]),
 	.b_out(hdmi_data[7:0]),
-	.total_active_pix(H_TOTAL - (H_FP + H_BP + H_SYNC)),
-	.total_active_lines(INTERLACED ? (V_TOTAL_0 - (V_FP_0 + V_BP_0 + V_SYNC_0)) + (V_TOTAL_1 - (V_FP_1 + V_BP_1 + V_SYNC_1)) : (V_TOTAL_0 - (V_FP_0 + V_BP_0 + V_SYNC_0))), // originally: 13'd480
+	.total_active_pix(WIDTH),
+	.total_active_lines(HEIGHT),
 	.pattern(4),
 	.ramp_step(20'h0333)
 );
 
+
 wire reset;
 sysmem_lite sysmem
 (
 	//Reset/Clock
 	.reset_reset_req(reset_req),
 	.reset_reset(reset),
-	.ctl_clock(ctl_clk),
+	.ctl_clock(clk_ctl),
 
 	//DE10-nano has no reset signal on GPIO, so core has to emulate cold reset button.
 	.reset_cold_req(~btn_reset),
@@ -452,9 +504,69 @@ sysmem_lite sysmem
 	.ram2_read(0),
 	.ram2_writedata(0),
 	.ram2_byteenable(0),
-	.ram2_write(0)
+	.ram2_write(0),
+
+	// HDMI frame buffer
+	.vbuf_clk(clk_ctl),
+	.vbuf_address(vbuf_address),
+	.vbuf_burstcount(vbuf_burstcount),
+	.vbuf_waitrequest(vbuf_waitrequest),
+	.vbuf_writedata(vbuf_writedata),
+	.vbuf_byteenable(vbuf_byteenable),
+	.vbuf_write(vbuf_write),
+	.vbuf_readdata(vbuf_readdata),
+	.vbuf_readdatavalid(vbuf_readdatavalid),
+	.vbuf_read(vbuf_read)
 );
 
+wire  [27:0] vbuf_address;
+wire   [7:0] vbuf_burstcount;
+wire         vbuf_waitrequest;
+wire [127:0] vbuf_readdata;
+wire         vbuf_readdatavalid;
+wire         vbuf_read;
+wire [127:0] vbuf_writedata;
+wire  [15:0] vbuf_byteenable;
+wire         vbuf_write;
+/*
+assign HDMI_TX_VS = vs_hdmi;
+assign HDMI_TX_HS = hs_hdmi;
+
+hdmi_lite hdmi_lite
+(
+	.reset(reset),
+
+	.clk_video(clk_vid),
+	.ce_pixel(ce_pix),
+	.video_vs(vs),
+	.video_de(de),
+	.video_d({r_out,g_out,b_out}),
+
+	.clk_hdmi(HDMI_TX_CLK),
+	.hdmi_hde(hde),
+	.hdmi_vde(vde),
+	.hdmi_d(hdmi_data),
+	.hdmi_de(hdmi_de),
+
+	.screen_w(WIDTH),
+	.screen_h(HEIGHT),
+	.quadbuf(1),
+	.scale_x(0),
+	.scale_y(0),
+	.scale_auto(1),
+
+	.clk_vbuf(clk_ctl),
+	.vbuf_address(vbuf_address),
+	.vbuf_burstcount(vbuf_burstcount),
+	.vbuf_waitrequest(vbuf_waitrequest),
+	.vbuf_writedata(vbuf_writedata),
+	.vbuf_byteenable(vbuf_byteenable),
+	.vbuf_write(vbuf_write),
+	.vbuf_readdata(vbuf_readdata),
+	.vbuf_readdatavalid(vbuf_readdatavalid),
+	.vbuf_read(vbuf_read)
+);
+*/
 `endif
 
 
@@ -463,42 +575,109 @@ sysmem_lite sysmem
 pll_hdmi pll_hdmi
 (
 	.refclk(FPGA_CLK1_50),
-	.rst(reset),
+	.rst(reset_req),
+	.reconfig_to_pll(reconfig_to_pll),
+	.reconfig_from_pll(reconfig_from_pll),
 	.outclk_0(HDMI_TX_CLK)
 );
 
+//1920x1080@60 PCLK=148.5MHz CEA
+reg  [11:0] WIDTH  = 1920;
+reg  [11:0] HFP    = 88;
+reg  [11:0] HS     = 48;
+reg  [11:0] HBP    = 148;
+reg  [11:0] HEIGHT = 1080;
+reg  [11:0] VFP    = 4;
+reg  [11:0] VS     = 5;
+reg  [11:0] VBP    = 36;
+reg  [11:0] VSET   = 0;
+
+wire [63:0] reconfig_to_pll;
+wire [63:0] reconfig_from_pll;
+wire        cfg_waitrequest;
+reg         cfg_write;
+reg   [5:0] cfg_address;
+reg  [31:0] cfg_data;
+
+pll_hdmi_cfg pll_hdmi_cfg
+(
+	.mgmt_clk(FPGA_CLK1_50),
+	.mgmt_reset(reset_req),
+	.mgmt_waitrequest(cfg_waitrequest),
+	.mgmt_read(0),
+	.mgmt_readdata(),
+	.mgmt_write(cfg_write),
+	.mgmt_address(cfg_address),
+	.mgmt_writedata(cfg_data),
+	.reconfig_to_pll(reconfig_to_pll),
+	.reconfig_from_pll(reconfig_from_pll)
+);
+
+reg cfg_ready = 0;
+
+always @(posedge FPGA_CLK1_50) begin
+	reg gotd = 0, gotd2 = 0;
+	reg custd = 0, custd2 = 0;
+	reg old_wait = 0;
+
+	gotd  <= cfg_got;
+	gotd2 <= gotd;
+	
+	cfg_write <= 0;
+	
+	custd <= cfg_custom_t;
+	custd2 <= custd;
+	if(custd2 != custd & ~gotd) begin
+		cfg_address <= cfg_custom_p1;
+		cfg_data <= cfg_custom_p2;
+		cfg_write <= 1;
+	end
+
+	if(~gotd2 & gotd) begin
+		cfg_address <= 2;
+		cfg_data <= 0;
+		cfg_write <= 1;
+	end
+
+	old_wait <= cfg_waitrequest;
+	if(old_wait & ~cfg_waitrequest & gotd) cfg_ready <= 1;
+end
+
 hdmi_config hdmi_config
 (
 	.iCLK(FPGA_CLK1_50),
-	.iRST_N(cfg_ready),
+	.iRST_N(cfg_ready & ~HDMI_TX_INT),
+
 	.I2C_SCL(HDMI_I2C_SCL),
 	.I2C_SDA(HDMI_I2C_SDA),
 
-	.audio_48k(~audio_96k),
-	.iRES(4), // 720p
-	.iAR(1)   // Aspect Ratio
+	.dvi_mode(dvi_mode),
+	.audio_96k(audio_96k)
 );
 
 wire [23:0] hdmi_data;
+wire        hdmi_de;
+
 osd hdmi_osd
 (
 	.clk_sys(clk_sys),
 
 	.io_osd(io_osd),
 	.io_strobe(io_strobe),
-	.io_din(io_din[7:0]),
+	.io_din(io_din),
 
-	.clk_video(HDMI_TX_CLK),
+	.clk_video(iHdmiClk),
 	.din(hdmi_data),
 	.dout(HDMI_TX_D),
-	.de(HDMI_TX_DE)
+	.de_in(hdmi_de),
+	.de_out(HDMI_TX_DE)
 );
 
 assign HDMI_MCLK = 0;
 i2s i2s
 (
 	.reset(~cfg_ready),
-	.clk_sys(FPGA_CLK1_50),
+	.clk_sys(FPGA_CLK3_50),
 	.half_rate(~audio_96k),
 
 	.sclk(HDMI_SCLK),
@@ -520,12 +699,12 @@ osd vga_osd
 
 	.io_osd(io_osd),
 	.io_strobe(io_strobe),
-	.io_din(io_din[7:0]),
+	.io_din(io_din),
 
 	.clk_video(clk_vid),
 	.din(de ? {r_out, g_out, b_out} : 24'd0),
 	.dout(vga_q),
-	.de(de)
+	.de_in(de)
 );
 
 wire [23:0] vga_o;
@@ -559,12 +738,14 @@ assign VGA_B  = VGA_EN ? 6'bZZZZZZ : vga_o[7:2];
 
 /////////////////////////  Audio output  ////////////////////////////////
 
+wire al, ar, aspdif;
+
 sigma_delta_dac #(15) dac_l
 (
 	.CLK(FPGA_CLK3_50),
 	.RESET(reset),
 	.DACin({audio_l[15] ^ audio_s, audio_l[14:0]}),
-	.DACout(AUDIO_L)
+	.DACout(al)
 );
 
 sigma_delta_dac #(15) dac_r
@@ -572,7 +753,7 @@ sigma_delta_dac #(15) dac_r
 	.CLK(FPGA_CLK3_50),
 	.RESET(reset),
 	.DACin({audio_r[15] ^ audio_s, audio_r[14:0]}),
-	.DACout(AUDIO_R)
+	.DACout(ar)
 );
 
 spdif toslink
@@ -585,14 +766,63 @@ spdif toslink
 	.audio_l(audio_l >> !audio_s),
 	.audio_r(audio_r >> !audio_s),
 
-	.spdif_o(AUDIO_SPDIF)
+	.spdif_o(aspdif)
 );
 
+assign AUDIO_SPDIF = SW[0] ? HDMI_LRCLK : aspdif;
+assign AUDIO_R     = SW[0] ? HDMI_I2S   : ar;
+assign AUDIO_L     = SW[0] ? HDMI_SCLK  : al;
+
+reg [15:0] audio_l; 
+reg [15:0] audio_r;
+
+always @(posedge FPGA_CLK3_50) begin
+	reg signed [15:0] al;
+	reg signed [15:0] ar;
+
+	case({audio_s,audio_mix})
+		'b000: al <= audio_ls;
+		'b001: al <= audio_ls - (audio_ls >> 3) + (audio_rs >> 3);
+		'b010: al <= audio_ls - (audio_ls >> 2) + (audio_rs >> 2);
+		'b011: al <= (audio_ls >> 1) + (audio_rs >> 1);
+		'b100: al <= audio_ls;
+		'b101: al <= audio_ls - (audio_ls >>> 3) + (audio_rs >>> 3);
+		'b110: al <= audio_ls - (audio_ls >>> 2) + (audio_rs >>> 2);
+		'b111: al <= (audio_ls >>> 1) + (audio_rs >>> 1);
+	endcase
+
+	case({audio_s,audio_mix})
+		'b000: ar <= audio_rs;
+		'b001: ar <= audio_rs - (audio_rs >> 3) + (audio_ls >> 3);
+		'b010: ar <= audio_rs - (audio_rs >> 2) + (audio_ls >> 2);
+		'b011: ar <= (audio_rs >> 1) + (audio_ls >> 1);
+		'b100: ar <= audio_rs;
+		'b101: ar <= audio_rs - (audio_rs >>> 3) + (audio_ls >>> 3);
+		'b110: ar <= audio_rs - (audio_rs >>> 2) + (audio_ls >>> 2);
+		'b111: ar <= (audio_rs >>> 1) + (audio_ls >>> 1);
+	endcase
+	
+	if(vol_att[4]) begin
+		audio_l <= 0;
+		audio_r <= 0;
+	end
+	else
+	if(audio_s) begin
+		audio_l <= al >>> vol_att[3:0];
+		audio_r <= ar >>> vol_att[3:0];
+	end
+	else
+	begin
+		audio_l <= al >> vol_att[3:0];
+		audio_r <= ar >> vol_att[3:0];
+	end
+end
 
 ///////////////////  User module connection ////////////////////////////
 
-wire [15:0] audio_l, audio_r;
+wire signed [15:0] audio_ls, audio_rs;
 wire        audio_s;
+wire  [1:0] audio_mix;
 wire  [7:0] r_out, g_out, b_out;
 wire        vs, hs, de;
 wire        clk_sys, clk_vid, ce_pix;
@@ -620,7 +850,7 @@ emu emu
 (
 	.CLK_50M(FPGA_CLK3_50),
 	.RESET(reset),
-	.HPS_BUS({ctl_clk, clk_vid, ce_pix, de, hs, vs, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
+	.HPS_BUS({HDMI_TX_VS, clk_ctl, clk_vid, ce_pix, de, hs, vs, io_wait, clk_sys, io_fpga, io_uio, io_strobe, io_wide, io_din, io_dout}),
 
 	.CLK_VIDEO(clk_vid),
 	.CE_PIXEL(ce_pix),
@@ -641,9 +871,10 @@ emu emu
 	.VIDEO_ARY(ARY),
 `endif
 
-	.AUDIO_L(audio_l),
-	.AUDIO_R(audio_r),
+	.AUDIO_L(audio_ls),
+	.AUDIO_R(audio_rs),
 	.AUDIO_S(audio_s),
+	.AUDIO_MIX(audio_mix),
 	.TAPE_IN(0),
 
 	// SCK  -> CLK
@@ -651,12 +882,12 @@ emu emu
 	// MISO <- DAT0
 	//    Z -> DAT1
 	//    Z -> DAT2
-   // CS   -> DAT3
-
+	// CS   -> DAT3
 	.SD_SCK(SDIO_CLK),
 	.SD_MOSI(SDIO_CMD),
 	.SD_MISO(SDIO_DAT[0]),
 	.SD_CS(SDIO_DAT[3]),
+	.SD_CD(VGA_EN ? VGA_HS : SDIO_CD),
 
 	.DDRAM_CLK(ram_clk),
 	.DDRAM_ADDR(ram_address),
diff --git a/sys/sysmem.qip b/sys/sysmem.qip
deleted file mode 100644
index 6f27d09..0000000
--- a/sys/sysmem.qip
+++ /dev/null
@@ -1,2 +0,0 @@
-set_global_assignment -name SYSTEMVERILOG_FILE sys/sysmem.sv
-set_global_assignment -name VERILOG_FILE sys/ip/reset_source.v 
diff --git a/sys/sysmem.sv b/sys/sysmem.sv
index 4f38ca0..0f60f65 100644
--- a/sys/sysmem.sv
+++ b/sys/sysmem.sv
@@ -27,7 +27,18 @@ module sysmem_lite
 	input          reset_cold_req,        //     reset.cold_req
 	output         reset_reset,           //          .reset
 	input          reset_reset_req,       //          .reset_req
-	input          reset_warm_req         //          .warm_req
+	input          reset_warm_req,        //          .warm_req
+
+	input          vbuf_clk,              //      vbuf.clk
+	input   [27:0] vbuf_address,          //      vbuf.address
+	input    [7:0] vbuf_burstcount,       //          .burstcount
+	output         vbuf_waitrequest,      //          .waitrequest
+	output [127:0] vbuf_readdata,         //          .readdata
+	output         vbuf_readdatavalid,    //          .readdatavalid
+	input          vbuf_read,             //          .read
+	input  [127:0] vbuf_writedata,        //          .writedata
+	input   [15:0] vbuf_byteenable,       //          .byteenable
+	input          vbuf_write             //          .write
 );
 
 assign ctl_clock = clk_vip_clk;
@@ -42,16 +53,16 @@ sysmem_HPS_fpga_interfaces fpga_interfaces (
 	.f2h_warm_rst_req_n       (~reset_source_reset_warm_reset), // f2h_warm_reset_req.reset_n
 	.h2f_user0_clk            (clk_vip_clk),                    //    h2f_user0_clock.clk
 	.h2f_rst_n                (hps_h2f_reset_reset),            //          h2f_reset.reset_n
-	.f2h_sdram0_clk           (clk_vip_clk),                    //   f2h_sdram0_clock.clk
-	.f2h_sdram0_ADDRESS       (0),                              //    f2h_sdram0_data.address
-	.f2h_sdram0_BURSTCOUNT    (0),                              //                   .burstcount
-	.f2h_sdram0_WAITREQUEST   (),                               //                   .waitrequest
-	.f2h_sdram0_READDATA      (),                               //                   .readdata
-	.f2h_sdram0_READDATAVALID (),                               //                   .readdatavalid
-	.f2h_sdram0_READ          (0),                              //                   .read
-	.f2h_sdram0_WRITEDATA     (0),                              //                   .writedata
-	.f2h_sdram0_BYTEENABLE    (0),                              //                   .byteenable
-	.f2h_sdram0_WRITE         (0),                              //                   .write
+	.f2h_sdram0_clk           (vbuf_clk),                       //   f2h_sdram0_clock.clk
+	.f2h_sdram0_ADDRESS       (vbuf_address),                   //    f2h_sdram0_data.address
+	.f2h_sdram0_BURSTCOUNT    (vbuf_burstcount),                //                   .burstcount
+	.f2h_sdram0_WAITREQUEST   (vbuf_waitrequest),               //                   .waitrequest
+	.f2h_sdram0_READDATA      (vbuf_readdata),                  //                   .readdata
+	.f2h_sdram0_READDATAVALID (vbuf_readdatavalid),             //                   .readdatavalid
+	.f2h_sdram0_READ          (vbuf_read),                      //                   .read
+	.f2h_sdram0_WRITEDATA     (vbuf_writedata),                 //                   .writedata
+	.f2h_sdram0_BYTEENABLE    (vbuf_byteenable),                //                   .byteenable
+	.f2h_sdram0_WRITE         (vbuf_write),                     //                   .write
 	.f2h_sdram1_clk           (ramclk1_clk),                    //   f2h_sdram1_clock.clk
 	.f2h_sdram1_ADDRESS       (ram1_address),                   //    f2h_sdram1_data.address
 	.f2h_sdram1_BURSTCOUNT    (ram1_burstcount),                //                   .burstcount
@@ -81,6 +92,7 @@ reset_source reset_source (
 	.cold_req   (reset_cold_req),                //  reset_ctl.cold_req
 	.reset      (reset_reset),                   //           .reset
 	.reset_req  (reset_reset_req),               //           .reset_req
+	.reset_vip  (0),                             //           .reset_vip
 	.warm_req   (reset_warm_req),                //           .warm_req
 	.reset_warm (reset_source_reset_warm_reset), // reset_warm.reset
 	.reset_cold (reset_source_reset_cold_reset)  // reset_cold.reset
diff --git a/sys/vip.qip b/sys/vip.qip
deleted file mode 100644
index abbb0dc..0000000
--- a/sys/vip.qip
+++ /dev/null
@@ -1,2 +0,0 @@
-set_global_assignment -name SYSTEMVERILOG_FILE sys/vip_config.sv
-set_global_assignment -name QIP_FILE sys/vip/synthesis/vip.qip
diff --git a/sys/vip.qsys b/sys/vip.qsys
index 4a96e70..47306be 100644
--- a/sys/vip.qsys
+++ b/sys/vip.qsys
@@ -13,7 +13,7 @@
    {
       datum _sortIndex
       {
-         value = "7";
+         value = "9";
          type = "int";
       }
    }
@@ -21,7 +21,7 @@
    {
       datum _sortIndex
       {
-         value = "3";
+         value = "4";
          type = "int";
       }
    }
@@ -33,11 +33,27 @@
          type = "int";
       }
    }
+   element Input
+   {
+      datum _sortIndex
+      {
+         value = "2";
+         type = "int";
+      }
+   }
    element Mixer
    {
       datum _sortIndex
       {
-         value = "5";
+         value = "6";
+         type = "int";
+      }
+   }
+   element Output
+   {
+      datum _sortIndex
+      {
+         value = "8";
          type = "int";
       }
    }
@@ -53,7 +69,7 @@
    {
       datum _sortIndex
       {
-         value = "4";
+         value = "5";
          type = "int";
       }
    }
@@ -61,7 +77,7 @@
    {
       datum _sortIndex
       {
-         value = "2";
+         value = "3";
          type = "int";
       }
    }
@@ -69,7 +85,7 @@
    {
       datum _sortIndex
       {
-         value = "6";
+         value = "7";
          type = "int";
       }
    }
@@ -489,6 +505,62 @@
          type = "String";
       }
    }
+   element vip
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element vip
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element vip
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element vip
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element vip
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element vip
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
+   element vip
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone V";
+         type = "String";
+      }
+   }
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
@@ -512,16 +584,10 @@
  <instanceScript></instanceScript>
  <interface name="ctl" internal="Controller.control" type="conduit" dir="end" />
  <interface name="finish" internal="Reset_Source.reset_cold_req" />
- <interface
-   name="hdmi"
-   internal="Video_Output.clocked_video"
-   type="conduit"
-   dir="end" />
- <interface
-   name="in"
-   internal="Video_Input.clocked_video"
-   type="conduit"
-   dir="end" />
+ <interface name="hdmi" internal="Output.Output" type="conduit" dir="end" />
+ <interface name="in" internal="Input.input" type="conduit" dir="end" />
+ <interface name="out_mix_0_Output" internal="Output.Output1" />
+ <interface name="out_mix_0_input" internal="Output.input1" />
  <interface name="ram1" internal="HPS.f2h_sdram1_data" type="avalon" dir="end" />
  <interface name="ram2" internal="HPS.f2h_sdram2_data" type="avalon" dir="end" />
  <interface name="ramclk1" internal="HPS.f2h_sdram1_clock" type="clock" dir="end" />
@@ -531,13 +597,13 @@
    internal="Reset_Source.reset_ctl"
    type="conduit"
    dir="end" />
- <module name="Controller" kind="avalon_combiner" version="1.0" enabled="1" />
+ <module name="Controller" kind="avalon_combiner" version="17.0" enabled="1" />
  <module name="Frame_Buffer" kind="alt_vip_cl_vfb" version="17.0" enabled="1">
   <parameter name="AUTO_DEVICE" value="5CSEBA6U23I7" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
   <parameter name="BITS_PER_SYMBOL" value="8" />
   <parameter name="BURST_ALIGNMENT" value="1" />
-  <parameter name="CLOCKS_ARE_SEPARATE" value="1" />
+  <parameter name="CLOCKS_ARE_SEPARATE" value="0" />
   <parameter name="COLOR_PLANES_ARE_IN_PARALLEL" value="1" />
   <parameter name="CONTROLLED_DROP_REPEAT" value="0" />
   <parameter name="DROP_FRAMES" value="1" />
@@ -557,20 +623,20 @@
   <parameter name="MEM_PORT_WIDTH" value="128" />
   <parameter name="MULTI_FRAME_DELAY" value="1" />
   <parameter name="NUMBER_OF_COLOR_PLANES" value="3" />
-  <parameter name="PIXELS_IN_PARALLEL" value="1" />
+  <parameter name="PIXELS_IN_PARALLEL" value="2" />
   <parameter name="READER_RUNTIME_CONTROL" value="0" />
   <parameter name="READY_LATENCY" value="1" />
-  <parameter name="READ_BURST_TARGET" value="32" />
+  <parameter name="READ_BURST_TARGET" value="64" />
   <parameter name="READ_FIFO_DEPTH" value="512" />
   <parameter name="REPEAT_FRAMES" value="1" />
   <parameter name="TEST_INIT" value="0" />
   <parameter name="USER_PACKETS_MAX_STORAGE" value="1" />
   <parameter name="USE_BUFFER_OFFSET" value="0" />
   <parameter name="WRITER_RUNTIME_CONTROL" value="0" />
-  <parameter name="WRITE_BURST_TARGET" value="32" />
+  <parameter name="WRITE_BURST_TARGET" value="64" />
   <parameter name="WRITE_FIFO_DEPTH" value="512" />
  </module>
- <module name="HPS" kind="altera_hps_lite" version="16.1" enabled="1">
+ <module name="HPS" kind="altera_hps_lite" version="17.0" enabled="1">
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
   <parameter name="BONDING_OUT_ENABLED" value="false" />
   <parameter name="BOOTFROMFPGA_Enable" value="false" />
@@ -784,6 +850,7 @@
   <parameter name="usb_mp_clk_div" value="0" />
   <parameter name="use_default_mpu_clk" value="true" />
  </module>
+ <module name="Input" kind="in_split" version="17.0" enabled="1" />
  <module name="Mixer" kind="alt_vip_cl_mixer" version="17.0" enabled="1">
   <parameter name="ALPHA_ENABLE" value="0" />
   <parameter name="ALPHA_STREAMS_ENABLE" value="0" />
@@ -801,18 +868,19 @@
   <parameter name="NUMBER_OF_COLOR_PLANES" value="2" />
   <parameter name="PATTERN" value="uniform" />
   <parameter name="PIPELINE_READY" value="0" />
-  <parameter name="PIXELS_IN_PARALLEL" value="1" />
+  <parameter name="PIXELS_IN_PARALLEL" value="2" />
   <parameter name="UNIFORM_VALUE_BCR" value="0" />
   <parameter name="UNIFORM_VALUE_GCB" value="0" />
   <parameter name="UNIFORM_VALUE_RY" value="0" />
   <parameter name="USER_PACKET_FIFO_DEPTH" value="0" />
   <parameter name="USER_PACKET_SUPPORT" value="DISCARD" />
  </module>
- <module name="Reset_Source" kind="reset_source" version="1.0" enabled="1" />
+ <module name="Output" kind="out_mix" version="17.0" enabled="1" />
+ <module name="Reset_Source" kind="reset_source" version="17.0" enabled="1" />
  <module name="Scaler" kind="alt_vip_cl_scl" version="17.0" enabled="1">
-  <parameter name="ALGORITHM_NAME" value="BICUBIC" />
+  <parameter name="ALGORITHM_NAME" value="POLYPHASE" />
   <parameter name="ALWAYS_DOWNSCALE" value="0" />
-  <parameter name="ARE_IDENTICAL" value="0" />
+  <parameter name="ARE_IDENTICAL" value="1" />
   <parameter name="AUTO_DEVICE" value="5CSEBA6U23I7" />
   <parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
   <parameter name="BITS_PER_SYMBOL" value="8" />
@@ -820,7 +888,7 @@
   <parameter name="DEFAULT_LOWER_BLUR" value="0" />
   <parameter name="DEFAULT_UPPER_BLUR" value="0" />
   <parameter name="ENABLE_FIR" value="0" />
-  <parameter name="EXTRA_PIPELINING" value="0" />
+  <parameter name="EXTRA_PIPELINING" value="1" />
   <parameter name="FAMILY" value="Cyclone V" />
   <parameter name="H_BANKS" value="1" />
   <parameter name="H_COEFF_FILE"><![CDATA[<enter file name (including full path)>]]></parameter>
@@ -840,7 +908,7 @@
   <parameter name="MAX_OUT_HEIGHT" value="1080" />
   <parameter name="MAX_OUT_WIDTH" value="1920" />
   <parameter name="NO_BLANKING" value="0" />
-  <parameter name="PIXELS_IN_PARALLEL" value="1" />
+  <parameter name="PIXELS_IN_PARALLEL" value="2" />
   <parameter name="PRESERVE_BITS" value="0" />
   <parameter name="RUNTIME_CONTROL" value="1" />
   <parameter name="SYMBOLS_IN_PAR" value="3" />
@@ -850,9 +918,9 @@
   <parameter name="V_BANKS" value="1" />
   <parameter name="V_COEFF_FILE"><![CDATA[<enter file name (including full path)>]]></parameter>
   <parameter name="V_FRACTION_BITS" value="7" />
-  <parameter name="V_FUNCTION" value="LANCZOS_3" />
+  <parameter name="V_FUNCTION" value="LANCZOS_2" />
   <parameter name="V_INTEGER_BITS" value="1" />
-  <parameter name="V_PHASES" value="16" />
+  <parameter name="V_PHASES" value="32" />
   <parameter name="V_SIGNED" value="1" />
   <parameter name="V_SYMMETRIC" value="0" />
   <parameter name="V_TAPS" value="4" />
@@ -877,7 +945,7 @@
   <parameter name="NO_OF_CHANNELS" value="1" />
   <parameter name="NUMBER_OF_COLOUR_PLANES" value="3" />
   <parameter name="OVERFLOW_HANDLING" value="0" />
-  <parameter name="PIXELS_IN_PARALLEL" value="1" />
+  <parameter name="PIXELS_IN_PARALLEL" value="2" />
   <parameter name="STD_WIDTH" value="1" />
   <parameter name="SYNC_TO" value="2" />
   <parameter name="USE_CONTROL" value="0" />
@@ -909,27 +977,27 @@
   <parameter name="F_FALLING_EDGE" value="0" />
   <parameter name="F_RISING_EDGE" value="0" />
   <parameter name="GENERATE_SYNC" value="0" />
-  <parameter name="H_ACTIVE_PIXELS" value="1280" />
-  <parameter name="H_BACK_PORCH" value="220" />
+  <parameter name="H_ACTIVE_PIXELS" value="1920" />
+  <parameter name="H_BACK_PORCH" value="148" />
   <parameter name="H_BLANK" value="0" />
-  <parameter name="H_FRONT_PORCH" value="110" />
-  <parameter name="H_SYNC_LENGTH" value="40" />
+  <parameter name="H_FRONT_PORCH" value="88" />
+  <parameter name="H_SYNC_LENGTH" value="44" />
   <parameter name="INTERLACED" value="0" />
-  <parameter name="LOW_LATENCY" value="0" />
+  <parameter name="LOW_LATENCY" value="1" />
   <parameter name="NO_OF_CHANNELS" value="1" />
   <parameter name="NO_OF_MODES" value="1" />
   <parameter name="NUMBER_OF_COLOUR_PLANES" value="3" />
-  <parameter name="PIXELS_IN_PARALLEL" value="1" />
+  <parameter name="PIXELS_IN_PARALLEL" value="2" />
   <parameter name="SRC_WIDTH" value="8" />
   <parameter name="STD_WIDTH" value="1" />
   <parameter name="TASK_WIDTH" value="8" />
   <parameter name="THRESHOLD" value="1999" />
   <parameter name="USE_CONTROL" value="1" />
   <parameter name="USE_EMBEDDED_SYNCS" value="0" />
-  <parameter name="V_ACTIVE_LINES" value="720" />
-  <parameter name="V_BACK_PORCH" value="20" />
+  <parameter name="V_ACTIVE_LINES" value="1080" />
+  <parameter name="V_BACK_PORCH" value="15" />
   <parameter name="V_BLANK" value="0" />
-  <parameter name="V_FRONT_PORCH" value="5" />
+  <parameter name="V_FRONT_PORCH" value="2" />
   <parameter name="V_SYNC_LENGTH" value="5" />
  </module>
  <connection
@@ -980,13 +1048,13 @@
  <connection
    kind="avalon_streaming"
    version="17.0"
-   start="Frame_Buffer.dout"
-   end="Scaler.din" />
+   start="Mixer.dout"
+   end="Video_Output.din" />
  <connection
    kind="avalon_streaming"
    version="17.0"
-   start="Mixer.dout"
-   end="Video_Output.din" />
+   start="Frame_Buffer.dout"
+   end="Scaler.din" />
  <connection
    kind="avalon_streaming"
    version="17.0"
@@ -1017,6 +1085,11 @@
    version="17.0"
    start="HPS.h2f_user0_clock"
    end="Video_Input.main_clock" />
+ <connection
+   kind="clock"
+   version="17.0"
+   start="HPS.h2f_user0_clock"
+   end="Frame_Buffer.main_clock" />
  <connection
    kind="clock"
    version="17.0"
@@ -1033,15 +1106,27 @@
    start="HPS.h2f_user0_clock"
    end="Video_Output.main_clock" />
  <connection
-   kind="clock"
+   kind="conduit"
    version="17.0"
-   start="HPS.h2f_user0_clock"
-   end="Frame_Buffer.main_clock" />
+   start="Video_Input.clocked_video"
+   end="Input.Output">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
  <connection
-   kind="clock"
+   kind="conduit"
    version="17.0"
-   start="HPS.h2f_user0_clock"
-   end="Frame_Buffer.mem_clock" />
+   start="Video_Output.clocked_video"
+   end="Output.input">
+  <parameter name="endPort" value="" />
+  <parameter name="endPortLSB" value="0" />
+  <parameter name="startPort" value="" />
+  <parameter name="startPortLSB" value="0" />
+  <parameter name="width" value="0" />
+ </connection>
  <connection
    kind="reset"
    version="17.0"
@@ -1077,11 +1162,6 @@
    version="17.0"
    start="Reset_Source.reset_sys"
    end="Video_Output.main_reset" />
- <connection
-   kind="reset"
-   version="17.0"
-   start="Reset_Source.reset_sys"
-   end="Frame_Buffer.mem_reset" />
  <connection
    kind="reset"
    version="17.0"
diff --git a/sys/vip_config.sv b/sys/vip_config.sv
index d5349b6..89bf241 100644
--- a/sys/vip_config.sv
+++ b/sys/vip_config.sv
@@ -6,6 +6,18 @@ module vip_config
 	
 	input       [7:0] ARX,
 	input       [7:0] ARY,
+	input             CFG_SET,
+
+	input      [11:0] WIDTH,
+	input      [11:0] HFP,
+	input      [11:0] HBP,
+	input      [11:0] HS,
+	input      [11:0] HEIGHT,
+	input      [11:0] VFP,
+	input      [11:0] VBP,
+	input      [11:0] VS,
+	
+	input      [11:0] VSET,
 
 	output reg  [8:0] address,
 	output reg        write,
@@ -13,156 +25,134 @@ module vip_config
 	input             waitrequest
 );
 
-//Any input video resolution up to 1920x1080 is supported.
 
-//Output video parameters.
-//It's good to keep 1280x720@60 resolution among all cores as most compatible resolution.
-parameter  WIDTH  = 1280;
-parameter  HEIGHT = 720;
-parameter  HFP    = 110;
-parameter  HBP    = 220;
-parameter  HS     = 40;
-parameter  VFP    = 5;
-parameter  VBP    = 20;
-parameter  VS     = 5;
+reg         newres = 1;
 
+wire [21:0] init[23] =
+'{
+	//video mode
+	{newres, 2'd2, 7'd04, 12'd0  }, //Bank
+	{newres, 2'd2, 7'd30, 12'd0  }, //Valid
+	{newres, 2'd2, 7'd05, 12'd0  }, //Progressive/Interlaced
+	{newres, 2'd2, 7'd06, w      }, //Active pixel count
+	{newres, 2'd2, 7'd07, h      }, //Active line count
+	{newres, 2'd2, 7'd09, hfp    }, //Horizontal Front Porch
+	{newres, 2'd2, 7'd10, hs     }, //Horizontal Sync Length
+	{newres, 2'd2, 7'd11, hb     }, //Horizontal Blanking (HFP+HBP+HSync)
+	{newres, 2'd2, 7'd12, vfp    }, //Vertical Front Porch
+	{newres, 2'd2, 7'd13, vs     }, //Vertical Sync Length
+	{newres, 2'd2, 7'd14, vb     }, //Vertical blanking (VFP+VBP+VSync)
+	{newres, 2'd2, 7'd30, 12'd1  }, //Valid
+	{newres, 2'd2, 7'd00, 12'd1  }, //Go
 
-reg  [31:0] wcalc;
-reg  [31:0] hcalc;
+	//mixer
+	{  1'd1, 2'd1, 7'd03, w      }, //Bkg Width
+	{  1'd1, 2'd1, 7'd04, h      }, //Bkg Height
+	{  1'd1, 2'd1, 7'd08, posx   }, //Pos X
+	{  1'd1, 2'd1, 7'd09, posy   }, //Pos Y
+	{  1'd1, 2'd1, 7'd10, 12'd1  }, //Enable Video 0
+	{  1'd1, 2'd1, 7'd00, 12'd1  }, //Go
 
-wire [31:0] videow = (wcalc > WIDTH)  ? WIDTH  : wcalc;
-wire [31:0] videoh = (hcalc > HEIGHT) ? HEIGHT : hcalc;
+	//scaler
+	{  1'd1, 2'd0, 7'd03, videow }, //Output Width
+	{  1'd1, 2'd0, 7'd04, videoh }, //Output Height
+	{  1'd1, 2'd0, 7'd00, 12'd1  }, //Go
 
-wire [31:0] posx   = (WIDTH - videow)>>1;
-wire [31:0] posy   = (HEIGHT- videoh)>>1;
+	22'h3FFFFF
+};
 
+reg [11:0] w;
+reg [11:0] hfp;
+reg [11:0] hbp;
+reg [11:0] hs;
+reg [11:0] hb;
+reg [11:0] h;
+reg [11:0] vfp;
+reg [11:0] vbp;
+reg [11:0] vs;
+reg [11:0] vb;
+
+reg [11:0] videow;
+reg [11:0] videoh;
+
+reg [11:0] posx;
+reg [11:0] posy;
 
 always @(posedge clk) begin
-	reg [7:0] state = 0;
-	reg [7:0] arx, ary;
-	integer timeout = 0;
+	reg  [7:0] state = 0;
+	reg  [7:0] arx, ary;
+	reg  [7:0] arxd, aryd;
+	reg [11:0] vset, vsetd;
+	reg        cfg, cfgd;
+	reg [31:0] wcalc;
+	reg [31:0] hcalc;
+	reg [12:0] timeout = 0;
 
-	if(reset || (!state && ((arx != ARX) || (ary != ARY)))) begin
-		arx <= ARX;
-		ary <= ARY;
-		timeout <= 0;
-		write   <= 0;
+	arxd  <= ARX;
+	aryd  <= ARY;
+	vsetd <= VSET;
+	
+	cfg   <= CFG_SET;
+	cfgd  <= cfg;
+
+	write <= 0;
+	if(reset || (arx != arxd) || (ary != aryd) || (vset != vsetd) || (~cfgd && cfg)) begin
+		arx <= arxd;
+		ary <= aryd;
+		vset <= vsetd;
+		timeout <= '1;
+		state <= 0;
+		if(reset || (~cfgd && cfg)) newres <= 1;
 	end
 	else
-	if(timeout < 1000000)
+	if(timeout > 0)
 	begin
-		timeout <= timeout + 1;
-		write <= 0;
+		timeout <= timeout - 1'd1;
 		state <= 1;
+		if(!(timeout & 'h1f)) case(timeout>>5)
+			5:	begin
+					w   <= WIDTH;
+					hfp <= HFP;
+					hbp <= HBP;
+					hs  <= HS;
+					h   <= HEIGHT;
+					vfp <= VFP;
+					vbp <= VBP;
+					vs  <= VS;
+				end
+			4: begin
+					hb  <= hfp+hbp+hs;
+					vb  <= vfp+vbp+vs;
+				end
+			3: begin
+					wcalc <= vset ? (vset*arx)/ary : (h*arx)/ary;
+					hcalc <= (w*ary)/arx;
+				end
+			2: begin
+					videow <= (!vset && (wcalc > w))    ? w : wcalc[11:0];
+					videoh <= vset ? vset : (hcalc > h) ? h : hcalc[11:0];
+				end
+			1: begin
+					posx <= (w - videow)>>1;
+					posy <= (h - videoh)>>1;
+				end
+		endcase
 	end
 	else
 	if(~waitrequest && state)
 	begin
 		state <= state + 1'd1;
-		write <= 1;
-
-		case(state)
-			01: begin
-					wcalc <= (HEIGHT*arx)/ary;
-					hcalc <= (WIDTH*ary)/arx;
-				end
-		endcase
-		
-		if(state&3) write <= 0;
-		else 
-		case(state>>2)
-			//scaler
-			01: begin
-					address   <= 'h003; //Output Width
-					writedata <= videow;
-				end
-			02: begin
-					address   <= 'h004; //Output Height
-					writedata <= videoh;
-				end
-			03: begin
-					address   <= 'h000; //Go
-					writedata <= 1;
-				end
-
-			//mixer
-			10: begin
-					address   <= 'h083; //Bkg Width
-					writedata <= WIDTH;
-				end
-			11: begin
-					address   <= 'h084; //Bkg Height
-					writedata <= HEIGHT;
-				end
-			12: begin
-					address   <= 'h088; //Pos X
-					writedata <= posx;
-				end
-			13: begin
-					address   <= 'h089; //Pos Y
-					writedata <= posy;
-				end
-			14: begin
-					address   <= 'h08A; //Enable Video 0
-					writedata <= 1;
-				end
-			15: begin
-					address   <= 'h080; //Go
-					writedata <= 1;
-				end
-
-			//video mode
-			20: begin
-					address   <= 'h104; //Bank
-					writedata <= 0;
-				end
-			21: begin
-					address   <= 'h105; //Progressive/Interlaced
-					writedata <= 0;
-				end
-			22: begin
-					address   <= 'h106; //Active pixel count
-					writedata <= WIDTH;
-				end
-			23: begin
-					address   <= 'h107; //Active line count
-					writedata <= HEIGHT;
-				end
-			24: begin
-					address   <= 'h109; //Horizontal Front Porch
-					writedata <= HFP;
-				end
-			25: begin
-					address   <= 'h10A; //Horizontal Sync Length
-					writedata <= HS;
-				end
-			26: begin
-					address   <= 'h10B; //Horizontal Blanking (HFP+HBP+HSync)
-					writedata <= HFP+HBP+HS;
-				end
-			27: begin
-					address   <= 'h10C; //Vertical Front Porch
-					writedata <= VFP;
-				end
-			28: begin
-					address   <= 'h10D; //Vertical Sync Length
-					writedata <= VS;
-				end
-			29: begin
-					address   <= 'h10E; //Vertical blanking (VFP+VBP+VSync)
-					writedata <= VFP+VBP+VS;
-				end
-			30: begin
-					address   <= 'h11E; //Valid
-					writedata <= 1;
-				end
-			31: begin
-					address   <= 'h100; //Go
-					writedata <= 1;
-				end
-
-			default: write  <= 0;
-		endcase
+		write <= 0;
+		if((state&3)==3) begin
+			if(init[state>>2] == 22'h3FFFFF) begin
+				state  <= 0;
+				newres <= 0;
+			end
+			else begin
+				writedata <= 0;
+				{write, address, writedata[11:0]} <= init[state>>2];
+			end
+		end
 	end
 end