148 lines
4.3 KiB
VHDL
148 lines
4.3 KiB
VHDL
-- PS2_Ctrl.vhd
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-- ------------------------------------------------
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-- Simplified PS/2 Controller (kbd, mouse...)
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-- ------------------------------------------------
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-- Only the Receive function is implemented !
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-- (c) ALSE. http://www.alse-fr.com
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library IEEE;
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use IEEE.Std_Logic_1164.all;
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use IEEE.Numeric_Std.all;
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-- --------------------------------------
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Entity PS2_Ctrl is
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-- --------------------------------------
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generic (FilterSize : positive := 8);
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port( Clk : in std_logic; -- System Clock
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Reset : in std_logic; -- System Reset
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PS2_Clk : in std_logic; -- Keyboard Clock Line
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PS2_Data : in std_logic; -- Keyboard Data Line
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DoRead : in std_logic; -- From outside when reading the scan code
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Scan_Err : out std_logic; -- To outside : Parity or Overflow error
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Scan_DAV : out std_logic; -- To outside when a scan code has arrived
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Scan_Code : out unsigned(7 downto 0) -- Eight bits Data Out
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);
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end PS2_Ctrl;
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-- --------------------------------------
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Architecture ALSE_RTL of PS2_Ctrl is
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-- --------------------------------------
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-- (c) ALSE. http://www.alse-fr.com
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-- Author : Bert Cuzeau.
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-- Fully synchronous solution, same Filter on PS2_Clk.
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-- Still as compact as "Plain_wrong"...
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-- Possible improvement : add TIMEOUT on PS2_Clk while shifting
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-- Note: PS2_Data is resynchronized though this should not be
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-- necessary (qualified by Fall_Clk and does not change at that time).
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-- Note the tricks to correctly interpret 'H' as '1' in RTL simulation.
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signal PS2_Datr : std_logic;
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subtype Filter_t is std_logic_vector(FilterSize-1 downto 0);
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signal Filter : Filter_t;
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signal Fall_Clk : std_logic;
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signal Bit_Cnt : unsigned(3 downto 0);
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signal Parity : std_logic;
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signal Scan_DAVi : std_logic;
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signal S_Reg : unsigned(8 downto 0);
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signal PS2_Clk_f : std_logic;
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Type State_t is (Idle, Shifting);
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signal State : State_t;
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begin
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Scan_DAV <= Scan_DAVi;
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-- This filters digitally the raw clock signal coming from the keyboard :
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-- * Eight consecutive PS2_Clk=1 makes the filtered_clock go high
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-- * Eight consecutive PS2_Clk=0 makes the filtered_clock go low
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-- Implies a (FilterSize+1) x Tsys_clock delay on Fall_Clk wrt Data
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-- Also in charge of the re-synchronization of PS2_Data
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process (Clk,Reset)
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begin
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if Reset='1' then
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PS2_Datr <= '0';
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PS2_Clk_f <= '0';
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Filter <= (others=>'0');
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Fall_Clk <= '0';
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elsif rising_edge (Clk) then
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PS2_Datr <= PS2_Data and PS2_Data; -- also turns 'H' into '1'
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Fall_Clk <= '0';
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Filter <= (PS2_Clk and PS2_CLK) & Filter(Filter'high downto 1);
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if Filter = Filter_t'(others=>'1') then
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PS2_Clk_f <= '1';
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elsif Filter = Filter_t'(others=>'0') then
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PS2_Clk_f <= '0';
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if PS2_Clk_f = '1' then
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Fall_Clk <= '1';
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end if;
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end if;
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end if;
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end process;
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-- This simple State Machine reads in the Serial Data
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-- coming from the PS/2 peripheral.
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process(Clk,Reset)
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begin
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if Reset='1' then
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State <= Idle;
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Bit_Cnt <= (others => '0');
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S_Reg <= (others => '0');
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Scan_Code <= (others => '0');
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Parity <= '0';
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Scan_Davi <= '0';
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Scan_Err <= '0';
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elsif rising_edge (Clk) then
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if DoRead='1' then
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Scan_Davi <= '0'; -- note: this assgnmnt can be overriden
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end if;
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case State is
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when Idle =>
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Parity <= '0';
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Bit_Cnt <= (others => '0');
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-- note that we dont need to clear the Shift Register
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if Fall_Clk='1' and PS2_Datr='0' then -- Start bit
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Scan_Err <= '0';
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State <= Shifting;
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end if;
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when Shifting =>
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if Bit_Cnt >= 9 then
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if Fall_Clk='1' then -- Stop Bit
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-- Error is (wrong Parity) or (Stop='0') or Overflow
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Scan_Err <= (not Parity) or (not PS2_Datr) or Scan_DAVi;
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Scan_Davi <= '1';
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Scan_Code <= S_Reg(7 downto 0);
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State <= Idle;
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end if;
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elsif Fall_Clk='1' then
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Bit_Cnt <= Bit_Cnt + 1;
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S_Reg <= PS2_Datr & S_Reg (S_Reg'high downto 1); -- Shift right
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Parity <= Parity xor PS2_Datr;
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end if;
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when others => -- never reached
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State <= Idle;
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end case;
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--Scan_Err <= '0'; -- to create an on-purpose error on Scan_Err !
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end if;
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end process;
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end ALSE_RTL;
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