66 lines
1.9 KiB
Verilog
66 lines
1.9 KiB
Verilog
// taken from the Apple II project by Alex Freed
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// and modified for own use
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module ramcard(mclk28,reset_in,addr,ram_addr, we, card_ram_we,card_ram_rd, bank1);
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input mclk28;
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input reset_in;
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input [15:0] addr;
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output [17:0] ram_addr;
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input we;
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output card_ram_we;
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output card_ram_rd;
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output bank1;
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reg bank1, read_en, write_en, pre_wr_en, bankB, sat_read_en, sat_write_en, sat_pre_wr_en, sat_en;
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reg [2:0] bank16k;
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reg [15:0] addr2;
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wire Dxxx,DEF;
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always @(posedge mclk28) begin
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addr2 <= addr;
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if(reset_in) begin
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bank1 <= 0;
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read_en <= 0;
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write_en <= 1;
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pre_wr_en <= 0;
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bankB <= 0;
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sat_read_en <= 0;
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sat_write_en <= 0;
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sat_pre_wr_en <= 0;
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end
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else
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begin
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if((addr[15:4] == 'hC08) & (addr2 != addr)) begin
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// Looks like a Language Card in slot 0
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bank1 <= addr[3];
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pre_wr_en <= addr[0] & ~we;
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write_en <= addr[0] & pre_wr_en & ~we;
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read_en <= ~(addr[0] ^ addr[1]);
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end
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if((addr[15:4] == 'hC0D) & (addr2 != addr)) begin
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// Looks like Saturn128 Card in slot 5
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if(addr[2] == 0) begin
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// State selection
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bankB <= addr[3];
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sat_pre_wr_en <= addr[0];
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sat_write_en <= addr[0] & sat_pre_wr_en;
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sat_read_en <= ~(addr[0] ^ addr[1]);
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end
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else
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begin
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// 16K bank selection
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bank16k <= {addr[3], addr[1], addr[0]};
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end
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end
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end
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end
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assign Dxxx = (addr[15:12] == 4'b1101);
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assign DEF = ((addr[15:14] == 2'b11) & (addr[13:12] != 2'b00));
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assign ram_addr = ((sat_write_en || sat_read_en) && DEF)?{1'b1, bank16k, addr[13], addr[12] & ~(bankB & Dxxx), addr[11:0]}:{2'b0,addr[15:13], addr[12] & ~(bank1 & Dxxx), addr[11:0]};
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assign card_ram_we = (write_en | sat_write_en);
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assign card_ram_rd = (read_en | sat_read_en);
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endmodule
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