187 lines
4.0 KiB
Verilog
187 lines
4.0 KiB
Verilog
//
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// scandoubler.v
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//
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// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
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// Copyright (c) 2017 Sorgelig
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// TODO: Delay vsync one line
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module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
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(
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// system interface
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input clk_sys,
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input ce_pix,
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output ce_pix_out,
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input hq2x,
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// shifter video interface
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input hs_in,
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input vs_in,
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input hb_in,
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input vb_in,
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input [DWIDTH:0] r_in,
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input [DWIDTH:0] g_in,
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input [DWIDTH:0] b_in,
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input mono,
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// output interface
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output reg hs_out,
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output vs_out,
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output hb_out,
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output vb_out,
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output [DWIDTH:0] r_out,
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output [DWIDTH:0] g_out,
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output [DWIDTH:0] b_out
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);
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localparam DWIDTH = HALF_DEPTH ? 3 : 7;
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assign vs_out = vs_in;
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assign ce_pix_out = ce_x4;
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//Compensate picture shift after HQ2x
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assign vb_out = vbo[2];
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assign hb_out = &hbo[5:4];
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reg [7:0] pix_len = 0;
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wire [7:0] pl = pix_len + 1'b1;
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reg ce_x1, ce_x4;
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reg req_line_reset;
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always @(negedge clk_sys) begin
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reg old_ce;
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reg [2:0] ce_cnt;
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reg [7:0] pixsz2, pixsz4 = 0;
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old_ce <= ce_pix;
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if(~&pix_len) pix_len <= pix_len + 1'd1;
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ce_x4 <= 0;
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ce_x1 <= 0;
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// use such odd comparison to place ce_x4 evenly if master clock isn't multiple 4.
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if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
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ce_x4 <= 1;
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end
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if(~old_ce & ce_pix) begin
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pixsz2 <= {1'b0, pl[7:1]};
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pixsz4 <= {2'b00, pl[7:2]};
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ce_x1 <= 1;
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ce_x4 <= 1;
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pix_len <= 0;
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req_line_reset <= 0;
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if(hb_in) req_line_reset <= 1;
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end
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end
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localparam AWIDTH = `BITS_TO_FIT(LENGTH);
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Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
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(
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.clk(clk_sys),
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.ce_x4(ce_x4),
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.inputpixel({b_d,g_d,r_d}),
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.mono(mono),
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.disable_hq2x(~hq2x),
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.reset_frame(vs_in),
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.reset_line(req_line_reset),
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.read_y(sd_line),
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.read_x(sd_h),
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.outpixel({b_out,g_out,r_out})
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);
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reg [10:0] sd_h;
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reg [1:0] sd_line;
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reg [2:0] vbo;
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reg [5:0] hbo;
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reg [DWIDTH:0] r_d;
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reg [DWIDTH:0] g_d;
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reg [DWIDTH:0] b_d;
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always @(posedge clk_sys) begin
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reg [11:0] hs_max,hs_rise;
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reg [10:0] hcnt;
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reg [11:0] sd_hcnt;
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reg [11:0] hde_start, hde_end;
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reg hs, hs2, vs, hb;
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if(ce_x1) begin
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hs <= hs_in;
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hb <= hb_in;
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r_d <= r_in;
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g_d <= g_in;
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b_d <= b_in;
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if(hb && !hb_in) begin
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hde_start <= {hcnt,1'b0};
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vbo <= {vbo[1:0], vb_in};
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end
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if(!hb && hb_in) hde_end <= {hcnt,1'b0};
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// falling edge of hsync indicates start of line
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if(hs && !hs_in) begin
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hs_max <= {hcnt,1'b1};
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hcnt <= 0;
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end else begin
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hcnt <= hcnt + 1'd1;
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end
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// save position of rising edge
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if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
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vs <= vs_in;
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if(vs && ~vs_in) sd_line <= 0;
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end
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if(ce_x4) begin
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hs2 <= hs_in;
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hbo[5:1] <= hbo[4:0];
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// output counter synchronous to input and at twice the rate
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sd_hcnt <= sd_hcnt + 1'd1;
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if(~&hbo) sd_h <= sd_h + 1'd1;
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if(hs2 && !hs_in) sd_hcnt <= hs_max;
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if(sd_hcnt == hs_max) sd_hcnt <= 0;
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//prepare to read in advance
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if(sd_hcnt == (hde_start-2)) begin
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sd_h <= 0;
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sd_line <= sd_line + 1'd1;
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end
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if(sd_hcnt == hde_start) hbo[0] <= 0;
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if(sd_hcnt == hde_end) hbo[0] <= 1;
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// replicate horizontal sync at twice the speed
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if(sd_hcnt == hs_max) hs_out <= 0;
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if(sd_hcnt == hs_rise) hs_out <= 1;
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end
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end
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endmodule
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