151 lines
4.7 KiB
VHDL
151 lines
4.7 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- Apple ][ Timing logic
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--
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-- Stephen A. Edwards, sedwards@cs.columbia.edu
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--
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-- Taken more-or-less verbatim from the schematics in the
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-- Apple ][ reference manual
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--
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-- This takes a 14.31818 MHz master clock and divides it down to generate
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-- the various lower-frequency signals (e.g., 7M, phase 0, colorburst)
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-- as well as horizontal and vertical blanking and sync signals for the video
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-- and the video addresses.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity timing_generator is
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port (
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CLK_14M : in std_logic; -- 14.31818 MHz master clock
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CLK_7M : buffer std_logic := '0';
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Q3 : buffer std_logic := '0'; -- 2 MHz signal in phase with PHI0
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RAS_N : buffer std_logic := '0';
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CAS_N : buffer std_logic := '0';
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AX : buffer std_logic := '0';
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PHI0 : buffer std_logic := '0'; -- 1.0 MHz processor clock
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PRE_PHI0 : buffer std_logic := '0'; -- One 14M cycle before
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COLOR_REF : buffer std_logic := '0'; -- 3.579545 MHz colorburst
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TEXT_MODE : in std_logic;
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PAGE2 : in std_logic;
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HIRES : in std_logic;
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VIDEO_ADDRESS : out unsigned(15 downto 0);
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H0 : out std_logic;
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VA : out std_logic; -- Character row address
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VB : out std_logic;
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VC : out std_logic;
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V2 : out std_logic;
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V4 : out std_logic;
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HBL : buffer std_logic; -- Horizontal blanking
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VBL : buffer std_logic; -- Vertical blanking
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BLANK : out std_logic; -- Composite blanking
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LDPS_N : out std_logic;
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LD194 : out std_logic
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);
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end timing_generator;
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architecture rtl of timing_generator is
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signal H : unsigned(6 downto 0) := "0000000";
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signal V : unsigned(8 downto 0) := "011111010";
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signal COLOR_DELAY_N : std_logic;
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begin
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-- To generate the once-a-line hiccup: D1 pin 6
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COLOR_DELAY_N <=
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not (not COLOR_REF and (not AX and not CAS_N) and PHI0 and not H(6));
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-- The DRAM signal generator
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C2_74S195: process (CLK_14M)
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begin
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if rising_edge(CLK_14M) then
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if Q3 = '1' then -- shift
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(Q3, CAS_N, AX, RAS_N) <=
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unsigned'(CAS_N, AX, RAS_N, '0');
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else -- load
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(Q3, CAS_N, AX, RAS_N) <=
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unsigned'(RAS_N, AX, COLOR_DELAY_N, AX);
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end if;
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end if;
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end process;
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-- The main clock signal generator
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B1_74S175 : process (CLK_14M)
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begin
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if rising_edge(CLK_14M) then
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COLOR_REF <= CLK_7M xor COLOR_REF;
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CLK_7M <= not CLK_7M;
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PHI0 <= PRE_PHI0;
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if AX = '1' then
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PRE_PHI0 <= not (Q3 xor PHI0); -- B1 pin 10
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end if;
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end if;
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end process;
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LDPS_N <= not (PHI0 and not AX and not CAS_N);
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LD194 <= not (PHI0 and not AX and not CAS_N and not CLK_7M);
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-- Four four-bit presettable binary counters
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-- Seven-bit horizontal counter counts 0, 40, 41, ..., 7F (65 states)
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-- Nine-bit vertical counter counts $FA .. $1FF (262 states)
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D11D12D13D14_74LS161 : process (CLK_14M)
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begin
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if rising_edge(CLK_14M) then
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-- True the cycle before the rising edge of LDPS_N: emulates
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-- the effects of using LDPS_N as the clock for the video counters
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if (PHI0 and not AX and ((Q3 and RAS_N) or
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(not Q3 and COLOR_DELAY_N))) = '1' then
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if H(6) = '0' then H <= "1000000";
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else
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H <= H + 1;
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if H = "1111111" then
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V <= V + 1;
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if V = "111111111" then V <= "011111010"; end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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H0 <= H(0);
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VA <= V(0);
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VB <= V(1);
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VC <= V(2);
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V2 <= V(5);
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V4 <= V(7);
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HBL <= not (H(5) or (H(3) and H(4)));
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VBL <= V(6) and V(7);
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BLANK <= HBL or VBL;
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-- V_SYNC <= VBL and V(5) and not V(4) and not V(3) and
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-- not V(2) and (H(4) or H(3) or H(5));
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-- H_SYNC <= HBL and H(3) and not H(2);
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-- SYNC <= not (V_SYNC or H_SYNC);
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-- COLOR_BURST <= HBL and H(2) and H(3) and (COLOR_REF or TEXT_MODE);
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-- Video address calculation
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VIDEO_ADDRESS(2 downto 0) <= H(2 downto 0);
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VIDEO_ADDRESS(6 downto 3) <= (not H(5) & V(6) & H(4) & H(3)) +
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( V(7) & not H(5) & V(7) & '1') +
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( "000" & V(6));
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VIDEO_ADDRESS(9 downto 7) <= V(5 downto 3);
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VIDEO_ADDRESS(14 downto 10) <=
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( "00" & HBL & PAGE2 & not PAGE2) when HIRES = '0' else
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(PAGE2 & not PAGE2 & V(2 downto 0));
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VIDEO_ADDRESS(15) <= '0';
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end rtl;
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