222 lines
6.9 KiB
VHDL
222 lines
6.9 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- Apple ][ Video Generation Logic
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--
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-- Stephen A. Edwards, sedwards@cs.columbia.edu
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--
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-- This takes data from memory and various mode switches to produce the
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-- serial one-bit video data stream.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity video_generator is
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port (
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CLK_14M : in std_logic; -- 14.31818 MHz master clock
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CLK_7M : in std_logic;
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AX : in std_logic;
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CAS_N : in std_logic;
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TEXT_MODE : in std_logic;
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PAGE2 : in std_logic;
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HIRES_MODE : in std_logic;
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MIXED_MODE : in std_logic;
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H0 : in std_logic;
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VA : in std_logic;
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VB : in std_logic;
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VC : in std_logic;
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V2 : in std_logic;
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V4 : in std_logic;
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BLANK : in std_logic;
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DL : in unsigned(7 downto 0); -- Data from RAM
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LDPS_N : in std_logic;
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LD194 : in std_logic;
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FLASH_CLK : in std_logic; -- Low-frequency flashing text clock
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HIRES : out std_logic;
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VIDEO : out std_logic;
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COLOR_LINE : out std_logic
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);
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end video_generator;
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architecture rtl of video_generator is
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signal char_rom_addr : unsigned(8 downto 0);
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signal char_rom_out : unsigned(4 downto 0);
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signal text_shiftreg : unsigned(5 downto 0);
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signal invert_character : std_logic;
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signal text_pixel : std_logic; -- B2 p11
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signal blank_delayed : std_logic;
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signal video_sig : std_logic; -- output of B10 p5
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signal graph_shiftreg : unsigned(7 downto 0);
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signal graphics_time_1, graphics_time_2,
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graphics_time_3 : std_logic; -- B5 p2, B8 p15, B8 p2
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signal lores_time : std_logic; -- A11 p6
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signal pixel_select : std_logic_vector(1 downto 0); -- A10 p14, A10 p15
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signal hires_delayed : std_logic; -- A11 p9
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begin
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-----------------------------------------------------------------------------
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--
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-- Text Mode Circuitry
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--
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-- The character ROM drives a parallel-to-serial shift register
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-- whose output is selectively inverted by inverted or flashing text
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--
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-----------------------------------------------------------------------------
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char_rom_addr <= DL(5 downto 0) & VC & VB & VA;
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thecharrom : entity work.character_rom
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port map(
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addr => char_rom_addr,
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clk => CLK_14M, -- FIXME: a lower frequency?
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dout => char_rom_out
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);
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-- Parallel-to-serial shifter for text mode
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-- The Apple actually used LDPS_N as the clock, not 14M; this is equivalent
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A3_74166: process (CLK_14M)
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begin
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if rising_edge(CLK_14M) then
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if CLK_7M = '0' then
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if LDPS_N = '0' then -- load
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text_shiftreg <= char_rom_out & "0";
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else -- shift
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text_shiftreg <= '0' & text_shiftreg(5 downto 1);
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end if;
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end if;
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end if;
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end process;
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-- Latch and decoder for flashing/inverted text
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-- Comprises part of B11, B13, and A10
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flash_invert : process (CLK_14M)
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begin
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if rising_edge(CLK_14M) then
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if LD194 = '0' then
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invert_character <= not (DL(7) or (DL(6) and FLASH_CLK));
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end if;
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end if;
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end process;
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text_pixel <= text_shiftreg(0) xor invert_character;
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-----------------------------------------------------------------------------
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--
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-- Lores and Hires Mode Circuitry
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--
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-- An eight-bit shift register that either shifts (hires mode) or rotates
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-- the two nibbles (lores) followed by a mux that selects the video
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-- data from the text mode display, the hires shift register (possibly
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-- delayed by a 14M clock pulse), or one of the bits in the lores shift
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-- register.
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--
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-----------------------------------------------------------------------------
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-- Original Apple clocked this shift register on the rising edge of RAS_N
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B5B8_74LS174 : process (CLK_14M)
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begin
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if rising_edge(CLK_14M) then
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if AX = '1' and CAS_N = '0' then
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graphics_time_3 <= graphics_time_2;
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graphics_time_2 <= graphics_time_1;
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graphics_time_1 <= not (TEXT_MODE or (V2 and V4 and MIXED_MODE));
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end if;
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end if;
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end process;
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COLOR_LINE <= graphics_time_1;
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HIRES <= HIRES_MODE and graphics_time_3; -- to address generator
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lores_time <= not HIRES_MODE and graphics_time_3;
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A8A10_74LS194 : process (CLK_14M)
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begin
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if rising_edge(CLK_14M) then
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if LD194 = '0' then
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if lores_time = '1' then -- LORES mode
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pixel_select <= VC & H0;
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else -- HIRES mode
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pixel_select <= graphics_time_1 & DL(7);
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end if;
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end if;
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end if;
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end process;
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-- Shift hires pixels by one 14M cycle to get orange and blue
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A11_74LS74 : process (CLK_14M)
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begin
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if rising_edge(CLK_14M) then
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hires_delayed <= graph_shiftreg(0);
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end if;
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end process;
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-- A pair of four-bit universal shift registers that either
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-- shift the whole byte (hires mode) or rotate the two nibbles (lores mode)
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B4B9_74LS194 : process (CLK_14M)
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begin
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if rising_edge(CLK_14M) then
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if LD194 = '0' then
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graph_shiftreg <= DL;
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else
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if lores_time = '1' then -- LORES configuration
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graph_shiftreg <= graph_shiftreg(4) & graph_shiftreg(7 downto 5) &
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graph_shiftreg(0) & graph_shiftreg(3 downto 1);
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else -- HIRES configuration
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if CLK_7M = '0' then
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graph_shiftreg <= graph_shiftreg(4) & graph_shiftreg(7 downto 1);
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end if;
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end if;
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end if;
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end if;
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end process;
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-- Synchronize BLANK to LD194
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A10_74LS194: process (CLK_14M)
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begin
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if rising_edge(CLK_14M) then
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if LD194 = '0' then
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blank_delayed <= BLANK;
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end if;
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end if;
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end process;
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-- Video output mux and flip-flop
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A9B10_74LS151 : process (CLK_14M)
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begin
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if rising_edge(CLK_14M) then
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if blank_delayed = '0' then
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if lores_time = '1' then -- LORES mode
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case pixel_select is
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when "00" => video_sig <= graph_shiftreg(0);
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when "01" => video_sig <= graph_shiftreg(2);
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when "10" => video_sig <= graph_shiftreg(4);
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when "11" => video_sig <= graph_shiftreg(6);
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when others => video_sig <= 'X';
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end case;
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else
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if pixel_select(1) = '0' then -- TEXT mode
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video_sig <= text_pixel;
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else -- HIRES mode
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if pixel_select(0) = '1' then
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video_sig <= hires_delayed;
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else
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video_sig <= graph_shiftreg(0);
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end if;
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end if;
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end if;
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else
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video_sig <= '0';
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end if;
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end if;
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end process;
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VIDEO <= video_sig;
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end rtl;
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