86 lines
1.8 KiB
Verilog
86 lines
1.8 KiB
Verilog
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module i2s
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#(
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parameter CLK_RATE = 50000000,
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parameter AUDIO_DW = 16,
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parameter AUDIO_RATE = 96000
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)
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(
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input reset,
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input clk_sys,
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input half_rate,
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output reg sclk,
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output reg lrclk,
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output reg sdata,
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input [AUDIO_DW-1:0] left_chan,
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input [AUDIO_DW-1:0] right_chan
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);
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localparam WHOLE_CYCLES = (CLK_RATE) / (AUDIO_RATE*AUDIO_DW*4);
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localparam ERROR_BASE = 10000;
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localparam [63:0] ERRORS_PER_BIT = ((CLK_RATE * ERROR_BASE) / (AUDIO_RATE*AUDIO_DW*4)) - (WHOLE_CYCLES * ERROR_BASE);
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always @(posedge clk_sys) begin
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reg [31:0] count_q;
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reg [31:0] error_q;
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reg [7:0] bit_cnt;
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reg [AUDIO_DW-1:0] left;
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reg [AUDIO_DW-1:0] right;
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reg msclk;
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reg ce;
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if (reset) begin
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count_q <= 0;
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error_q <= 0;
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ce <= 0;
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bit_cnt <= 1;
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lrclk <= 1;
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sclk <= 1;
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msclk <= 1;
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end
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else
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begin
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if(count_q == WHOLE_CYCLES-1) begin
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if (error_q < (ERROR_BASE - ERRORS_PER_BIT)) begin
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error_q <= error_q + ERRORS_PER_BIT[31:0];
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count_q <= 0;
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end else begin
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error_q <= error_q + ERRORS_PER_BIT[31:0] - ERROR_BASE;
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count_q <= count_q + 1;
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end
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end else if(count_q == WHOLE_CYCLES) begin
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count_q <= 0;
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end else begin
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count_q <= count_q + 1;
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end
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sclk <= msclk;
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if(!count_q) begin
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ce <= ~ce;
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if(~half_rate || ce) begin
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msclk <= ~msclk;
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if(msclk) begin
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if(bit_cnt >= AUDIO_DW) begin
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bit_cnt <= 1;
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lrclk <= ~lrclk;
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if(lrclk) begin
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left <= left_chan;
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right <= right_chan;
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end
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end
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else begin
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bit_cnt <= bit_cnt + 1'd1;
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end
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sdata <= lrclk ? right[AUDIO_DW - bit_cnt] : left[AUDIO_DW - bit_cnt];
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end
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end
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end
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end
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end
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endmodule
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