61 lines
2.2 KiB
Verilog
61 lines
2.2 KiB
Verilog
// avalon_combiner.v
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`timescale 1 ps / 1 ps
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module avalon_combiner
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(
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input wire clk, // clock.clk
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input wire rst, // reset.reset
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output wire [6:0] mixer_address, // ctl_mixer.address
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output wire [3:0] mixer_byteenable, // .byteenable
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output wire mixer_write, // .write
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output wire [31:0] mixer_writedata, // .writedata
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input wire mixer_waitrequest, // .waitrequest
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output wire [6:0] scaler_address, // ctl_scaler.address
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output wire [3:0] scaler_byteenable, // .byteenable
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input wire scaler_waitrequest, // .waitrequest
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output wire scaler_write, // .write
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output wire [31:0] scaler_writedata, // .writedata
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output wire [7:0] video_address, // ctl_video.address
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output wire [3:0] video_byteenable, // .byteenable
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input wire video_waitrequest, // .waitrequest
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output wire video_write, // .write
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output wire [31:0] video_writedata, // .writedata
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output wire clock, // control.clock
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output wire reset, // .reset
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input wire [8:0] address, // .address
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input wire write, // .write
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input wire [31:0] writedata, // .writedata
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output wire waitrequest // .waitrequest
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);
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assign clock = clk;
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assign reset = rst;
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assign mixer_address = address[6:0];
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assign scaler_address = address[6:0];
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assign video_address = address[7:0];
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assign mixer_byteenable = 4'b1111;
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assign scaler_byteenable = 4'b1111;
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assign video_byteenable = 4'b1111;
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wire en_scaler = (address[8:7] == 0);
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wire en_mixer = (address[8:7] == 1);
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wire en_video = address[8];
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assign mixer_write = en_mixer & write;
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assign scaler_write = en_scaler & write;
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assign video_write = en_video & write;
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assign mixer_writedata = writedata;
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assign scaler_writedata = writedata;
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assign video_writedata = writedata;
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assign waitrequest = (en_mixer & mixer_waitrequest) | (en_scaler & scaler_waitrequest) | (en_video & video_waitrequest);
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endmodule
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