101 lines
3.0 KiB
Systemverilog
101 lines
3.0 KiB
Systemverilog
// low pass filter
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// Revision 1.00
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//
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// Copyright (c) 2008 Takayuki Hara.
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// All rights reserved.
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//
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// Redistribution and use of this source code or any derivative works, are
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// permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// 3. Redistributions may not be sold, nor may they be used in a commercial
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// product or activity without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// LPF (cut off 48kHz at 3.58MHz)
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module lpf48k #(parameter MSB = 15)
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(
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input RESET,
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input CLK,
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input CE,
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input ENABLE,
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input [MSB:0] IDATA,
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output [MSB:0] ODATA
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);
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wire [7:0] LPF_TAP_DATA[0:71] =
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'{
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8'h51, 8'h07, 8'h07, 8'h08, 8'h08, 8'h08, 8'h09, 8'h09,
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8'h09, 8'h0A, 8'h0A, 8'h0A, 8'h0A, 8'h0B, 8'h0B, 8'h0B,
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8'h0B, 8'h0C, 8'h0C, 8'h0C, 8'h0C, 8'h0D, 8'h0D, 8'h0D,
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8'h0D, 8'h0D, 8'h0D, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E,
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8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E,
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8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0E, 8'h0D, 8'h0D, 8'h0D,
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8'h0D, 8'h0D, 8'h0D, 8'h0C, 8'h0C, 8'h0C, 8'h0C, 8'h0B,
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8'h0B, 8'h0B, 8'h0B, 8'h0A, 8'h0A, 8'h0A, 8'h0A, 8'h09,
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8'h09, 8'h09, 8'h08, 8'h08, 8'h08, 8'h07, 8'h07, 8'h51
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};
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reg [7:0] FF_ADDR = 0;
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reg [MSB+10:0] FF_INTEG = 0;
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wire [MSB+8:0] W_DATA;
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wire W_ADDR_END;
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assign W_ADDR_END = ((FF_ADDR == 71));
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reg [MSB:0] OUT;
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assign ODATA = ENABLE ? OUT : IDATA;
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always @(posedge RESET or posedge CLK) begin
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if (RESET) FF_ADDR <= 0;
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else
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begin
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if (CE) begin
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if (W_ADDR_END) FF_ADDR <= 0;
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else FF_ADDR <= FF_ADDR + 1'd1;
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end
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end
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end
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assign W_DATA = LPF_TAP_DATA[FF_ADDR] * IDATA;
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always @(posedge RESET or posedge CLK) begin
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if (RESET) FF_INTEG <= 0;
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else
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begin
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if (CE) begin
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if (W_ADDR_END) FF_INTEG <= 0;
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else FF_INTEG <= FF_INTEG + W_DATA;
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end
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end
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end
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always @(posedge RESET or posedge CLK) begin
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if (RESET) OUT <= 0;
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else
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begin
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if (CE && W_ADDR_END) OUT <= FF_INTEG[MSB + 10:10];
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end
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end
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endmodule
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