169 lines
3.7 KiB
Verilog
169 lines
3.7 KiB
Verilog
// A simple OSD implementation. Can be hooked up between a cores
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// VGA output and the physical VGA pins
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module osd
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(
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input clk_sys,
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input io_osd,
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input io_strobe,
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input [7:0] io_din,
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input clk_video,
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input [23:0] din,
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output [23:0] dout,
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input de
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);
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parameter OSD_COLOR = 3'd4;
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parameter OSD_X_OFFSET = 12'd0;
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parameter OSD_Y_OFFSET = 12'd0;
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localparam OSD_WIDTH = 12'd256;
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localparam OSD_HEIGHT = 12'd64;
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// this core supports only the display related OSD commands
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// of the minimig v1
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reg osd_enable;
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(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[4096]; // the OSD buffer itself
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reg highres = 0;
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// the OSD has its own SPI interface to the io controller
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always@(posedge clk_sys) begin
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reg [11:0] bcnt;
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reg [7:0] cmd;
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reg has_cmd;
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reg old_strobe;
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old_strobe <= io_strobe;
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if(~io_osd) begin
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bcnt <= 0;
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has_cmd <= 0;
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end else begin
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if(~old_strobe & io_strobe) begin
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if(!has_cmd) begin
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has_cmd <= 1;
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cmd <= io_din;
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// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
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if(io_din[7:4] == 4'b0100) begin
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osd_enable <= io_din[0];
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if(!io_din[0]) highres <= 0;
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end
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bcnt <= {io_din[3:0], 8'h00};
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if(io_din[7:3] == 5'b00101) highres <= 1;
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end else begin
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// command 0x20: OSDCMDWRITE
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if(cmd[7:4] == 4'b0010) begin
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osd_buffer[bcnt] <= io_din;
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bcnt <= bcnt + 1'd1;
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end
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end
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end
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end
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end
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reg ce_pix;
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always @(negedge clk_video) begin
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integer cnt = 0;
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integer pixsz, pixcnt;
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reg deD;
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cnt <= cnt + 1;
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deD <= de;
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pixcnt <= pixcnt + 1;
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if(pixcnt == pixsz) pixcnt <= 0;
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ce_pix <= !pixcnt;
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if(~deD && de) cnt <= 0;
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if(deD && ~de) begin
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pixsz <= (((cnt+1'b1) >> 9) > 1) ? (((cnt+1'b1) >> 9) - 1) : 0;
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pixcnt <= 0;
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end
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end
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reg [23:0] h_cnt;
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reg [21:0] v_cnt;
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reg [21:0] dsp_width;
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reg [21:0] dsp_height;
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reg [7:0] osd_byte;
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reg [21:0] osd_vcnt;
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reg [21:0] fheight;
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wire [21:0] hrheight = (OSD_HEIGHT<<highres);
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always @(posedge clk_video) begin
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reg deD;
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reg [1:0] osd_div;
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reg [1:0] multiscan;
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if(ce_pix) begin
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deD <= de;
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if(~&h_cnt) h_cnt <= h_cnt + 1'd1;
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// falling edge of de
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if(!de && deD) dsp_width <= h_cnt[21:0];
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// rising edge of de
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if(de && !deD) begin
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v_cnt <= v_cnt + 1'd1;
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if(h_cnt > {dsp_width, 2'b00}) begin
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v_cnt <= 0;
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dsp_height <= v_cnt;
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if(v_cnt<320) begin
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multiscan <= 0;
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fheight <= hrheight;
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end
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else if(v_cnt<640) begin
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multiscan <= 1;
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fheight <= hrheight << 1;
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end
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else if(v_cnt<960) begin
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multiscan <= 2;
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fheight <= hrheight + (hrheight<<1);
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end
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else begin
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multiscan <= 3;
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fheight <= hrheight << 2;
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end
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end
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h_cnt <= 0;
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osd_div <= osd_div + 1'd1;
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if(osd_div == multiscan) begin
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osd_div <= 0;
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osd_vcnt <= osd_vcnt + 1'd1;
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end
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if(v_osd_start == (v_cnt+1'b1)) {osd_div, osd_vcnt} <= 0;
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end
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osd_byte <= osd_buffer[{osd_vcnt[6:3], osd_hcnt[7:0]}];
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end
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end
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// area in which OSD is being displayed
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wire [21:0] h_osd_start = ((dsp_width - OSD_WIDTH)>>1) + OSD_X_OFFSET;
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wire [21:0] h_osd_end = h_osd_start + OSD_WIDTH;
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wire [21:0] v_osd_start = ((dsp_height- fheight)>>1) + OSD_Y_OFFSET;
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wire [21:0] v_osd_end = v_osd_start + fheight;
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wire [21:0] osd_hcnt = h_cnt[21:0] - h_osd_start + 1'd1;
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wire osd_de = osd_enable &&
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(h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
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(v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
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wire osd_pixel = osd_byte[osd_vcnt[2:0]];
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assign dout = !osd_de ? din : {{osd_pixel, osd_pixel, OSD_COLOR[2], din[23:19]},
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{osd_pixel, osd_pixel, OSD_COLOR[1], din[15:11]},
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{osd_pixel, osd_pixel, OSD_COLOR[0], din[7:3]}};
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endmodule
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