121 lines
2.8 KiB
Verilog
121 lines
2.8 KiB
Verilog
module pattern_vg
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#(
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parameter B=8, // number of bits per channel
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X_BITS=13,
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Y_BITS=13,
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FRACTIONAL_BITS = 12
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)
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(
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input reset, clk_in,
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input wire [X_BITS-1:0] x,
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input wire [Y_BITS-1:0] y,
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input wire vn_in, hn_in, dn_in,
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input wire [B-1:0] r_in, g_in, b_in,
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output reg vn_out, hn_out, den_out,
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output reg [B-1:0] r_out, g_out, b_out,
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input wire [X_BITS-1:0] total_active_pix,
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input wire [Y_BITS-1:0] total_active_lines,
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input wire [7:0] pattern,
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input wire [B+FRACTIONAL_BITS-1:0] ramp_step
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);
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reg [B+FRACTIONAL_BITS-1:0] ramp_values; // 12-bit fractional end for ramp values
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//wire bar_0 = y<90;
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wire bar_1 = y>=90 & y<180;
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wire bar_2 = y>=180 & y<270;
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wire bar_3 = y>=270 & y<360;
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wire bar_4 = y>=360 & y<450;
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wire bar_5 = y>=450 & y<540;
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wire bar_6 = y>=540 & y<630;
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wire bar_7 = y>=630 & y<720;
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wire red_enable = bar_1 | bar_3 | bar_5 | bar_7;
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wire green_enable = bar_2 | bar_3 | bar_6 | bar_7;
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wire blue_enable = bar_4 | bar_5 | bar_6 | bar_7;
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always @(posedge clk_in)
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begin
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vn_out <= vn_in;
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hn_out <= hn_in;
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den_out <= dn_in;
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if (reset)
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ramp_values <= 0;
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else if (pattern == 8'b0) // no pattern
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begin
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r_out <= r_in;
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g_out <= g_in;
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b_out <= b_in;
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end
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else if (pattern == 8'b1) // border
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begin
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if (dn_in && ((y == 12'b0) || (x == 12'b0) || (x == total_active_pix - 1) || (y == total_active_lines - 1)))
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begin
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r_out <= 8'hFF;
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g_out <= 8'hFF;
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b_out <= 8'hFF;
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end
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else // Double-border (OzOnE)...
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if (dn_in && ((y == 12'b0+20) || (x == 12'b0+20) || (x == total_active_pix - 1 - 20) || (y == total_active_lines - 1 - 20)))
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begin
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r_out <= 8'hD0;
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g_out <= 8'hB0;
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b_out <= 8'hB0;
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end
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else
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begin
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r_out <= r_in;
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g_out <= g_in;
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b_out <= b_in;
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end
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end
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else if (pattern == 8'd2) // moireX
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begin
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if ((dn_in) && x[0] == 1'b1)
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begin
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r_out <= 8'hFF;
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g_out <= 8'hFF;
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b_out <= 8'hFF;
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end
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else
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begin
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r_out <= 8'b0;
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g_out <= 8'b0;
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b_out <= 8'b0;
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end
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end
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else if (pattern == 8'd3) // moireY
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begin
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if ((dn_in) && y[0] == 1'b1)
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begin
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r_out <= 8'hFF;
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g_out <= 8'hFF;
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b_out <= 8'hFF;
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end
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else
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begin
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r_out <= 8'b0;
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g_out <= 8'b0;
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b_out <= 8'b0;
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end
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end
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else if (pattern == 8'd4) // Simple RAMP
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begin
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r_out <= (red_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
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g_out <= (green_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
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b_out <= (blue_enable) ? ramp_values[B+FRACTIONAL_BITS-1:FRACTIONAL_BITS] : 8'h00;
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if ((x == total_active_pix - 1) && (dn_in))
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ramp_values <= 0;
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else if ((x == 0) && (dn_in))
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ramp_values <= ramp_step;
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else if (dn_in)
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ramp_values <= ramp_values + ramp_step;
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end
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end
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endmodule
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