91 lines
2.2 KiB
Verilog
91 lines
2.2 KiB
Verilog
`timescale 1ns/10ps
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module pll_0002(
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// interface 'refclk'
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input wire refclk,
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// interface 'reset'
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input wire rst,
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// interface 'outclk0'
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output wire outclk_0,
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// interface 'outclk1'
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output wire outclk_1,
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// interface 'locked'
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output wire locked
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);
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altera_pll #(
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.fractional_vco_multiplier("false"),
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.reference_clock_frequency("50.0 MHz"),
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.operation_mode("direct"),
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.number_of_clocks(2),
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.output_clock_frequency0("28.000000 MHz"),
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.phase_shift0("0 ps"),
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.duty_cycle0(50),
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.output_clock_frequency1("14.000000 MHz"),
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.phase_shift1("5000 ps"),
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.duty_cycle1(50),
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.output_clock_frequency2("0 MHz"),
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.phase_shift2("0 ps"),
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.duty_cycle2(50),
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.output_clock_frequency3("0 MHz"),
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.phase_shift3("0 ps"),
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.duty_cycle3(50),
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.output_clock_frequency4("0 MHz"),
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.phase_shift4("0 ps"),
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.duty_cycle4(50),
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.output_clock_frequency5("0 MHz"),
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.phase_shift5("0 ps"),
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.duty_cycle5(50),
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.output_clock_frequency6("0 MHz"),
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.phase_shift6("0 ps"),
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.duty_cycle6(50),
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.output_clock_frequency7("0 MHz"),
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.phase_shift7("0 ps"),
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.duty_cycle7(50),
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.output_clock_frequency8("0 MHz"),
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.phase_shift8("0 ps"),
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.duty_cycle8(50),
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.output_clock_frequency9("0 MHz"),
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.phase_shift9("0 ps"),
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.duty_cycle9(50),
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.output_clock_frequency10("0 MHz"),
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.phase_shift10("0 ps"),
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.duty_cycle10(50),
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.output_clock_frequency11("0 MHz"),
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.phase_shift11("0 ps"),
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.duty_cycle11(50),
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.output_clock_frequency12("0 MHz"),
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.phase_shift12("0 ps"),
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.duty_cycle12(50),
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.output_clock_frequency13("0 MHz"),
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.phase_shift13("0 ps"),
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.duty_cycle13(50),
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.output_clock_frequency14("0 MHz"),
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.phase_shift14("0 ps"),
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.duty_cycle14(50),
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.output_clock_frequency15("0 MHz"),
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.phase_shift15("0 ps"),
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.duty_cycle15(50),
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.output_clock_frequency16("0 MHz"),
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.phase_shift16("0 ps"),
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.duty_cycle16(50),
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.output_clock_frequency17("0 MHz"),
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.phase_shift17("0 ps"),
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.duty_cycle17(50),
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.pll_type("General"),
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.pll_subtype("General")
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) altera_pll_i (
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.rst (rst),
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.outclk ({outclk_1, outclk_0}),
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.locked (locked),
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.fboutclk ( ),
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.fbclk (1'b0),
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.refclk (refclk)
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);
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endmodule
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