263 lines
9.1 KiB
Systemverilog
263 lines
9.1 KiB
Systemverilog
//
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// sdram.v
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//
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// Static RAM controller implementation using SDRAM MT48LC16M16A2
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//
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// Copyright (c) 2015,2016 Sorgelig
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//
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// Some parts of SDRAM code used from project:
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// http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ------------------------------------------
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//
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// v2.1 - Add universal 8/16 bit mode.
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//
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module sdram
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(
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input init, // reset to initialize RAM
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input clk, // clock ~100MHz
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//
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// SDRAM_* - signals to the MT48LC16M16 chip
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inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
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output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
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output reg SDRAM_DQML, // two byte masks
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output reg SDRAM_DQMH, //
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output reg [1:0] SDRAM_BA, // two banks
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output SDRAM_nCS, // a single chip select
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output SDRAM_nWE, // write enable
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output SDRAM_nRAS, // row address select
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output SDRAM_nCAS, // columns address select
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output SDRAM_CKE, // clock enable
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//
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input [1:0] wtbt, // 16bit mode: bit1 - write high byte, bit0 - write low byte,
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// 8bit mode: 2'b00 - use addr[0] to decide which byte to write
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// Ignored while reading.
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//
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input [24:0] addr, // 25 bit address for 8bit mode. addr[0] = 0 for 16bit mode for correct operations.
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output [15:0] dout, // data output to cpu
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input [15:0] din, // data input from cpu
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input we, // cpu requests write
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input rd, // cpu requests read
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output reg ready // dout is valid. Ready to accept new read/write.
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);
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assign SDRAM_nCS = command[3];
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assign SDRAM_nRAS = command[2];
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assign SDRAM_nCAS = command[1];
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assign SDRAM_nWE = command[0];
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assign SDRAM_CKE = cke;
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assign dout = latched ? data_l : data_d;
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// no burst configured
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localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
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localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
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localparam CAS_LATENCY = 3'd2; // 2 for < 100MHz, 3 for >100MHz
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localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
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localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
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localparam MODE = {3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
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localparam sdram_startup_cycles= 14'd12100;// 100us, plus a little more, @ 100MHz
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localparam cycles_per_refresh = 14'd780; // (64000*100)/8192-1 Calc'd as (64ms @ 100MHz)/8192 rose
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localparam startup_refresh_max = 14'b11111111111111;
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// SDRAM commands
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localparam CMD_INHIBIT = 4'b1111;
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localparam CMD_NOP = 4'b0111;
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localparam CMD_ACTIVE = 4'b0011;
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localparam CMD_READ = 4'b0101;
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localparam CMD_WRITE = 4'b0100;
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localparam CMD_BURST_TERMINATE = 4'b0110;
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localparam CMD_PRECHARGE = 4'b0010;
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localparam CMD_AUTO_REFRESH = 4'b0001;
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localparam CMD_LOAD_MODE = 4'b0000;
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reg [13:0] refresh_count = startup_refresh_max - sdram_startup_cycles;
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reg [3:0] command = CMD_INHIBIT;
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reg cke = 0;
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reg [24:0] save_addr;
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reg latched;
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reg [15:0] data;
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wire[15:0] data_l = save_addr[0] ? {data[7:0], data[15:8]} : {data[15:8], data[7:0]};
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wire[15:0] data_d = save_addr[0] ? {SDRAM_DQ[7:0], SDRAM_DQ[15:8]} : {SDRAM_DQ[15:8], SDRAM_DQ[7:0]};
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typedef enum
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{
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STATE_STARTUP,
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STATE_OPEN_1, STATE_OPEN_2,
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STATE_WRITE,
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STATE_READ,
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STATE_IDLE, STATE_IDLE_1, STATE_IDLE_2, STATE_IDLE_3,
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STATE_IDLE_4, STATE_IDLE_5, STATE_IDLE_6, STATE_IDLE_7
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} state_t;
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always @(posedge clk) begin
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reg old_we, old_rd;
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reg [CAS_LATENCY:0] data_ready_delay;
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reg [15:0] new_data;
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reg [1:0] new_wtbt;
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reg new_we;
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reg new_rd;
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reg save_we = 1;
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state_t state = STATE_STARTUP;
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command <= CMD_NOP;
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refresh_count <= refresh_count+1'b1;
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data_ready_delay <= {1'b0, data_ready_delay[CAS_LATENCY:1]};
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// make it ready 1T in advance
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if(data_ready_delay[1]) {latched, ready} <= {1'b0, 1'b1};
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if(data_ready_delay[0]) {latched, data} <= {1'b1, SDRAM_DQ};
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case(state)
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STATE_STARTUP: begin
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//------------------------------------------------------------------------
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//-- This is the initial startup state, where we wait for at least 100us
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//-- before starting the start sequence
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//--
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//-- The initialisation is sequence is
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//-- * de-assert SDRAM_CKE
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//-- * 100us wait,
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//-- * assert SDRAM_CKE
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//-- * wait at least one cycle,
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//-- * PRECHARGE
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//-- * wait 2 cycles
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//-- * REFRESH,
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//-- * tREF wait
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//-- * REFRESH,
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//-- * tREF wait
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//-- * LOAD_MODE_REG
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//-- * 2 cycles wait
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//------------------------------------------------------------------------
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cke <= 1;
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SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
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SDRAM_DQML <= 1;
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SDRAM_DQMH <= 1;
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SDRAM_A <= 0;
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SDRAM_BA <= 0;
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// All the commands during the startup are NOPS, except these
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if(refresh_count == startup_refresh_max-31) begin
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// ensure all rows are closed
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command <= CMD_PRECHARGE;
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SDRAM_A[10] <= 1; // all banks
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SDRAM_BA <= 2'b00;
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end else if (refresh_count == startup_refresh_max-23) begin
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// these refreshes need to be at least tREF (66ns) apart
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command <= CMD_AUTO_REFRESH;
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end else if (refresh_count == startup_refresh_max-15)
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command <= CMD_AUTO_REFRESH;
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else if (refresh_count == startup_refresh_max-7) begin
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// Now load the mode register
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command <= CMD_LOAD_MODE;
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SDRAM_A <= MODE;
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end
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//------------------------------------------------------
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//-- if startup is complete then go into idle mode,
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//-- get prepared to accept a new command, and schedule
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//-- the first refresh cycle
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//------------------------------------------------------
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if(!refresh_count) begin
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state <= STATE_IDLE;
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ready <= 1;
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refresh_count <= 0;
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end
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end
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STATE_IDLE_7: state <= STATE_IDLE_6;
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STATE_IDLE_6: state <= STATE_IDLE_5;
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STATE_IDLE_5: state <= STATE_IDLE_4;
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STATE_IDLE_4: state <= STATE_IDLE_3;
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STATE_IDLE_3: state <= STATE_IDLE_2;
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STATE_IDLE_2: state <= STATE_IDLE_1;
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STATE_IDLE_1: begin
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SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
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state <= STATE_IDLE;
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// mask possible refresh to reduce colliding.
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if(refresh_count > cycles_per_refresh) begin
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//------------------------------------------------------------------------
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//-- Start the refresh cycle.
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//-- This tasks tRFC (66ns), so 6 idle cycles are needed @ 100MHz
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//------------------------------------------------------------------------
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state <= STATE_IDLE_7;
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command <= CMD_AUTO_REFRESH;
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refresh_count <= refresh_count - cycles_per_refresh + 1'd1;
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end
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end
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STATE_IDLE: begin
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// Priority is to issue a refresh if one is outstanding
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if(refresh_count > (cycles_per_refresh<<1)) state <= STATE_IDLE_1;
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else if(new_rd | new_we) begin
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new_we <= 0;
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new_rd <= 0;
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save_addr<= addr;
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save_we <= new_we;
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state <= STATE_OPEN_1;
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command <= CMD_ACTIVE;
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SDRAM_A <= addr[13:1];
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SDRAM_BA <= addr[24:23];
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end
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end
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// ACTIVE-to-READ or WRITE delay >20ns (-75)
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STATE_OPEN_1: state <= STATE_OPEN_2;
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STATE_OPEN_2: begin
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SDRAM_A <= {4'b0010, save_addr[22:14]};
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SDRAM_DQML <= save_we & (new_wtbt ? ~new_wtbt[0] : save_addr[0]);
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SDRAM_DQMH <= save_we & (new_wtbt ? ~new_wtbt[1] : ~save_addr[0]);
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state <= save_we ? STATE_WRITE : STATE_READ;
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end
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STATE_READ: begin
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state <= STATE_IDLE_5;
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command <= CMD_READ;
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SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
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// Schedule reading the data values off the bus
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data_ready_delay[CAS_LATENCY] <= 1;
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end
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STATE_WRITE: begin
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state <= STATE_IDLE_5;
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command <= CMD_WRITE;
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SDRAM_DQ <= new_wtbt ? new_data : {new_data[7:0], new_data[7:0]};
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ready <= 1;
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end
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endcase
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if(init) begin
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state <= STATE_STARTUP;
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refresh_count <= startup_refresh_max - sdram_startup_cycles;
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end
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old_we <= we;
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if(we & ~old_we) {ready, new_we, new_data, new_wtbt} <= {1'b0, 1'b1, din, wtbt};
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old_rd <= rd;
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if(rd & ~old_rd) begin
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if(ready & ~save_we & (save_addr[24:1] == addr[24:1])) save_addr <= addr;
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else {ready, new_rd} <= {1'b0, 1'b1};
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end
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end
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endmodule
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