124 lines
3.0 KiB
Verilog
124 lines
3.0 KiB
Verilog
module sync_vg
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#(
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parameter X_BITS=12,
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Y_BITS=12
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)
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(
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input wire clk,
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input wire reset,
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input wire interlaced,
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input wire [Y_BITS-1:0] v_total_0,
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input wire [Y_BITS-1:0] v_fp_0,
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input wire [Y_BITS-1:0] v_bp_0,
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input wire [Y_BITS-1:0] v_sync_0,
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input wire [Y_BITS-1:0] v_total_1,
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input wire [Y_BITS-1:0] v_fp_1,
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input wire [Y_BITS-1:0] v_bp_1,
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input wire [Y_BITS-1:0] v_sync_1,
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input wire [X_BITS-1:0] h_total,
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input wire [X_BITS-1:0] h_fp,
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input wire [X_BITS-1:0] h_bp,
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input wire [X_BITS-1:0] h_sync,
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input wire [X_BITS-1:0] hv_offset_0,
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input wire [X_BITS-1:0] hv_offset_1,
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output reg vs_out,
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output reg hs_out,
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output reg hde_out,
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output reg vde_out,
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output reg [Y_BITS:0] v_count_out,
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output reg [X_BITS-1:0] h_count_out,
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output reg [X_BITS-1:0] x_out,
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output reg [Y_BITS:0] y_out,
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output reg field_out,
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output wire clk_out
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);
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reg [X_BITS-1:0] h_count;
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reg [Y_BITS-1:0] v_count;
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reg field;
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reg [Y_BITS-1:0] v_total;
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reg [Y_BITS-1:0] v_fp;
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reg [Y_BITS-1:0] v_bp;
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reg [Y_BITS-1:0] v_sync;
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reg [X_BITS-1:0] hv_offset;
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assign clk_out = !clk;
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/* horizontal counter */
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always @(posedge clk)
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if (reset)
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h_count <= 0;
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else
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if (h_count < h_total - 1)
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h_count <= h_count + 1'd1;
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else
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h_count <= 0;
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/* vertical counter */
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always @(posedge clk)
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if (reset)
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v_count <= 0;
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else
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if (h_count == h_total - 1)
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begin
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if (v_count == v_total - 1)
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v_count <= 0;
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else
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v_count <= v_count + 1'd1;
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end
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/* field */
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always @(posedge clk)
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if (reset)
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begin
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field <= 0;
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v_total <= v_total_0;
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v_fp <= interlaced ? v_fp_1 : v_fp_0; // In the interlaced mode this value must be inverted as v_fp_1 is still in field0
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v_bp <= v_bp_0;
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v_sync <= v_sync_0;
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hv_offset <= hv_offset_0;
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end
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else
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if ((interlaced) && ((v_count == v_total - 1) && (h_count == h_total - 1)))
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begin
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field <= field + interlaced;
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v_total <= field ? v_total_0 : v_total_1;
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v_fp <= field ? v_fp_1 : v_fp_0; // This order is inverted as v_fp_1 is still in field0
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v_bp <= field ? v_bp_0 : v_bp_1;
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v_sync <= field ? v_sync_0 : v_sync_1;
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hv_offset <= field ? hv_offset_0 : hv_offset_1;
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end
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always @(posedge clk)
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if (reset)
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{ vs_out, hs_out, hde_out, vde_out, field_out } <= 4'b0;
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else begin
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hs_out <= ((h_count < h_sync));
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hde_out <= (h_count >= h_sync + h_bp) && (h_count <= h_total - h_fp - 1);
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vde_out <= (v_count >= v_sync + v_bp) && (v_count <= v_total - v_fp - 1);
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if ((v_count == 0) && (h_count == hv_offset))
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vs_out <= 1'b1;
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else if ((v_count == v_sync) && (h_count == hv_offset))
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vs_out <= 1'b0;
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/* H_COUNT_OUT and V_COUNT_OUT */
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h_count_out <= h_count;
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if (field)
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v_count_out <= v_count + v_total_0;
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else
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v_count_out <= v_count;
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/* X and Y coords <20> for a backend pattern generator */
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x_out <= h_count - (h_sync + h_bp);
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if (interlaced)
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y_out <= { (v_count - (v_sync + v_bp)) , field };
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else
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y_out <= { 1'b0, (v_count - (v_sync + v_bp)) };
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field_out <= field;
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end
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endmodule
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