168 lines
3.6 KiB
Systemverilog
168 lines
3.6 KiB
Systemverilog
//
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//
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// Copyright (c) 2017 Sorgelig
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//
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// This program is GPL Licensed. See COPYING for the full license.
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//
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//
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////////////////////////////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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//
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// LINE_LENGTH: Length of display line in pixels
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// Usually it's length from HSync to HSync.
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// May be less if line_start is used.
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//
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// HALF_DEPTH: If =1 then color dept is 4 bits per component
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// For half depth 8 bits monochrome is available with
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// mono signal enabled and color = {G, R}
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module video_mixer
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#(
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parameter LINE_LENGTH = 768,
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parameter HALF_DEPTH = 0
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)
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(
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// master clock
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// it should be multiple by (ce_pix*4).
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input clk_sys,
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// Pixel clock or clock_enable (both are accepted).
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input ce_pix,
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output ce_pix_out,
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input scandoubler,
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// scanlines (00-none 01-25% 10-50% 11-75%)
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input [1:0] scanlines,
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// High quality 2x scaling
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input hq2x,
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// color
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input [DWIDTH:0] R,
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input [DWIDTH:0] G,
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input [DWIDTH:0] B,
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// Monochrome mode (for HALF_DEPTH only)
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input mono,
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// Positive pulses.
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input HSync,
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input VSync,
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input HBlank,
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input VBlank,
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// video output signals
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output reg [7:0] VGA_R,
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output reg [7:0] VGA_G,
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output reg [7:0] VGA_B,
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output reg VGA_VS,
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output reg VGA_HS,
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output reg VGA_DE
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);
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localparam DWIDTH = HALF_DEPTH ? 3 : 7;
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wire [DWIDTH:0] R_sd;
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wire [DWIDTH:0] G_sd;
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wire [DWIDTH:0] B_sd;
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wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd;
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scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) sd
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(
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.*,
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.hs_in(HSync),
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.vs_in(VSync),
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.hb_in(HBlank),
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.vb_in(VBlank),
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.r_in(R),
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.g_in(G),
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.b_in(B),
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.ce_pix_out(ce_pix_sd),
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.hs_out(hs_sd),
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.vs_out(vs_sd),
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.hb_out(hb_sd),
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.vb_out(vb_sd),
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.r_out(R_sd),
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.g_out(G_sd),
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.b_out(B_sd)
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);
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wire [DWIDTH:0] rt = (scandoubler ? R_sd : R);
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wire [DWIDTH:0] gt = (scandoubler ? G_sd : G);
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wire [DWIDTH:0] bt = (scandoubler ? B_sd : B);
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generate
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if(HALF_DEPTH) begin
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wire [7:0] r = mono ? {gt,rt} : {rt,rt};
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wire [7:0] g = mono ? {gt,rt} : {gt,gt};
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wire [7:0] b = mono ? {gt,rt} : {bt,bt};
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end else begin
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wire [7:0] r = rt;
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wire [7:0] g = gt;
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wire [7:0] b = bt;
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end
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endgenerate
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wire hs = (scandoubler ? hs_sd : HSync);
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wire vs = (scandoubler ? vs_sd : VSync);
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assign ce_pix_out = scandoubler ? ce_pix_sd : ce_pix;
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reg scanline = 0;
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always @(posedge clk_sys) begin
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reg old_hs, old_vs;
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old_hs <= hs;
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old_vs <= vs;
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if(old_hs && ~hs) scanline <= ~scanline;
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if(old_vs && ~vs) scanline <= 0;
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end
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wire hde = scandoubler ? ~hb_sd : ~HBlank;
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wire vde = scandoubler ? ~vb_sd : ~VBlank;
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always @(posedge clk_sys) begin
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reg old_hde;
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case(scanlines & {scanline, scanline})
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1: begin // reduce 25% = 1/2 + 1/4
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VGA_R <= {1'b0, r[7:1]} + {2'b00, r[7:2]};
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VGA_G <= {1'b0, g[7:1]} + {2'b00, g[7:2]};
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VGA_B <= {1'b0, b[7:1]} + {2'b00, b[7:2]};
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end
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2: begin // reduce 50% = 1/2
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VGA_R <= {1'b0, r[7:1]};
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VGA_G <= {1'b0, g[7:1]};
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VGA_B <= {1'b0, b[7:1]};
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end
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3: begin // reduce 75% = 1/4
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VGA_R <= {2'b00, r[7:2]};
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VGA_G <= {2'b00, g[7:2]};
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VGA_B <= {2'b00, b[7:2]};
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end
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default: begin
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VGA_R <= r;
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VGA_G <= g;
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VGA_B <= b;
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end
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endcase
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VGA_VS <= vs;
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VGA_HS <= hs;
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old_hde <= hde;
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if(~old_hde && hde && vde) VGA_DE <= 1;
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if(old_hde && ~hde) VGA_DE <= 0;
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end
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endmodule
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