170 lines
3.4 KiB
Systemverilog
170 lines
3.4 KiB
Systemverilog
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module vip_config
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(
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input clk,
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input reset,
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input [7:0] ARX,
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input [7:0] ARY,
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output reg [8:0] address,
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output reg write,
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output reg [31:0] writedata,
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input waitrequest
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);
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//Any input video resolution up to 1920x1080 is supported.
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//Output video parameters.
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//It's good to keep 1280x720@60 resolution among all cores as most compatible resolution.
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parameter WIDTH = 1280;
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parameter HEIGHT = 720;
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parameter HFP = 110;
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parameter HBP = 220;
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parameter HS = 40;
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parameter VFP = 5;
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parameter VBP = 20;
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parameter VS = 5;
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reg [31:0] wcalc;
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reg [31:0] hcalc;
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wire [31:0] videow = (wcalc > WIDTH) ? WIDTH : wcalc;
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wire [31:0] videoh = (hcalc > HEIGHT) ? HEIGHT : hcalc;
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wire [31:0] posx = (WIDTH - videow)>>1;
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wire [31:0] posy = (HEIGHT- videoh)>>1;
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always @(posedge clk) begin
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reg [7:0] state = 0;
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reg [7:0] arx, ary;
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integer timeout = 0;
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if(reset || (!state && ((arx != ARX) || (ary != ARY)))) begin
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arx <= ARX;
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ary <= ARY;
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timeout <= 0;
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write <= 0;
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end
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else
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if(timeout < 1000000)
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begin
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timeout <= timeout + 1;
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write <= 0;
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state <= 1;
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end
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else
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if(~waitrequest && state)
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begin
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state <= state + 1'd1;
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write <= 1;
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case(state)
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01: begin
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wcalc <= (HEIGHT*arx)/ary;
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hcalc <= (WIDTH*ary)/arx;
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end
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endcase
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if(state&3) write <= 0;
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else
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case(state>>2)
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//scaler
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01: begin
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address <= 'h003; //Output Width
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writedata <= videow;
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end
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02: begin
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address <= 'h004; //Output Height
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writedata <= videoh;
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end
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03: begin
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address <= 'h000; //Go
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writedata <= 1;
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end
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//mixer
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10: begin
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address <= 'h083; //Bkg Width
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writedata <= WIDTH;
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end
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11: begin
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address <= 'h084; //Bkg Height
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writedata <= HEIGHT;
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end
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12: begin
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address <= 'h088; //Pos X
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writedata <= posx;
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end
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13: begin
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address <= 'h089; //Pos Y
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writedata <= posy;
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end
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14: begin
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address <= 'h08A; //Enable Video 0
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writedata <= 1;
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end
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15: begin
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address <= 'h080; //Go
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writedata <= 1;
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end
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//video mode
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20: begin
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address <= 'h104; //Bank
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writedata <= 0;
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end
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21: begin
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address <= 'h105; //Progressive/Interlaced
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writedata <= 0;
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end
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22: begin
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address <= 'h106; //Active pixel count
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writedata <= WIDTH;
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end
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23: begin
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address <= 'h107; //Active line count
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writedata <= HEIGHT;
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end
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24: begin
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address <= 'h109; //Horizontal Front Porch
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writedata <= HFP;
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end
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25: begin
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address <= 'h10A; //Horizontal Sync Length
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writedata <= HS;
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end
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26: begin
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address <= 'h10B; //Horizontal Blanking (HFP+HBP+HSync)
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writedata <= HFP+HBP+HS;
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end
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27: begin
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address <= 'h10C; //Vertical Front Porch
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writedata <= VFP;
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end
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28: begin
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address <= 'h10D; //Vertical Sync Length
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writedata <= VS;
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end
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29: begin
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address <= 'h10E; //Vertical blanking (VFP+VBP+VSync)
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writedata <= VFP+VBP+VS;
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end
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30: begin
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address <= 'h11E; //Valid
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writedata <= 1;
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end
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31: begin
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address <= 'h100; //Go
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writedata <= 1;
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end
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default: write <= 0;
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endcase
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end
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end
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endmodule
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