133 lines
3.0 KiB
Systemverilog
133 lines
3.0 KiB
Systemverilog
//
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// ddram.v
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//
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// DE10-nano DDR3 memory interface
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//
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// Copyright (c) 2017 Sorgelig
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ------------------------------------------
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//
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// 8-bit version
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module ddram
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(
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input reset,
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input DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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input [27:0] addr, // 256MB at the end of 1GB
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output [7:0] dout, // data output to cpu
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input [7:0] din, // data input from cpu
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input we, // cpu requests write
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input rd, // cpu requests read
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output ready // dout is valid. Ready to accept new read/write.
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);
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assign DDRAM_BURSTCNT = 1;
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assign DDRAM_BE = (8'd1<<ram_address[2:0]) | {8{ram_read}};
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assign DDRAM_ADDR = {4'b0011, ram_address[27:3]}; // RAM at 0x30000000
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assign DDRAM_RD = ram_read;
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assign DDRAM_DIN = ram_cache;
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assign DDRAM_WE = ram_write;
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assign dout = ram_q;
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assign ready = ~busy;
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reg [7:0] ram_q;
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reg [27:0] ram_address;
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reg ram_read;
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reg [63:0] ram_cache;
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reg ram_write;
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reg [7:0] cached;
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reg busy;
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always @(posedge DDRAM_CLK)
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begin
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reg old_rd, old_we;
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reg old_reset;
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reg state;
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old_reset <= reset;
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if(old_reset && ~reset)
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begin
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busy <= 0;
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state <= 0;
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cached <= 0;
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end
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if(!DDRAM_BUSY)
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begin
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ram_write <= 0;
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ram_read <= 0;
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if(state)
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begin
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if(DDRAM_DOUT_READY)
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begin
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ram_q <= DDRAM_DOUT[{ram_address[2:0], 3'b000} +:8];
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ram_cache <= DDRAM_DOUT;
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cached <= 8'hFF;
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state <= 0;
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busy <= 0;
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end
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end
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else
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begin
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old_rd <= rd;
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old_we <= we;
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busy <= 0;
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if(~old_we && we)
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begin
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ram_cache[{addr[2:0], 3'b000} +:8] <= din;
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ram_address <= addr;
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busy <= 1;
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ram_write <= 1;
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cached <= ((ram_address[27:3] == addr[27:3]) ? cached : 8'h00) | (8'd1<<addr[2:0]);
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end
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if(~old_rd && rd)
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begin
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busy <= 1;
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if((ram_address[27:3] == addr[27:3]) && (cached & (8'd1<<addr[2:0])))
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begin
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ram_q <= ram_cache[{addr[2:0], 3'b000} +:8];
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end
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else
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begin
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ram_address <= addr;
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ram_read <= 1;
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state <= 1;
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cached <= 0;
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end
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end
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end
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end
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end
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endmodule
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