242 lines
6.3 KiB
Verilog
242 lines
6.3 KiB
Verilog
`timescale 1ns/10ps
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module pll_hdmi_0002(
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// interface 'refclk'
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input wire refclk,
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// interface 'reset'
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input wire rst,
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// interface 'outclk0'
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output wire outclk_0,
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// interface 'locked'
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output wire locked,
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// interface 'reconfig_to_pll'
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input wire [63:0] reconfig_to_pll,
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// interface 'reconfig_from_pll'
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output wire [63:0] reconfig_from_pll
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);
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altera_pll #(
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.fractional_vco_multiplier("true"),
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.reference_clock_frequency("50.0 MHz"),
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.pll_fractional_cout(32),
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.pll_dsm_out_sel("1st_order"),
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.operation_mode("direct"),
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.number_of_clocks(1),
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.output_clock_frequency0("148.500000 MHz"),
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.phase_shift0("0 ps"),
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.duty_cycle0(50),
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.output_clock_frequency1("0 MHz"),
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.phase_shift1("0 ps"),
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.duty_cycle1(50),
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.output_clock_frequency2("0 MHz"),
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.phase_shift2("0 ps"),
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.duty_cycle2(50),
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.output_clock_frequency3("0 MHz"),
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.phase_shift3("0 ps"),
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.duty_cycle3(50),
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.output_clock_frequency4("0 MHz"),
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.phase_shift4("0 ps"),
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.duty_cycle4(50),
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.output_clock_frequency5("0 MHz"),
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.phase_shift5("0 ps"),
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.duty_cycle5(50),
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.output_clock_frequency6("0 MHz"),
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.phase_shift6("0 ps"),
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.duty_cycle6(50),
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.output_clock_frequency7("0 MHz"),
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.phase_shift7("0 ps"),
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.duty_cycle7(50),
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.output_clock_frequency8("0 MHz"),
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.phase_shift8("0 ps"),
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.duty_cycle8(50),
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.output_clock_frequency9("0 MHz"),
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.phase_shift9("0 ps"),
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.duty_cycle9(50),
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.output_clock_frequency10("0 MHz"),
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.phase_shift10("0 ps"),
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.duty_cycle10(50),
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.output_clock_frequency11("0 MHz"),
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.phase_shift11("0 ps"),
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.duty_cycle11(50),
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.output_clock_frequency12("0 MHz"),
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.phase_shift12("0 ps"),
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.duty_cycle12(50),
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.output_clock_frequency13("0 MHz"),
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.phase_shift13("0 ps"),
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.duty_cycle13(50),
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.output_clock_frequency14("0 MHz"),
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.phase_shift14("0 ps"),
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.duty_cycle14(50),
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.output_clock_frequency15("0 MHz"),
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.phase_shift15("0 ps"),
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.duty_cycle15(50),
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.output_clock_frequency16("0 MHz"),
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.phase_shift16("0 ps"),
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.duty_cycle16(50),
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.output_clock_frequency17("0 MHz"),
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.phase_shift17("0 ps"),
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.duty_cycle17(50),
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.pll_type("Cyclone V"),
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.pll_subtype("Reconfigurable"),
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.m_cnt_hi_div(4),
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.m_cnt_lo_div(4),
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.n_cnt_hi_div(256),
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.n_cnt_lo_div(256),
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.m_cnt_bypass_en("false"),
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.n_cnt_bypass_en("true"),
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.m_cnt_odd_div_duty_en("false"),
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.n_cnt_odd_div_duty_en("false"),
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.c_cnt_hi_div0(2),
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.c_cnt_lo_div0(1),
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.c_cnt_prst0(1),
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.c_cnt_ph_mux_prst0(0),
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.c_cnt_in_src0("ph_mux_clk"),
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.c_cnt_bypass_en0("false"),
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.c_cnt_odd_div_duty_en0("true"),
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.c_cnt_hi_div1(1),
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.c_cnt_lo_div1(1),
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.c_cnt_prst1(1),
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.c_cnt_ph_mux_prst1(0),
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.c_cnt_in_src1("ph_mux_clk"),
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.c_cnt_bypass_en1("true"),
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.c_cnt_odd_div_duty_en1("false"),
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.c_cnt_hi_div2(1),
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.c_cnt_lo_div2(1),
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.c_cnt_prst2(1),
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.c_cnt_ph_mux_prst2(0),
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.c_cnt_in_src2("ph_mux_clk"),
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.c_cnt_bypass_en2("true"),
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.c_cnt_odd_div_duty_en2("false"),
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.c_cnt_hi_div3(1),
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.c_cnt_lo_div3(1),
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.c_cnt_prst3(1),
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.c_cnt_ph_mux_prst3(0),
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.c_cnt_in_src3("ph_mux_clk"),
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.c_cnt_bypass_en3("true"),
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.c_cnt_odd_div_duty_en3("false"),
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.c_cnt_hi_div4(1),
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.c_cnt_lo_div4(1),
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.c_cnt_prst4(1),
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.c_cnt_ph_mux_prst4(0),
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.c_cnt_in_src4("ph_mux_clk"),
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.c_cnt_bypass_en4("true"),
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.c_cnt_odd_div_duty_en4("false"),
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.c_cnt_hi_div5(1),
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.c_cnt_lo_div5(1),
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.c_cnt_prst5(1),
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.c_cnt_ph_mux_prst5(0),
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.c_cnt_in_src5("ph_mux_clk"),
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.c_cnt_bypass_en5("true"),
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.c_cnt_odd_div_duty_en5("false"),
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.c_cnt_hi_div6(1),
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.c_cnt_lo_div6(1),
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.c_cnt_prst6(1),
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.c_cnt_ph_mux_prst6(0),
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.c_cnt_in_src6("ph_mux_clk"),
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.c_cnt_bypass_en6("true"),
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.c_cnt_odd_div_duty_en6("false"),
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.c_cnt_hi_div7(1),
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.c_cnt_lo_div7(1),
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.c_cnt_prst7(1),
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.c_cnt_ph_mux_prst7(0),
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.c_cnt_in_src7("ph_mux_clk"),
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.c_cnt_bypass_en7("true"),
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.c_cnt_odd_div_duty_en7("false"),
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.c_cnt_hi_div8(1),
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.c_cnt_lo_div8(1),
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.c_cnt_prst8(1),
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.c_cnt_ph_mux_prst8(0),
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.c_cnt_in_src8("ph_mux_clk"),
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.c_cnt_bypass_en8("true"),
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.c_cnt_odd_div_duty_en8("false"),
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.c_cnt_hi_div9(1),
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.c_cnt_lo_div9(1),
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.c_cnt_prst9(1),
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.c_cnt_ph_mux_prst9(0),
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.c_cnt_in_src9("ph_mux_clk"),
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.c_cnt_bypass_en9("true"),
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.c_cnt_odd_div_duty_en9("false"),
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.c_cnt_hi_div10(1),
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.c_cnt_lo_div10(1),
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.c_cnt_prst10(1),
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.c_cnt_ph_mux_prst10(0),
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.c_cnt_in_src10("ph_mux_clk"),
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.c_cnt_bypass_en10("true"),
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.c_cnt_odd_div_duty_en10("false"),
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.c_cnt_hi_div11(1),
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.c_cnt_lo_div11(1),
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.c_cnt_prst11(1),
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.c_cnt_ph_mux_prst11(0),
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.c_cnt_in_src11("ph_mux_clk"),
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.c_cnt_bypass_en11("true"),
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.c_cnt_odd_div_duty_en11("false"),
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.c_cnt_hi_div12(1),
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.c_cnt_lo_div12(1),
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.c_cnt_prst12(1),
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.c_cnt_ph_mux_prst12(0),
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.c_cnt_in_src12("ph_mux_clk"),
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.c_cnt_bypass_en12("true"),
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.c_cnt_odd_div_duty_en12("false"),
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.c_cnt_hi_div13(1),
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.c_cnt_lo_div13(1),
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.c_cnt_prst13(1),
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.c_cnt_ph_mux_prst13(0),
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.c_cnt_in_src13("ph_mux_clk"),
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.c_cnt_bypass_en13("true"),
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.c_cnt_odd_div_duty_en13("false"),
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.c_cnt_hi_div14(1),
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.c_cnt_lo_div14(1),
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.c_cnt_prst14(1),
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.c_cnt_ph_mux_prst14(0),
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.c_cnt_in_src14("ph_mux_clk"),
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.c_cnt_bypass_en14("true"),
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.c_cnt_odd_div_duty_en14("false"),
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.c_cnt_hi_div15(1),
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.c_cnt_lo_div15(1),
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.c_cnt_prst15(1),
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.c_cnt_ph_mux_prst15(0),
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.c_cnt_in_src15("ph_mux_clk"),
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.c_cnt_bypass_en15("true"),
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.c_cnt_odd_div_duty_en15("false"),
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.c_cnt_hi_div16(1),
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.c_cnt_lo_div16(1),
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.c_cnt_prst16(1),
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.c_cnt_ph_mux_prst16(0),
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.c_cnt_in_src16("ph_mux_clk"),
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.c_cnt_bypass_en16("true"),
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.c_cnt_odd_div_duty_en16("false"),
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.c_cnt_hi_div17(1),
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.c_cnt_lo_div17(1),
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.c_cnt_prst17(1),
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.c_cnt_ph_mux_prst17(0),
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.c_cnt_in_src17("ph_mux_clk"),
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.c_cnt_bypass_en17("true"),
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.c_cnt_odd_div_duty_en17("false"),
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.pll_vco_div(2),
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.pll_cp_current(20),
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.pll_bwctrl(4000),
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.pll_output_clk_frequency("445.499999 MHz"),
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.pll_fractional_division("3908420153"),
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.mimic_fbclk_type("none"),
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.pll_fbclk_mux_1("glb"),
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.pll_fbclk_mux_2("m_cnt"),
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.pll_m_cnt_in_src("ph_mux_clk"),
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.pll_slf_rst("true")
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) altera_pll_i (
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.rst (rst),
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.outclk ({outclk_0}),
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.locked (locked),
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.reconfig_to_pll (reconfig_to_pll),
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.fboutclk ( ),
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.fbclk (1'b0),
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.refclk (refclk),
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.reconfig_from_pll (reconfig_from_pll)
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);
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endmodule
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