308 lines
7.1 KiB
Systemverilog
308 lines
7.1 KiB
Systemverilog
//============================================================================
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// Apple II+
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//
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// Port to MiSTer
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// Copyright (C) 2017 Sorgelig
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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// more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with this program; if not, write to the Free Software Foundation, Inc.,
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// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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//============================================================================
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module emu
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(
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//Master input clock
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input CLK_50M,
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//Async reset from top-level module.
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//Can be used as initial reset.
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input RESET,
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//Must be passed to hps_io module
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inout [43:0] HPS_BUS,
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//Base video clock. Usually equals to CLK_SYS.
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output CLK_VIDEO,
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//Multiple resolutions are supported using different CE_PIXEL rates.
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//Must be based on CLK_VIDEO
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output CE_PIXEL,
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//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
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output [7:0] VIDEO_ARX,
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output [7:0] VIDEO_ARY,
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output [7:0] VGA_R,
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output [7:0] VGA_G,
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output [7:0] VGA_B,
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output VGA_HS,
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output VGA_VS,
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output VGA_DE, // = ~(VBlank | HBlank)
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output LED_USER, // 1 - ON, 0 - OFF.
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// b[1]: 0 - LED status is system status ORed with b[0]
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// 1 - LED status is controled solely by b[0]
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// hint: supply 2'b00 to let the system control the LED.
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output [1:0] LED_POWER,
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output [1:0] LED_DISK,
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output [15:0] AUDIO_L,
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output [15:0] AUDIO_R,
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output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
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input TAPE_IN,
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// SD-SPI
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output SD_SCK,
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output SD_MOSI,
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input SD_MISO,
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output SD_CS,
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//High latency DDR3 RAM interface
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//Use for non-critical time purposes
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output DDRAM_CLK,
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input DDRAM_BUSY,
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output [7:0] DDRAM_BURSTCNT,
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output [28:0] DDRAM_ADDR,
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input [63:0] DDRAM_DOUT,
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input DDRAM_DOUT_READY,
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output DDRAM_RD,
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output [63:0] DDRAM_DIN,
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output [7:0] DDRAM_BE,
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output DDRAM_WE,
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//SDRAM interface with lower latency
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output SDRAM_CLK,
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output SDRAM_CKE,
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output [12:0] SDRAM_A,
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output [1:0] SDRAM_BA,
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inout [15:0] SDRAM_DQ,
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output SDRAM_DQML,
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output SDRAM_DQMH,
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output SDRAM_nCS,
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output SDRAM_nCAS,
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output SDRAM_nRAS,
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output SDRAM_nWE
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);
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assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
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assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
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assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
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assign LED_USER = led;
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assign LED_DISK = 0;
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assign LED_POWER = 0;
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assign VIDEO_ARX = status[1] ? 8'd16 : 8'd4;
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assign VIDEO_ARY = status[1] ? 8'd9 : 8'd3;
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`include "build_id.v"
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parameter CONF_STR = {
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"Apple-II;;",
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"-;",
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"S,NIB;",
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"-;",
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"O1,Aspect ratio,4:3,16:9;",
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"O23,Display,Color,B&W,Green,Amber;",
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"-;",
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"O4,Mocking board,Yes,No;",
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"-;",
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"T6,Reset;",
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"J,Fire 1,Fire 2;",
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"V,v1.01.",`BUILD_DATE
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};
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///////////////// CLOCKS ////////////////////////
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wire clk_ram, clk_sys, clk_fdd, clk_vid;
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wire pll_locked;
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pll pll
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(
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.refclk(CLK_50M),
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.rst(0),
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.outclk_0(clk_vid),
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.outclk_1(clk_sys),
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.locked(pll_locked)
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);
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///////////////// HPS ///////////////////////////
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wire [31:0] status;
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wire [1:0] buttons;
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wire [15:0] joystick_0, joystick_1;
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wire [15:0] joystick_a0, joystick_a1;
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wire [5:0] joy = (joystick_0[5:0] | joystick_1[5:0]) & {2'b11, {4{~joya_en}}};
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wire [15:0] joya = joystick_a0 ? joystick_a0 : joystick_a1;
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wire joya_en = |joya;
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wire ps2_kbd_clk_out;
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wire ps2_kbd_data_out;
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reg [31:0] sd_lba;
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reg sd_rd;
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wire sd_ack;
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wire [8:0] sd_buff_addr;
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wire [7:0] sd_buff_dout;
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wire sd_buff_wr;
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wire img_mounted;
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wire [63:0] img_size;
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hps_io #(.STRLEN($size(CONF_STR)>>3)) hps_io
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(
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.clk_sys(clk_sys),
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.HPS_BUS(HPS_BUS),
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.conf_str(CONF_STR),
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.buttons(buttons),
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.status(status),
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.sd_lba(sd_lba),
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.sd_rd(sd_rd),
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.sd_wr(0),
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.sd_ack(sd_ack),
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.sd_buff_addr(sd_buff_addr),
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.sd_buff_dout(sd_buff_dout),
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.sd_buff_din(0),
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.sd_buff_wr(sd_buff_wr),
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.img_mounted(img_mounted),
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.img_size(img_size),
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.ioctl_wait(0),
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.ps2_kbd_clk_out(ps2_kbd_clk_out),
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.ps2_kbd_data_out(ps2_kbd_data_out),
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.joystick_0(joystick_0),
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.joystick_1(joystick_1),
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.joystick_analog_0(joystick_a0),
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.joystick_analog_1(joystick_a1)
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);
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///////////////// RESET /////////////////////////
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wire reset = RESET | status[0] | buttons[1] | status[6];
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///////////////////////////////////////////////////
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wire [7:0] audio_l, audio_r;
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wire speaker;
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assign AUDIO_L = {1'b0, audio_l, 7'd0} + {2'b0, speaker, 13'd0};
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assign AUDIO_R = {1'b0, audio_r, 7'd0} + {2'b0, speaker, 13'd0};
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assign AUDIO_S = 0;
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assign CLK_VIDEO = clk_vid;
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assign CE_PIXEL = 1;
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wire led;
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apple2_top apple2_top
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(
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.CLK_28M(clk_vid),
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.CLK_14M(clk_sys),
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.CPU_WAIT(cpu_wait),
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.reset_in(reset),
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.VGA_DE(VGA_DE),
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.VGA_HS(VGA_HS),
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.VGA_VS(VGA_VS),
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.VGA_R(VGA_R),
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.VGA_G(VGA_G),
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.VGA_B(VGA_B),
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.SCREEN_MODE(status[3:2]),
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.AUDIO_L(audio_l),
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.AUDIO_R(audio_r),
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.SPEAKER(speaker),
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.ps2Clk(ps2_kbd_clk_out),
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.ps2Data(ps2_kbd_data_out),
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.joy(joy),
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.joy_an(joya),
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.mb_enabled(~status[4]),
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.TRACK(track),
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.TRACK_RAM_ADDR({track_sec, sd_buff_addr}),
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.TRACK_RAM_DI(sd_buff_dout),
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.TRACK_RAM_WE(sd_buff_wr),
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.ram_addr(ram_addr),
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.ram_dout(ram_dout),
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.ram_din(ram_din),
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.ram_we(ram_we),
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.LED(led)
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);
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wire [17:0] ram_addr;
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reg [7:0] ram_dout;
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wire [7:0] ram_din;
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wire ram_we;
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reg [7:0] ram[262144]; //om-nom-nom :)
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always @(posedge clk_sys) begin
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if(ram_we) begin
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ram[ram_addr] <= ram_din;
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ram_dout <= ram_din;
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end else begin
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ram_dout <= ram[ram_addr];
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end
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end
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wire [5:0] track;
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reg [3:0] track_sec;
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reg cpu_wait = 0;
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always @(posedge clk_sys) begin
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reg [2:0] state = 0;
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reg [5:0] cur_track;
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reg mounted = 0;
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reg old_ack = 0;
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old_ack <= sd_ack;
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mounted <= mounted | img_mounted;
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case(state)
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0: if((cur_track != track) || (mounted && ~img_mounted)) begin
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cur_track <= track;
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mounted <= 0;
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if(img_size) begin
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track_sec <= 0;
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sd_lba <= 13 * track;
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state <= 1;
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sd_rd <= 1;
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cpu_wait <= 1;
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end
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end
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1: if(~old_ack & sd_ack) begin
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if(track_sec >= 12) sd_rd <= 0;
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sd_lba <= sd_lba + 1'd1;
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end else if(old_ack & ~sd_ack) begin
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track_sec <= track_sec + 1'd1;
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if(~sd_rd) state <= 0;
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cpu_wait <= 0;
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end
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endcase
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end
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endmodule
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