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Mockingboard: only do multi-TIMER1 support update when 6502 interrupts are enabled. (#685)
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@ -188,6 +188,11 @@ void SetActiveCpu(eCpuType cpu)
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g_ActiveCPU = cpu;
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}
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bool Is6502InterruptEnabled(void)
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{
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return !(regs.ps & AF_INTERRUPT);
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}
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//
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#include "CPU/cpu_general.inl"
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@ -42,3 +42,5 @@ eCpuType ProbeMainCpuDefault(eApple2Type apple2Type);
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void SetMainCpuDefault(eApple2Type apple2Type);
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eCpuType GetActiveCpu(void);
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void SetActiveCpu(eCpuType cpu);
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bool Is6502InterruptEnabled(void);
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@ -1797,7 +1797,7 @@ static bool CheckTimerUnderflowAndIrq(USHORT& timerCounter, int& timerIrqDelay,
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// Called by:
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// . CpuExecute() every ~1000 @ 1MHz
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// . CheckInterruptSources() every 128 cycles
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// . CheckInterruptSources() every opcode (or every 40 opcodes at full-speed)
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// . MB_Read() / MB_Write()
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void MB_UpdateCycles(ULONG uExecutedCycles)
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{
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@ -1847,7 +1847,9 @@ void MB_UpdateCycles(ULONG uExecutedCycles)
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}
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else // GH#685: Multiple TIMER1 interrupts
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{
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g_waitFirstAYWriteAfterTimer1Int = true; // Defer MB_Update() until MB_Write()
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// Only allow when not in interrupt handler (ie. only allow when interrupts are enabled)
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if (Is6502InterruptEnabled())
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g_waitFirstAYWriteAfterTimer1Int = true; // Defer MB_Update() until MB_Write()
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}
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if ((pMB->sy6522.ACR & RUNMODE) == RM_ONESHOT)
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