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Split from cpu.cpp
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mpohoreski
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143
AppleWin/source/CPU/cpu_general.inl
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143
AppleWin/source/CPU/cpu_general.inl
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/*
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AppleWin : An Apple //e emulator for Windows
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Copyright (C) 1994-1996, Michael O'Brien
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Copyright (C) 1999-2001, Oliver Schmidt
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Copyright (C) 2002-2005, Tom Charlesworth
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Copyright (C) 2006-2010, Tom Charlesworth, Michael Pohoreski
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AppleWin is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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AppleWin is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with AppleWin; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* Description: 6502/65C02 emulation
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*
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* Author: Various
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*/
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/****************************************************************************
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*
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* GENERAL PURPOSE MACROS
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*
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***/
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#undef AF_TO_EF
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#undef EF_TO_AF
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#define AF_TO_EF flagc = (regs.ps & AF_CARRY); \
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flagn = (regs.ps & AF_SIGN); \
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flagv = (regs.ps & AF_OVERFLOW); \
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flagz = (regs.ps & AF_ZERO);
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#define EF_TO_AF regs.ps = (regs.ps & ~(AF_CARRY | AF_SIGN | \
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AF_OVERFLOW | AF_ZERO)) \
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| flagc \
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| flagn \
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| (flagv ? AF_OVERFLOW : 0) \
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| (flagz ? AF_ZERO : 0) \
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| AF_RESERVED | AF_BREAK;
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// CYC(a): This can be optimised, as only certain opcodes will affect uExtraCycles
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#define CYC(a) uExecutedCycles += (a)+uExtraCycles; g_nIrqCheckTimeout -= (a)+uExtraCycles;
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#define POP (*(mem+((regs.sp >= 0x1FF) ? (regs.sp = 0x100) : ++regs.sp)))
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#define PUSH(a) *(mem+regs.sp--) = (a); \
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if (regs.sp < 0x100) \
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regs.sp = 0x1FF;
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#define READ ( \
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((addr & 0xF000) == 0xC000) \
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? IORead[(addr>>4) & 0xFF](regs.pc,addr,0,0,uExecutedCycles) \
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: *(mem+addr) \
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)
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#define SETNZ(a) { \
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flagn = ((a) & 0x80); \
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flagz = !((a) & 0xFF); \
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}
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#define SETZ(a) flagz = !((a) & 0xFF);
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#define WRITE(a) { \
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memdirty[addr >> 8] = 0xFF; \
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LPBYTE page = memwrite[addr >> 8]; \
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if (page) \
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*(page+(addr & 0xFF)) = (BYTE)(a); \
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else if ((addr & 0xF000) == 0xC000) \
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IOWrite[(addr>>4) & 0xFF](regs.pc,addr,1,(BYTE)(a),uExecutedCycles); \
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}
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//
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// ExtraCycles:
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// +1 if branch taken
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// +1 if page boundary crossed
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#define BRANCH_TAKEN { \
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base = regs.pc; \
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regs.pc += addr; \
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if ((base ^ regs.pc) & 0xFF00) \
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uExtraCycles=2; \
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else \
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uExtraCycles=1; \
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}
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//
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#define CHECK_PAGE_CHANGE if (bSlowerOnPagecross) { \
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if ((base ^ addr) & 0xFF00) \
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uExtraCycles=1; \
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}
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/****************************************************************************
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*
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* ADDRESSING MODE MACROS
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*
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***/
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#define ABS addr = *(LPWORD)(mem+regs.pc); regs.pc += 2;
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#define IABSX addr = *(LPWORD)(mem+(*(LPWORD)(mem+regs.pc))+(WORD)regs.x); regs.pc += 2;
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#define ABSX base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.x; regs.pc += 2; CHECK_PAGE_CHANGE;
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#define ABSY base = *(LPWORD)(mem+regs.pc); addr = base+(WORD)regs.y; regs.pc += 2; CHECK_PAGE_CHANGE;
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#define IABSCMOS base = *(LPWORD)(mem+regs.pc); \
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addr = *(LPWORD)(mem+base); \
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if ((base & 0xFF) == 0xFF) uExtraCycles=1; \
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regs.pc += 2;
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#define IABSNMOS base = *(LPWORD)(mem+regs.pc); \
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if ((base & 0xFF) == 0xFF) \
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addr = *(mem+base)+((WORD)*(mem+(base&0xFF00))<<8);\
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else \
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addr = *(LPWORD)(mem+base); \
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regs.pc += 2;
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#define IMM addr = regs.pc++;
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#define INDX base = ((*(mem+regs.pc++))+regs.x) & 0xFF; \
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if (base == 0xFF) \
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addr = *(mem+0xFF)+(((WORD)*mem)<<8); \
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else \
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addr = *(LPWORD)(mem+base);
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#define INDY if (*(mem+regs.pc) == 0xFF) \
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base = *(mem+0xFF)+(((WORD)*mem)<<8); \
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else \
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base = *(LPWORD)(mem+*(mem+regs.pc)); \
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regs.pc++; \
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addr = base+(WORD)regs.y; \
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CHECK_PAGE_CHANGE;
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#define IZPG base = *(mem+regs.pc++); \
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if (base == 0xFF) \
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addr = *(mem+0xFF)+(((WORD)*mem)<<8); \
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else \
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addr = *(LPWORD)(mem+base);
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#define REL addr = (signed char)*(mem+regs.pc++);
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// Optimiation note:
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// . Opcodes that generate zero-page addresses can't be accessing $C000..$CFFF
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// so they could be paired with special READZP/WRITEZP macros (instead of READ/WRITE)
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#define ZPG addr = *(mem+regs.pc++);
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#define ZPGX addr = ((*(mem+regs.pc++))+regs.x) & 0xFF;
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#define ZPGY addr = ((*(mem+regs.pc++))+regs.y) & 0xFF;
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