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MB: Fix ASSERT for 6522 write (#1333)

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This commit is contained in:
tomcw 2024-10-13 18:09:21 +01:00
parent 617e2b5d16
commit 9f508d1b7e
1 changed files with 43 additions and 32 deletions
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75
source/6522.cpp
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@ -87,7 +87,6 @@ void SY6522::StopTimer1(void)
void SY6522::StartTimer2(void)
{
m_timer2Active = true;
}
void SY6522::StopTimer2(void)
@ -512,9 +511,9 @@ UINT SY6522::GetOpcodeCyclesForRead(BYTE reg)
// TODO: RMW opcodes: dec,inc,asl,lsr,rol,ror (abs16 & abs16,x) + 65C02 trb,tsb (abs16)
UINT SY6522::GetOpcodeCyclesForWrite(BYTE reg)
{
UINT opcodeCycles = 0;
BYTE opcode = 0;
bool abs16 = false;
UINT zpOpcodeCycles = 0, opcodeCycles = 0;
BYTE zpOpcode = 0, opcode = 0;
bool isZP = false, isAbs16 = false;
const BYTE opcodeMinus3 = mem[(::regs.pc - 3) & 0xffff];
const BYTE opcodeMinus2 = mem[(::regs.pc - 2) & 0xffff];
@ -525,61 +524,66 @@ UINT SY6522::GetOpcodeCyclesForWrite(BYTE reg)
{ // Eg. FT demos: CHIP, MADEF, MAD2
opcodeCycles = 4;
opcode = opcodeMinus3;
abs16 = true;
isAbs16 = true;
}
else if ((opcodeMinus3 == 0x99) || // sta abs16,y
(opcodeMinus3 == 0x9D)) // sta abs16,x
{ // Eg. Paleotronic microTracker demo
opcodeCycles = 5;
opcode = opcodeMinus3;
abs16 = true;
}
else if (opcodeMinus2 == 0x81) // sta (zp,x)
{
opcodeCycles = 6;
opcode = opcodeMinus2;
}
else if (opcodeMinus2 == 0x91) // sta (zp),y
{ // Eg. FT demos: OMT, PLS
opcodeCycles = 6;
opcode = opcodeMinus2;
}
else if (opcodeMinus2 == 0x92 && GetMainCpu() == CPU_65C02) // sta (zp) : 65C02-only
{
opcodeCycles = 5;
opcode = opcodeMinus2;
isAbs16 = true;
}
else if (opcodeMinus3 == 0x9C && GetMainCpu() == CPU_65C02) // stz abs16 : 65C02-only
{
opcodeCycles = 4;
opcode = opcodeMinus3;
abs16 = true;
isAbs16 = true;
}
else if (opcodeMinus3 == 0x9E && GetMainCpu() == CPU_65C02) // stz abs16,x : 65C02-only
{
opcodeCycles = 5;
opcode = opcodeMinus3;
abs16 = true;
isAbs16 = true;
}
else
if (opcodeMinus2 == 0x81) // sta (zp,x)
{
zpOpcodeCycles = 6;
zpOpcode = opcodeMinus2;
isZP = true;
}
else if (opcodeMinus2 == 0x91) // sta (zp),y
{ // Eg. FT demos: OMT, PLS
zpOpcodeCycles = 6;
zpOpcode = opcodeMinus2;
isZP = true;
}
else if (opcodeMinus2 == 0x92 && GetMainCpu() == CPU_65C02) // sta (zp) : 65C02-only
{
zpOpcodeCycles = 5;
zpOpcode = opcodeMinus2;
isZP = true;
}
if (!isAbs16 && !isZP) // Unsupported opcode
{
_ASSERT(0);
opcodeCycles = 0;
return 0;
}
//
WORD addr16 = 0;
WORD zpAddr16 = 0, addr16 = 0;
if (!abs16)
if (isZP)
{
BYTE zp = mem[(::regs.pc - 1) & 0xffff];
if (opcode == 0x81) zp += ::regs.x;
addr16 = (mem[zp] | (mem[(zp + 1) & 0xff] << 8));
if (opcode == 0x91) addr16 += ::regs.y;
if (zpOpcode == 0x81) zp += ::regs.x;
zpAddr16 = (mem[zp] | (mem[(zp + 1) & 0xff] << 8));
if (zpOpcode == 0x91) zpAddr16 += ::regs.y;
}
else
if (isAbs16)
{
addr16 = mem[(::regs.pc - 2) & 0xffff] | (mem[(::regs.pc - 1) & 0xffff] << 8);
if (opcode == 0x99) addr16 += ::regs.y;
@ -587,12 +591,19 @@ UINT SY6522::GetOpcodeCyclesForWrite(BYTE reg)
}
// Check we've reverse looked-up the 6502 opcode correctly
if ((addr16 & 0xF80F) != (0xC000 + reg))
const bool isZpAddrValid = (zpAddr16 & 0xF80F) == (0xC000 + reg);
const bool isAbs16AddrValid = (addr16 & 0xF80F) == (0xC000 + reg);
if ( (isZpAddrValid && isAbs16AddrValid)
|| (!isZpAddrValid && !isAbs16AddrValid) )
{
_ASSERT(0);
return 0;
}
if (isZpAddrValid && !isAbs16AddrValid)
opcodeCycles = zpOpcodeCycles;
return opcodeCycles;
}