Fixed 6522 timer interrupt which was occurring 1 cycle late (#711)
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@ -378,8 +378,6 @@ static void UpdateIFR(SY6522_AY8910* pMB, BYTE clr_ifr, BYTE set_ifr=0)
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CpuIrqDeassert(IS_6522);
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}
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#define DEFER_T1C_LOAD
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static void SY6522_Write(BYTE nDevice, BYTE nReg, BYTE nValue)
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{
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g_bMB_Active = true;
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@ -1801,6 +1799,9 @@ void MB_PeriodicUpdate(UINT executedCycles)
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static bool CheckTimerUnderflowAndIrq(USHORT& timerCounter, int& timerIrqDelay, const USHORT nClocks, bool* pTimerUnderflow=NULL)
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{
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if (nClocks == 0)
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return false;
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int oldTimer = timerCounter;
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int timer = timerCounter;
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timer -= nClocks;
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@ -1810,23 +1811,20 @@ static bool CheckTimerUnderflowAndIrq(USHORT& timerCounter, int& timerIrqDelay,
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if (timerIrqDelay) // Deal with any previous counter underflow which didn't yet result in an IRQ
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{
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timerIrqDelay -= nClocks;
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if (timerIrqDelay <= 0)
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{
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timerIrqDelay = 0;
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timerIrq = true;
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}
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// don't re-underflow if TIMER = 0xFFFF or 0xFFFE (so just return)
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_ASSERT(timerIrqDelay == 1);
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timerIrqDelay = 0;
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timerIrq = true;
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// don't re-underflow if TIMER = 0x0000 (so just return)
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}
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else if (oldTimer >= 0 && timer < 0) // Underflow occurs for 0x0000 -> 0xFFFF
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{
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if (pTimerUnderflow)
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*pTimerUnderflow = true; // Just for Willy Byte!
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if (timer < -2)
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if (timer <= -2) // TIMER = 0xFFFE (or less)
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timerIrq = true;
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else // TIMER = 0xFFFF or 0xFFFE
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timerIrqDelay = 3 + timer; // ...so 2 or 1 cycles until IRQ
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else // TIMER = 0xFFFF
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timerIrqDelay = 1; // ...so 1 cycle until IRQ
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}
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return timerIrq;
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