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SSC: Change DIPSW1's baud rate to 9600 (was 19200) & reflect this change in the help doc for SSC

This commit is contained in:
tomcw 2018-04-23 21:34:09 +01:00
parent 54d159c044
commit ba090ebcef
2 changed files with 13 additions and 8 deletions
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15
help/card-ssc.html
View File

@ -18,8 +18,8 @@
<ul>
<li>DIP SW1:
<ul>
<li>Baud rate = 19200
<li>Mode = CIC (ie. SSC)
<li>Baud rate = 9600
<li>Mode = CIC (ie. SSC's Communication Mode)
</ul>
<li>DIP SW2:
<ul>
@ -33,17 +33,22 @@
<p>Notes:</p>
<ul>
<li>The SSC emulation supports both Rx and Tx interrupts, RTS/CTS, DSR/DTR, and the undocumented 115200 baud rate.
<li>The SSC emulation supports both Rx and Tx interrupts (for both COM and TCP modes), RTS/CTS, DSR/DTR, and the undocumented 115200 baud rate.
<li>For the TCP mode it doesn't matter what baud rate, stop-bit, byte size and parity are set to.
<ul>
<li>It always uses an unthrottled data-rate of 8-bit bytes (no stop-bit, no parity).
<li>When there's an active TCP connection, then the 6551's Status register has DCD,DSR bits clear (active low), and DIPSW2 has CTS bit clear (active low). When there's no TCP connection, then all these bits are set (inactive).
</ul>
<li>The TCP mode can expose buggy Rx interrupt handling code where the 6551's Status register is read more than once in the Interrupt Service Routine (ISR).
<ul>
<li>Details: TCP mode doesn't throttle the serial data rate, so after reading the Status register (to clear the Rx interrupt) the Rx interrupt may get asserted immediately if there is more data in the TCP receive buffer, resulting in a missed interrupt (and therefore missed Rx data).
<li>Details: TCP mode doesn't throttle the serial data-rate, so after reading the Status register (to clear the Rx interrupt) the Rx interrupt may get asserted immediately if there is more data in the TCP receive buffer, resulting in a missed interrupt (and therefore missed Rx data).
</ul>
<li>The 6551's Command register's DSR (bit0) must be set, to enable interrupts (Rx, Tx) along with the respective Rx and/or Tx bits (bit3:1). This is part of the 6551 specification, but (DSR bit) has only been enforced by AppleWin since 1.27.4.
</ul>
<p>Unsupported features are:</p>
<ul>
<li>Configuring the DIP switches (not a problem, since most functions can be set in software).
<li>Can't configure the DIP switches (not a problem, since most functions can be set in software).
<li>6551 ACIA Command register: Echo mode(bit4=1) and Transmit BRK (bit3:2=3).
<li>6551 ACIA Control register: external clock (bit4=0).
<li>6551 ACIA baud rates: 50, 75, 109.92, 134.58, 150 all map to 110 baud.

6
source/SerialComms.cpp
View File

@ -47,11 +47,11 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#define TCP_SERIAL_PORT 1977
// Default: 19200-8-N-1
// Default: 9600-8-N-1
SSC_DIPSW CSuperSerialCard::m_DIPSWDefault =
{
// DIPSW1:
CBR_19200,
CBR_9600, // Use 9600, as a 1MHz Apple II can only handle up to 9600 bps [Ref.1]
FWMODE_CIC,
// DIPSW2:
@ -559,7 +559,7 @@ BYTE __stdcall CSuperSerialCard::CommControl(WORD, WORD, BYTE write, BYTE value,
// Plus running in "fast" mode) cannot handle 19.2 kbps, and even 9600
// bps on these machines requires either some highly optimised code or
// a decent buffer in the device being accessed. The faster Apples
// have no difficulty with this speed, however.
// have no difficulty with this speed, however. [Ref.1]
case 0x00: m_uBaudRate = CBR_115200; break; // Internal clk: undoc'd 115.2K (or 16x external clock)
case 0x01: // fall through [50 bps]